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[139.162.88.49]) by smtp.gmail.com with ESMTPSA id s68sm43510861pgc.5.2017.06.03.07.43.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 03 Jun 2017 07:43:28 -0700 (PDT) From: Leo Yan To: Mathieu Poirier , Will Deacon , Suzuki K Poulose , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mike Leach , Chunyan Zhang Cc: Leo Yan Subject: [PATCH v1 1/4] coresight: support panic dump functionality Date: Sat, 3 Jun 2017 22:42:53 +0800 Message-Id: <1496500976-18362-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496500976-18362-1-git-send-email-leo.yan@linaro.org> References: <1496500976-18362-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org After kernel panic happens, coresight has many useful info can be used for analysis. For example, the trace info from ETB RAM can be used to check the CPU execution flows before crash. So we can save the tracing data from sink devices, and rely on kdump to extract them from vmcore file. This patch is to add a simple framework to support panic dump functionality; it registers panic notifier, and provide the general APIs {coresight_add_panic_cb|coresight_del_panic_cb} as helper functions so any coresight device can add itself into dump list or delete as needed; usually these two functions can be used when a session is started or when it ends. When kernel panic happened, the panic notifier iterates dump list and calls every node for the device callback function to dump device specific info. Generally all the panic dump specific stuff are related to the sinks devices, so this initial version code it only supports sink devices. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/Kconfig | 10 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-panic-dump.c | 130 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 10 ++ include/linux/coresight.h | 2 + 5 files changed, 153 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-panic-dump.c -- 2.7.4 diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 8d55d6d..8890023 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -103,4 +103,14 @@ config CORESIGHT_CPU_DEBUG properly, please refer Documentation/trace/coresight-cpu-debug.txt for detailed description and the example for usage. +config CORESIGHT_PANIC_DUMP + bool "CoreSight Panic Dump driver" + depends on ARM || ARM64 + depends on CORESIGHT_LINKS_AND_SINKS + help + This driver provides panic dump functionality for coresight + devices; when kernel panic happens, we can use callback functions + to save trace data to memory. Finally can rely on kdump to extract + out these trace data from kernel dump file. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 433d590..0ac3216 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o +obj-$(CONFIG_CORESIGHT_PANIC_DUMP) += coresight-panic-dump.o diff --git a/drivers/hwtracing/coresight/coresight-panic-dump.c b/drivers/hwtracing/coresight/coresight-panic-dump.c new file mode 100644 index 0000000..23869ff --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-panic-dump.c @@ -0,0 +1,130 @@ +/* + * Copyright(C) 2017 Linaro Limited. All rights reserved. + * Author: Leo Yan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(coresight_panic_lock); +static struct list_head coresight_panic_list; +static struct notifier_block coresight_panic_nb; + +struct coresight_panic_node { + char *name; + struct coresight_device *csdev; + struct list_head list; +}; + +static int coresight_panic_notify(struct notifier_block *nb, + unsigned long mode, void *_unused) +{ + int ret = 0, err; + struct coresight_panic_node *node; + struct coresight_device *csdev; + u32 type; + + mutex_lock(&coresight_panic_lock); + + list_for_each_entry(node, &coresight_panic_list, list) { + csdev = node->csdev; + type = csdev->type; + + dev_info(&csdev->dev, "invoke panic dump...\n"); + + switch (type) { + case CORESIGHT_DEV_TYPE_SINK: + case CORESIGHT_DEV_TYPE_LINKSINK: + err = sink_ops(csdev)->panic_cb(csdev); + if (err) + ret = err; + break; + default: + dev_err(&csdev->dev, + "Unsupported type for panic dump\n"); + break; + } + } + + mutex_unlock(&coresight_panic_lock); + return ret; +} + +int coresight_add_panic_cb(struct coresight_device *csdev) +{ + struct coresight_panic_node *node; + + node = kzalloc(sizeof(struct coresight_panic_node), GFP_KERNEL); + if (!node) + return -ENOMEM; + + node->name = kstrndup(dev_name(&csdev->dev), 16, GFP_KERNEL); + if (!node->name) { + kfree(node); + return -ENOMEM; + } + node->csdev = csdev; + + mutex_lock(&coresight_panic_lock); + list_add_tail(&node->list, &coresight_panic_list); + mutex_unlock(&coresight_panic_lock); + + return 0; +} + +void coresight_del_panic_cb(struct coresight_device *csdev) +{ + struct coresight_panic_node *node; + + mutex_lock(&coresight_panic_lock); + + list_for_each_entry(node, &coresight_panic_list, list) { + if (node->csdev == csdev) { + list_del(&node->list); + kfree(node->name); + kfree(node); + mutex_unlock(&coresight_panic_lock); + return; + } + } + + dev_err(&csdev->dev, "Failed to find panic node.\n"); + mutex_unlock(&coresight_panic_lock); +} + +static int __init coresight_panic_init(void) +{ + int ret; + + INIT_LIST_HEAD(&coresight_panic_list); + + coresight_panic_nb.notifier_call = coresight_panic_notify; + ret = atomic_notifier_chain_register(&panic_notifier_list, + &coresight_panic_nb); + if (ret) + return ret; + + return 0; +} +subsys_initcall(coresight_panic_init); diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 5f662d8..e6ed3e9 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -122,4 +122,14 @@ static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } #endif +#ifdef CONFIG_CORESIGHT_PANIC_DUMP +extern int coresight_add_panic_cb(struct coresight_device *csdev); +extern void coresight_del_panic_cb(struct coresight_device *csdev); +#else +static inline int coresight_add_panic_cb(struct coresight_device *csdev) +{ return 0; } +static inline void coresight_del_panic_cb(struct coresight_device *csdev) +{ return; } +#endif + #endif diff --git a/include/linux/coresight.h b/include/linux/coresight.h index d950dad..31fcaeb 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -189,6 +189,7 @@ struct coresight_device { * @set_buffer: initialises buffer mechanic before a trace session. * @reset_buffer: finalises buffer mechanic after a trace session. * @update_buffer: update buffer pointers after a trace session. + * @panic_cb: hooks callback function for panic notifier. */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, u32 mode); @@ -205,6 +206,7 @@ struct coresight_ops_sink { void (*update_buffer)(struct coresight_device *csdev, struct perf_output_handle *handle, void *sink_config); + int (*panic_cb)(struct coresight_device *csdev); }; /** From patchwork Sat Jun 3 14:42:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 101325 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp203947qgd; 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[139.162.88.49]) by smtp.gmail.com with ESMTPSA id s68sm43510861pgc.5.2017.06.03.07.43.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 03 Jun 2017 07:43:33 -0700 (PDT) From: Leo Yan To: Mathieu Poirier , Will Deacon , Suzuki K Poulose , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mike Leach , Chunyan Zhang Cc: Leo Yan Subject: [PATCH v1 2/4] coresight: add and remove panic callback for sink Date: Sat, 3 Jun 2017 22:42:54 +0800 Message-Id: <1496500976-18362-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496500976-18362-1-git-send-email-leo.yan@linaro.org> References: <1496500976-18362-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If the sink device has panic callback function, add the panic callback node for coresight panic dump list when the sink device is enabled; also cleanup the node when the sink device is disabled. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 0c37356..5928886 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -138,6 +138,13 @@ static int coresight_enable_sink(struct coresight_device *csdev, u32 mode) if (ret) return ret; } + + /* Add kernel panic callback */ + if (sink_ops(csdev)->panic_cb) { + ret = coresight_add_panic_cb(csdev); + if (ret) + return ret; + } csdev->enable = true; } @@ -149,6 +156,10 @@ static int coresight_enable_sink(struct coresight_device *csdev, u32 mode) static void coresight_disable_sink(struct coresight_device *csdev) { if (atomic_dec_return(csdev->refcnt) == 0) { + /* Remove kernel panic callback */ + if (sink_ops(csdev)->panic_cb) + coresight_del_panic_cb(csdev); + if (sink_ops(csdev)->disable) { sink_ops(csdev)->disable(csdev); csdev->enable = false; From patchwork Sat Jun 3 14:42:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 101326 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp203949qgd; Sat, 3 Jun 2017 07:44:13 -0700 (PDT) X-Received: by 10.84.215.217 with SMTP id g25mr4416207plj.77.1496501053887; Sat, 03 Jun 2017 07:44:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496501053; cv=none; d=google.com; s=arc-20160816; b=mbGhIy+FH6vIetYvw+vsq9Ab2OfprkqC3ScpcJ2zifOWTxPj50xZXYXcgdRoIu9e9t 3ObubSLx8QZTkk5ynMnUl/4Km/x7U+f9WLdeai3mNCixvmy6pTMvjMmd7I5w83dBtaYg DAXD5+22clhVj3idB41nIO1pmb5KVgD5eit0r0It2v1We1ytYyQUUmhRSKjWlSKd4dOr py+wtLzd28S3XNMwgi2qXEl0Ua09j470+RC68dqYMiCBu8IA3Qsdk8Ith8d485RcthaJ n3UMjvULk/Sd7Sw7QM9Xkjx4WRx/ucU5nIDgN0BYuFee2MnbJu1fBLXwImZtOa33yMS/ nXQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=lf0MPX7LVbpXSwd0G7UQOFXyUslJkvCiyDFp18Fylc4=; b=zTzXRdBKo77O6AX+ITPuBUHaNVMNbHxgZilDL1Htr56TQPgDhPmZKxYVI3LLvRGkpk EFlBOwO84ljJAZ6pWhcv/cKsVA7vtPVghN/dUPGm8vRSDmBhJ0E5+bvBnz4caguBQsOU iqy9UTFq5D68yfKcLppwdVM6wmHAgxcbXDc365Dm30DsYrOgBVjYlsnzx2IpjhYzE4Kg WWmXhgiDd0NDalkb1QM7GOItL1WE+RdOq4cAwlh12Q6G1yZmbv7xm2a7HPcqxL57jOaA KPxG6ryP8SGn/tVzqqZYg26EToNoSl0AVCythHseiOePX2eYtpemL0pAjX73R6SFzqEf RcmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[139.162.88.49]) by smtp.gmail.com with ESMTPSA id s68sm43510861pgc.5.2017.06.03.07.43.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 03 Jun 2017 07:43:39 -0700 (PDT) From: Leo Yan To: Mathieu Poirier , Will Deacon , Suzuki K Poulose , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mike Leach , Chunyan Zhang Cc: Leo Yan Subject: [PATCH v1 3/4] coresight: tmc: hook panic callback for ETB/ETF Date: Sat, 3 Jun 2017 22:42:55 +0800 Message-Id: <1496500976-18362-4-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496500976-18362-1-git-send-email-leo.yan@linaro.org> References: <1496500976-18362-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The panic dump functionality has been ready, this patch is to hook panic callback function for ETB/ETF. Because the driver data structure has allocated buffer when the session started, so simply save ETB/ETF trace data into the buffer when panic happens. Below is simple usage when we connect kdump to extract trace data: - During kernel panic, tmc driver prints out below log. Dump ETB buffer 0x2000@0xffff80003bd5a180 - After get kernel dump file 'vmcore', use below command to extract ETB/ETF trace data. crash vmlinux vmcore rd 0xffff80003bd5a180 0x2000 -r cs_etb_trace.bin - Generate perf formatted file, so can be analyzed by perf tool: python perf_cs_dump_wrapper.py -i cs_etb_trace.bin -o perf.data ./perf script -v -F cpu,event,ip,sym,symoff --kallsyms ksymbol -i perf.data -k vmlinux Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index e3b9fb8..4cadbb1 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -476,6 +476,31 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, CS_LOCK(drvdata->base); } +static int tmc_panic_cb(struct coresight_device *csdev) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB && + drvdata->config_type != TMC_CONFIG_TYPE_ETF)) + return -EINVAL; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + CS_UNLOCK(drvdata->base); + + tmc_flush_and_stop(drvdata); + tmc_etb_dump_hw(drvdata); + + CS_LOCK(drvdata->base); + + dev_err(drvdata->dev, "Dump ETB buffer 0x%x@0x%p\n", + drvdata->len, drvdata->buf); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return 0; +} + static const struct coresight_ops_sink tmc_etf_sink_ops = { .enable = tmc_enable_etf_sink, .disable = tmc_disable_etf_sink, @@ -484,6 +509,7 @@ static const struct coresight_ops_sink tmc_etf_sink_ops = { .set_buffer = tmc_set_etf_buffer, .reset_buffer = tmc_reset_etf_buffer, .update_buffer = tmc_update_etf_buffer, + .panic_cb = tmc_panic_cb, }; static const struct coresight_ops_link tmc_etf_link_ops = { From patchwork Sat Jun 3 14:42:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 101327 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp203957qgd; Sat, 3 Jun 2017 07:44:14 -0700 (PDT) X-Received: by 10.98.192.134 with SMTP id g6mr11960932pfk.26.1496501054262; Sat, 03 Jun 2017 07:44:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496501054; cv=none; d=google.com; s=arc-20160816; b=t6VXBuEGPNCEZytr/7z3i/lELL7uAs1JA8fQLfUb6P+5qxGZlhyiZwB6xVcIKErrIG aNvEi/nxHBY1DAi5K7oUVrYp1vPMS7JXpBRabovKzhAur42+6AqMR8EfszIYlpdSQSDU iJrBkMRwNiJJ1wnOrZ0QWMocpuXm9DaNcDlmRS9I5cbmUBy47GYejKxTxgZrC6SK6F+9 2hgxjFjbo1LsfxNJ+HN2mhEXRlR8+Eujn1NcVwPQ4/AKy/qPBxZ0Gz4bLoVGm3yacuEf HeUhbSNTvfe30RUlumiQrR36fhAmrT+SoHoeQjHou4ZpJ7IdgXVmH60haUg13nmRcq1i STPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=3mL7U13BoT2g+Y/Krj6xL7W0FneQRf7/jf5zG6HgJ5k=; b=ojXd3snKZ0IdK+MV+wx3b+tixiLKdGnpEZIM2wS676d8WE9asQ1VUlgkapRHP0jRxo ZvwvjUx+OvJ6FNs+kSbnUZeERdv2x2UH1ee9x7sIfhz9XZfol21JS6gn3tsEA/SFCBEC 7pib5hRqWXlFFAjx0yGM/n9MiIGQmEyVkkOx8kdSk0x4WC8H+iJn4BWUHYnHCml8ooRA Vwoh+HaPcwETvKJ0AXZTmorMR61UpDd9j8PK3+BA0artfvJEtrPZkc1DjRVTEO4Z5eEy asWlZ4/7dpdsWFY0TcZceV3/uZomuNMMim0riVNv8HRiaqEpceGNwan3QS1YB7qqh7Rk Kp2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[139.162.88.49]) by smtp.gmail.com with ESMTPSA id s68sm43510861pgc.5.2017.06.03.07.43.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 03 Jun 2017 07:43:44 -0700 (PDT) From: Leo Yan To: Mathieu Poirier , Will Deacon , Suzuki K Poulose , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mike Leach , Chunyan Zhang Cc: Leo Yan Subject: [PATCH v1 4/4] coresight: etb10: hook panic callback Date: Sat, 3 Jun 2017 22:42:56 +0800 Message-Id: <1496500976-18362-5-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496500976-18362-1-git-send-email-leo.yan@linaro.org> References: <1496500976-18362-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch is to hook panic callback for etb10 driver; so after panic can dump trace data from it. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-etb10.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 979ea6e..c9ea281 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -473,6 +473,21 @@ static void etb_update_buffer(struct coresight_device *csdev, CS_LOCK(drvdata->base); } +static int etb_panic_cb(struct coresight_device *csdev) +{ + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + etb_disable_hw(drvdata); + etb_dump_hw(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + dev_err(drvdata->dev, "Dump ETB buffer 0x%x@0x%p\n", + drvdata->buffer_depth, drvdata->buf); + return 0; +} + static const struct coresight_ops_sink etb_sink_ops = { .enable = etb_enable, .disable = etb_disable, @@ -481,6 +496,7 @@ static const struct coresight_ops_sink etb_sink_ops = { .set_buffer = etb_set_buffer, .reset_buffer = etb_reset_buffer, .update_buffer = etb_update_buffer, + .panic_cb = etb_panic_cb, }; static const struct coresight_ops etb_cs_ops = {