From patchwork Fri Apr 29 11:43:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 568243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C4F2C433FE for ; Fri, 29 Apr 2022 11:43:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358250AbiD2Lqx (ORCPT ); Fri, 29 Apr 2022 07:46:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358073AbiD2Lqw (ORCPT ); Fri, 29 Apr 2022 07:46:52 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C32AB252AB; Fri, 29 Apr 2022 04:43:34 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id x18so10481340wrc.0; Fri, 29 Apr 2022 04:43:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=noiLEGjS69TNqfsR+PPtmcT72BXbzXlEteGUOjRdti4=; b=VBCT5w1S0mXJE2U2KRraF7W92VzzhpTIuk/ertQoUbVYS6V+zNOL/nC3B4Taz2fGIq 3Tc/0cnzp082Zxar3Q/FWb9rgXdmmmT1ipDxYlxmQgKMfRzHTZCh1wzvBRy7lEmL89Wv jthJtdv/9NLhlkTlkCJmP2G/qYS4i7VTGIec0/gipIVHy5JiF53Hmxl4SzmlX33RWnvF SfV1sxWgJa4Hj+cdzESUhBUXblaYGwLWZGKy+32z8PpIfpEjQmvlZO/mxFcwlXr/zlgS a9UztJBAFJSHXfT83Evm3497rnkjzZs32CrHndY9uS0Mez35COZnKz5vUQjXdcUyCc4i +BCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=noiLEGjS69TNqfsR+PPtmcT72BXbzXlEteGUOjRdti4=; b=OdPA5Tk2qxpOepY+p6fEUUZR1pY65SAeu4aGkFwcrG4/Sll3zZ3lNEEpkA7w5RJYVe yEdAvx9+Ja9mwsLGWf/5JS4Pu6ReSbdc180CZ+kggWgLvLkiDaYXMNY0r1fQloN2apGx U4WtRKWpTG+R1ByIjwK8fPPIxIhCK8qxc4OdVZmyNndy6pFHIwBiYJUKN4YI8v5FgVJS 46gJqO3LwD4cQRdCQAUqvcXVd1AMFjuK6luHr22lXSDII7e3qRlrW+mXP7M7nGf3Qtm+ mEruR2GOIg3ql2143SLIm5uXvedK3cD72jZ0kxO6tV3J04osEsM5zQ+8Oa0cIwRzNpPJ 52VA== X-Gm-Message-State: AOAM531Lvq3AEOT2ejDqvJakIOzbeFvmTIjzyyXW2ckJfNArAELr8K/Y YKoi13QAynSBms3AvUsVCYo= X-Google-Smtp-Source: ABdhPJy8R+fDWCVWIT8z/71l8GYePMC7jBJ8hyQmGdE9wl+d1vgnwHXdLIyUlbQ1WNfE9YmD9FTuVQ== X-Received: by 2002:a5d:498d:0:b0:20a:dc6b:35c9 with SMTP id r13-20020a5d498d000000b0020adc6b35c9mr19684389wrq.176.1651232613260; Fri, 29 Apr 2022 04:43:33 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-183.xnet.hr. [88.207.99.183]) by smtp.googlemail.com with ESMTPSA id l6-20020a1c2506000000b0038e6fe8e8d8sm2990900wml.5.2022.04.29.04.43.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:43:32 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH 1/6] clk: qcom: clk-alpha-pll: add support for APSS PLL Date: Fri, 29 Apr 2022 13:43:25 +0200 Message-Id: <20220429114330.59026-1-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APSS PLL type will be used by the IPQ8074 APSS driver for providing the CPU core clocks and enabling CPU Frequency scaling. This is ported from the downstream 5.4 kernel. Signed-off-by: Robert Marko --- drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4406cf609aae..8270363ff98e 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_APSS] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0xff, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0xff, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6e9907deaf30..626fdf80336d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_APSS, CLK_ALPHA_PLL_TYPE_MAX, }; From patchwork Fri Apr 29 11:43:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 567571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A9DAC433EF for ; Fri, 29 Apr 2022 11:43:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358613AbiD2Lqy (ORCPT ); Fri, 29 Apr 2022 07:46:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358599AbiD2Lqy (ORCPT ); Fri, 29 Apr 2022 07:46:54 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5729F252AB; Fri, 29 Apr 2022 04:43:36 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id e24so10413219wrc.9; Fri, 29 Apr 2022 04:43:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d8OkAwRbkHWcFbANoUbxBUbD6cV4qvLXIuN4HbbAMGs=; b=Ut1dlQTh4t1c+ch6/VG1doi1BCn9s5DjSLJp2RkSj4rpQ16ngBJEaOA5tm9IO4oo5U 89l3qqVRK2PCI0vqycKRPuD4yk5zMibBIjf9C/MGFsSkLsgI5nyqnE7NHNvm1Yog5+DM W4jgiq7dwp88dsP9MeHbHmPP/jy3sW6RDCtQ1va8NxMmotTGV8g9CyVstkKoNz4ryetp /hjLSECGo6tX72hCzcYx09bXn8MWtRDZ3Q0eh0KPJr+GCYad1GvKoGey7iXTfFN827IL dakKOcKLeedLDMw7wYrJdJ5qJAkvabFOijIu5falxMpDK3oMC9eltOEvHmrl3+f+l4Gc 5P0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d8OkAwRbkHWcFbANoUbxBUbD6cV4qvLXIuN4HbbAMGs=; b=0Js/e/3SnGDP7FwCCQHO1tCPWPmIOBw2mpSuqkgzwK7j15E3B3SxISWwhf12i9KacL 6hz9YTIzG/q24bIL8qqieC6RgocLf3EwffvhagmXnu3MLYqW4t2I3XYkA9HkvdMnKxQn ywLr5L84+xL+ZbgC7aZ0/FwGUETIyaBvjE747eIPn0h/KAyKCsknroUAeQAtwZQ3+PyD KU2DwLKB1zs8DK/+Io6nh3apnNOa2cOp8N+5NJSSei0xp4uLyTRyWN/817XenFLZTX8A x7j1Tcjyr22dbwz6DRhzeAKmU5GhR5lPTklxmjbnPCNVVsHe1pkoLmRvjvwdqEq4rC5m s8QQ== X-Gm-Message-State: AOAM530wQGTft/JRgkzeR7ue7M7UPvPGblpZCTmkgKQv/MVJ/ExX+njo OjJ19UjJoXSNnU/Vj1zRZIQ= X-Google-Smtp-Source: ABdhPJwaMbSZi7RDy5+PiQ0JDW5YF7MWEubEQcP5zGT6WmDaJN4YKChkvRDEsNdTZrPNxUbZCBrN9A== X-Received: by 2002:a5d:584f:0:b0:20a:83aa:ad2a with SMTP id i15-20020a5d584f000000b0020a83aaad2amr31244602wrf.610.1651232614808; Fri, 29 Apr 2022 04:43:34 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-183.xnet.hr. [88.207.99.183]) by smtp.googlemail.com with ESMTPSA id l6-20020a1c2506000000b0038e6fe8e8d8sm2990900wml.5.2022.04.29.04.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:43:34 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/6] clk: qcom: Add DT bindings for IPQ8074 APSS clock controller Date: Fri, 29 Apr 2022 13:43:26 +0200 Message-Id: <20220429114330.59026-2-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429114330.59026-1-robimarko@gmail.com> References: <20220429114330.59026-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DT-binding for the IPQ8074 APSS clock controller. Signed-off-by: Robert Marko --- include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq8074.h b/include/dt-bindings/clock/qcom,apss-ipq8074.h new file mode 100644 index 000000000000..df07766b0146 --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq8074.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H + +#define APSS_PLL_EARLY 0 +#define APSS_PLL 1 +#define APCS_ALIAS0_CLK_SRC 2 +#define APCS_ALIAS0_CORE_CLK 3 + +#endif From patchwork Fri Apr 29 11:43:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 567570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F09AC433FE for ; Fri, 29 Apr 2022 11:43:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358654AbiD2LrB (ORCPT ); Fri, 29 Apr 2022 07:47:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358629AbiD2Lq4 (ORCPT ); Fri, 29 Apr 2022 07:46:56 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D10B6B36A8; Fri, 29 Apr 2022 04:43:37 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id d5so10434578wrb.6; Fri, 29 Apr 2022 04:43:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uiv+eJ0PX4idMh1j62/T7g+AmF3uDQ8Ole73fVdj848=; b=Q6A1ie/U+V39l6JGVP9D1AxlWc7lhnXJs7WSZymyNiAja3BLEbfzAWlvJlotNvye9U Ji7AdmJqylWkc/VP6rrAA3E+uOab0wz5bdm9T2YS3LFygnHsAGuvV1QXs9MlbKfvR5i1 khk6pRrnpHuKjbSgLBPoMKRhNPudjVbXR6h99VfsAOIgWWnrA2KWKWHaAW5RcIkDCwG7 TlPd9out9zAv+ZBK/BKJKW3S0fgp7nlMYzNTWrCnI41WZpRCU1rbHAqIdFJJclcs37U2 l7dSh+dVVgb898B7O89hElUFOj9f7R4XuDRkmVUZZnZOKqS6p5ZvB8auqUV3OiMItKSl 2h1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uiv+eJ0PX4idMh1j62/T7g+AmF3uDQ8Ole73fVdj848=; b=fHvl6NbWbkTtDbZCEhjej7h5rHpj5eaxitu0zjTOUgIr7RYQxRBYnZ+r1c89WpGlIA zG+KxHoLsbj/OcTka7xK6ytTohPhzWvFYFEqKeCtdvgtOr1iFVk4ozwjy1Dcwn0j/R+H Ulpf1uzPJ41w/eCKIpOwGy6Von+nP4N/zu/ymte2to1FrAUUKbTJ/8XGFDg1j2+BjVYP ZKqgIAz3+SxGTdK5jtkjsf+HGS64O/lWMvv30NwUQyhPNXfFXrnkh02XSVyZh2OHpv/V xwVt0ABrt510ofgg5COdxDMrclzG117xDRApLpCIhWQ74LmhlAavttgGgToLxnPSe1M7 T0kg== X-Gm-Message-State: AOAM532x+MdlaIUaVnSETR1QZK25Vs2k5VXKy94MfH9HONZwmjI/Fz1B QPDr83guDoSBWMQZDCrAua4= X-Google-Smtp-Source: ABdhPJx75CpRrB/NoRLYcOqS+eCw2ZGGkuXWHWJ8Y9RBsGEMOpSfbfBf5hRIET4Oo3xlIIdoMiNeXw== X-Received: by 2002:a5d:610b:0:b0:20a:e00b:5e46 with SMTP id v11-20020a5d610b000000b0020ae00b5e46mr17685305wrt.293.1651232616365; Fri, 29 Apr 2022 04:43:36 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-183.xnet.hr. [88.207.99.183]) by smtp.googlemail.com with ESMTPSA id l6-20020a1c2506000000b0038e6fe8e8d8sm2990900wml.5.2022.04.29.04.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:43:35 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH 3/6] clk: qcom: Add IPQ8074 APSS clock controller Date: Fri, 29 Apr 2022 13:43:27 +0200 Message-Id: <20220429114330.59026-3-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429114330.59026-1-robimarko@gmail.com> References: <20220429114330.59026-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU cores, thus also providing support for CPU frequency scaling. It looks like they are clocked by the XO and a custom APSS type PLL. Signed-off-by: Robert Marko --- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq8074.c | 170 ++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq8074.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d01436be6d7a..ea2ecb062563 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -134,6 +134,17 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_APSS_8074 + tristate "IPQ8074 APSS Clock Controller" + select IPQ_GCC_8074 + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for APSS clock controller on IPQ8074 platforms. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + IPQ8074 based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 671cf5821af1..7b2da6dd570c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o diff --git a/drivers/clk/qcom/apss-ipq8074.c b/drivers/clk/qcom/apss-ipq8074.c new file mode 100644 index 000000000000..7fab66606941 --- /dev/null +++ b/drivers/clk/qcom/apss-ipq8074.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +enum { + P_XO, + P_GPLL0, + P_GPLL2, + P_GPLL4, + P_APSS_PLL_EARLY, + P_APSS_PLL +}; + +static struct clk_alpha_pll apss_pll_early = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apss_pll_early", + .parent_names = (const char *[]){ + "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv apss_pll = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], + .width = 2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apss_pll", + .parent_names = (const char *[]){ "apss_pll_early" }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static const char * const parents_apcs_alias0_clk_src[] = { + "xo", + "gpll0", + "gpll2", + "gpll4", + "apss_pll", + "apss_pll_early", +}; + +static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_GPLL2, 2 }, + { P_GPLL4, 1 }, + { P_APSS_PLL, 3 }, + { P_APSS_PLL_EARLY, 5 }, +}; + +struct freq_tbl ftbl_apcs_alias0_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(403200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(806400000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1017600000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1382400000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1651200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1843200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1920000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(2208000000UL, P_APSS_PLL_EARLY, 1, 0, 0), + { } +}; + +struct clk_rcg2 apcs_alias0_clk_src = { + .cmd_rcgr = 0x0050, + .freq_tbl = ftbl_apcs_alias0_clk_src, + .hid_width = 5, + .parent_map = parents_apcs_alias0_clk_src_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_clk_src", + .parent_names = parents_apcs_alias0_clk_src, + .num_parents = 6, + .ops = &clk_rcg2_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch apcs_alias0_core_clk = { + .halt_reg = 0x0058, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x0058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_core_clk", + .parent_names = (const char *[]){ + "apcs_alias0_clk_src" + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *apss_ipq8074_clks[] = { + [APSS_PLL_EARLY] = &apss_pll_early.clkr, + [APSS_PLL] = &apss_pll.clkr, + [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, + [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, +}; + +static const struct regmap_config apss_ipq8074_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5ffc, + .fast_io = true, +}; + +static const struct qcom_cc_desc apss_ipq8074_desc = { + .config = &apss_ipq8074_regmap_config, + .clks = apss_ipq8074_clks, + .num_clks = ARRAY_SIZE(apss_ipq8074_clks), +}; + +static int apss_ipq8074_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) + return -ENODEV; + + return qcom_cc_really_probe(pdev, &apss_ipq8074_desc, regmap); +} + +static struct platform_driver apss_ipq8074_driver = { + .probe = apss_ipq8074_probe, + .driver = { + .name = "qcom,apss-ipq8074-clk", + }, +}; + +module_platform_driver(apss_ipq8074_driver); + +MODULE_DESCRIPTION("Qualcomm IPQ8074 APSS clock driver"); +MODULE_LICENSE("GPL"); From patchwork Fri Apr 29 11:43:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 568241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC93BC43219 for ; Fri, 29 Apr 2022 11:43:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358671AbiD2LrC (ORCPT ); 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[88.207.99.183]) by smtp.googlemail.com with ESMTPSA id l6-20020a1c2506000000b0038e6fe8e8d8sm2990900wml.5.2022.04.29.04.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:43:37 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH 4/6] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support Date: Fri, 29 Apr 2022 13:43:28 +0200 Message-Id: <20220429114330.59026-4-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429114330.59026-1-robimarko@gmail.com> References: <20220429114330.59026-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS clock driver. Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be updated to 0x5FFC. Signed-off-by: Robert Marko --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 80a54d81412e..b3b9debf5673 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = { .offset = 8, .clk_name = "qcom,apss-ipq6018-clk" }; +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { + .offset = 8, .clk_name = "qcom,apss-ipq8074-clk" +}; + static const struct qcom_apcs_ipc_data msm8916_apcs_data = { .offset = 8, .clk_name = "qcom-apcs-msm8916-clk" }; @@ -57,7 +61,7 @@ static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = 0x1008, + .max_register = 0x5FFC, .fast_io = true, }; @@ -142,7 +146,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) /* .data is the offset of the ipc register within the global block */ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, - { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data }, + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data }, From patchwork Fri Apr 29 11:43:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 568242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78DF7C433FE for ; Fri, 29 Apr 2022 11:43:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358633AbiD2LrA (ORCPT ); Fri, 29 Apr 2022 07:47:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358638AbiD2Lq7 (ORCPT ); Fri, 29 Apr 2022 07:46:59 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D11F2B36B8; Fri, 29 Apr 2022 04:43:40 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id e24so10413453wrc.9; Fri, 29 Apr 2022 04:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gWKXfiKxqjbcYlfe3kWZvieFF6W0RPqcnKcoAS9f6lc=; b=He+Cwlecz1hDBm2IJYt+u0ldkrGLbPIsCcCq6mBPrZGJyMKH1NVkYWUr4WX1ibdXXm vQBiuz26ZFKKmcsrnbH+4N3937pwiS7MAgOVq9+VjP03otC84nk2oQFPDpUFfULuYcib aSG+5YLEKhTPuY2RHeFMDWPUQSPn37qJmnffO4tYbOyCOA72krUNND4Dtz+1PYaxSE3x +Tj3YnJM8ehF7N8WfKNyxZa2DIksUKai58wSgA+ZKMh4zQ0wF1YwGFqvH6pyXA66Cfhp tTeHMAw2g1DEcZRaMP5JAPD5X1Fe67/bev3AhaulR0pem+oHnlDnT68F3uGd83eKzNeP hLig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gWKXfiKxqjbcYlfe3kWZvieFF6W0RPqcnKcoAS9f6lc=; b=R5mAdPyVRiMWQFCPeXCB/VBkpLJ6o47/eCkempvtFklzwnNGon/VU91CHEuRPYIZJ2 BeX/DyzeKczkceH98tqM/AMnYQxUdikkWRG3RlB5D7Hh6vU/3rOf0YiKyqXU2Psf2g/B WCtd2Omgfytl9CIVjYg6DuV3ckC/l+RrPBJDBXNoGRysdFff5ikCywtStbAeEFesbkhn 377cA9GFkCHf7Ui+gSdoIecqMLOT32VLWUnmyQDsD/LV9YgEaa3w7CsyI7fweHzMvbeE WEb0poT9MDbxiYqvw6OzHtjhibFIDecW+Gjb/F6OFJV+Jw927QVJsAuJjgDS4//UwsgH r7yg== X-Gm-Message-State: AOAM5304JWYWuOLC+fKQIUR/H5jrSoFFvcl2xqy9o+NSJZy766lFmV+S UygNZRfDIzb14x4le71d9Nc= X-Google-Smtp-Source: ABdhPJwlui24U3T83X+XjnY/lJ8e1qD5Ggmuafe91jzYtl9OMwc9D8pBqxPBhn81IJ8nQQbK49vR2g== X-Received: by 2002:adf:f64b:0:b0:20a:c685:89ee with SMTP id x11-20020adff64b000000b0020ac68589eemr28342607wrp.366.1651232619363; Fri, 29 Apr 2022 04:43:39 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-183.xnet.hr. [88.207.99.183]) by smtp.googlemail.com with ESMTPSA id l6-20020a1c2506000000b0038e6fe8e8d8sm2990900wml.5.2022.04.29.04.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:43:39 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH 5/6] dt-bindings: mailbox: set correct #clock-cells Date: Fri, 29 Apr 2022 13:43:29 +0200 Message-Id: <20220429114330.59026-5-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429114330.59026-1-robimarko@gmail.com> References: <20220429114330.59026-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ6018 and IPQ8074 require #clock-cells to be set to 1 as their APSS clock driver provides multiple clock outputs. So allow setting 1 as #clock-cells and check that its set to 1 for IPQ6018 and IPQ8074, check others for 0 as its currently. Signed-off-by: Robert Marko --- .../mailbox/qcom,apcs-kpss-global.yaml | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 3b5ba7ecc19d..1f803925867e 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -50,7 +50,7 @@ properties: const: 1 '#clock-cells': - const: 0 + enum: [0, 1] clock-names: minItems: 2 @@ -96,6 +96,22 @@ allOf: properties: clocks: maxItems: 3 + - if: + properties: + compatible: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + then: + properties: + '#clock-cells': + const: 1 + + else: + properties: + '#clock-cells': + const: 0 + examples: # Example apcs with msm8996 From patchwork Fri Apr 29 11:43:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 567569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01406C4332F for ; Fri, 29 Apr 2022 11:43:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358643AbiD2LrD (ORCPT ); Fri, 29 Apr 2022 07:47:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358626AbiD2LrA (ORCPT ); Fri, 29 Apr 2022 07:47:00 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5940FB36B0; Fri, 29 Apr 2022 04:43:42 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id j15so10460785wrb.2; Fri, 29 Apr 2022 04:43:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QAG6pPyD19LucMP6CU8bLxTFEbcMKLUH+h3BO7hHMdg=; b=XrPtIQJKdVelzjyZcDP5JYWrAupI8eZfW+4qG0MmikLOobez5/6ud+gLpdOLZq0qwz 5toAEsssrC9sqnJ4HQhGUJcYOB80r7aCIq0ahp12jO/r2k9Q0/9GFD9wz3locbaO+4Ja dDIJQ1eZ/pa6I06DOQKdfLsrH84GiyAdDTcJtVJl9onmAOaiaTmVvVUhIT3nkA76UPWw jFjnt/vJKMmieYSXzyGaOSu+lsQkhJCI1VNHvG+9wvv3T69ycqRGyR5V6Npw48QLREmb HglDsujyrC+DWR62abq5WjWN+j4ry+eIZ/iAqRth9YFKC08dQblImp1l2trLqws/awdV FMHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QAG6pPyD19LucMP6CU8bLxTFEbcMKLUH+h3BO7hHMdg=; b=QSCE2WzkjwxveiiEdkxUEJDA2CTIdSi7leihBDyrhuCvSD8P2+QncrbBDAWbH62ozl yQig5f//p1TzFBfYC9lpLxjdoy4ZgvNkkJbzNbilhLV/VxPLfLBfzU4RwiuJb0Xu2wMJ bdhUL+pTFadw20DsXfO+dPdlR8CUjY/v2IrmBEaQcWzUW+U3gp4Ud1cxjljsOG0DRrG/ q6t35olAV2GRJKsGtHnYuPP0LUGAXgoNqLz48Tvk8ptHFc99gz2J2AIvqJZr83xAP7Zq VggrTHCThjPv5lG+Q74qEXwSdn5Ftt9j7aRBQh3DuM6UdLcgTJ/A9boB5cNHU7vkmv+T TFXQ== X-Gm-Message-State: AOAM532lFkSzkomgpqPK3URnbdcEiKU616tsQAHljhnC8x40J8LQcPYF umSptQkrWZAeo6XPFxoH0eSNIz5WoPB+8w== X-Google-Smtp-Source: ABdhPJwa9zh912EeQ+Wd2W4TIvEJ8UM0h4erACtzSUOUAWGv85uWKfGiyjFUhY9MzrZxsC1K1zBUMw== X-Received: by 2002:a5d:634e:0:b0:20a:d67e:4a76 with SMTP id b14-20020a5d634e000000b0020ad67e4a76mr24094750wrw.637.1651232620918; Fri, 29 Apr 2022 04:43:40 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-183.xnet.hr. [88.207.99.183]) by smtp.googlemail.com with ESMTPSA id l6-20020a1c2506000000b0038e6fe8e8d8sm2990900wml.5.2022.04.29.04.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:43:40 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH 6/6] arm64: dts: ipq8074: update APCS node due to clock support Date: Fri, 29 Apr 2022 13:43:30 +0200 Message-Id: <20220429114330.59026-6-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429114330.59026-1-robimarko@gmail.com> References: <20220429114330.59026-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APCS now has support for providing the APSS clocks as the child device for IPQ8074, so update the DT node to reflect the expanded register space as well as add #clock-cells property as it now provides the APSS clock that will be used for CPU scaling. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5b32d141c7ae..d23b14a8d4b4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -970,8 +970,9 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ apcs_glb: mailbox@b111000 { compatible = "qcom,ipq8074-apcs-apps-global"; - reg = <0x0b111000 0x1000>; + reg = <0x0b111000 0x6000>; + #clock-cells = <1>; #mbox-cells = <1>; };