From patchwork Sun Jun 4 08:50:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 101350 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp447786qgd; Sun, 4 Jun 2017 01:50:28 -0700 (PDT) X-Received: by 10.84.198.3 with SMTP id o3mr8723610pld.60.1496566228520; Sun, 04 Jun 2017 01:50:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496566228; cv=none; d=google.com; s=arc-20160816; b=jNwopoBaGHoIrxdyoHvmMSptaNs/8rz10RsqET9ZjsRO6chzC2ZMyOHeTG7m7Np9uE Bz4HaTjw3Z1bRKtiAv4Zqy5nHyXVl+bhd9cSS3ZEsWhoWF9I8wP81g04lDlqp0QKhN9F g5HFu8eYmtu1OcLqKbT/baWLSRf3UoHejP6dBB4HGSjSLvL5IgLA7cgl4QK0xUSvr1xi UPIAG+96mAxtbpPMNf2Nx2kroaXP4LIifAEj7j91UYO7X8jlYDdMrnXewSaUUQ/kwz/j OHv/Dfdsd343tk4+4TwEghzphI9gh76LFBCeoZOGuTvW//kC8FFKZIcnhHc2xhk7B9Ho NPpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=oV0NbSIsQ4pRgefPEAKvEEDlRv0+Sn4HWHaLEyD5ll4=; b=NpWCSb8RQciDGnCZixJ3a/Fc3cMQwxQsUCmF5zaZo0i++Rxw8l9X0jjQTUnfEdX+F5 dQPIBgLBEsrLpWtDLzV5FjEF6NPYv17QOPAXJUDhdG1Uh/1BnAmF9Qr/4SS7JuvQMvXI m4vbnIJ+FZg8BFg1CnelWaPFAzt+DauWe4s3YShKqv+fouL9Mn7plRy+w7RSsEwx5GiI O9k7PJaVjoLiMyJ4iizEMkTryBizVCINQ8zWu0HzX2F79DwvU1NS45vem4ZnJ4EXPy1k 64hNffwNg3ckql0Hv7FMfmhPKLO8IhdmmitYi9fHmv8+KW9c7xZ0fCq73IG7siod5D/e XLUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.121.4]) by smtp.gmail.com with ESMTPSA id a88sm1440462ljb.54.2017.06.04.01.50.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 04 Jun 2017 01:50:22 -0700 (PDT) From: Linus Walleij To: Tejun Heo , Bartlomiej Zolnierkiewicz , linux-ide@vger.kernel.org Cc: Janos Laube , Paulius Zaleckas , linux-arm-kernel@lists.infradead.org, Hans Ulli Kroll , Florian Fainelli , Linus Walleij , devicetree@vger.kernel.org, John Feng-Hsin Chiang , Greentime Hu Subject: [PATCH 1/4 v4] ata: Add DT bindings for Faraday Technology FTIDE010 Date: Sun, 4 Jun 2017 10:50:06 +0200 Message-Id: <20170604085009.11902-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Faraday Technology FTIDE010 found in the Storlink/Storm/Cortina Systems Gemini SoC. I am not 100% sure that this part is from Faraday Technology but a lot points in that direction: - A later IDE interface called FTIDE020 exist and share some properties. - The SATA bridge has the same Built In Self Test (BIST) that the Faraday FTSATA100 seems to have, and it has version number 0100 in the device ID register, so this is very likely a FTSATA100 bundled with the FTIDE010. Cc: devicetree@vger.kernel.org Cc: John Feng-Hsin Chiang Cc: Greentime Hu Acked-by: Hans Ulli Kroll Acked-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - No changes, just resending to keep the patch set together. ChangeLog v2->v3: - No changes, just resending to keep the patch set together. ChangeLog v1->v2: - Cut the timings defintions from the device tree. Hard-code it in the driver instead, keeping the nice layout and configurability by making it easy to tweak the timings in the code. - Fix up some confused references to 50 MHz in 66 MHz properties. --- .../devicetree/bindings/ata/faraday,ftide010.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/faraday,ftide010.txt -- 2.9.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt b/Documentation/devicetree/bindings/ata/faraday,ftide010.txt new file mode 100644 index 000000000000..a0c64a29104d --- /dev/null +++ b/Documentation/devicetree/bindings/ata/faraday,ftide010.txt @@ -0,0 +1,38 @@ +* Faraday Technology FTIDE010 PATA controller + +This controller is the first Faraday IDE interface block, used in the +StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini +platform. The controller can do PIO modes 0 through 4, Multi-word DMA +(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6. + +On the Gemini platform, this PATA block is accompanied by a PATA to +SATA bridge in order to support SATA. This is why a phandle to that +controller is compulsory on that platform. + +The timing properties are unique per-SoC, not per-board. + +Required properties: +- compatible: should be one of + "cortina,gemini-pata", "faraday,ftide010" + "faraday,ftide010" +- interrupts: interrupt for the block +- reg: registers and size for the block + +Optional properties: +- clocks: a SoC clock running the peripheral. +- clock-names: should be set to "PCLK" for the peripheral clock. + +Required properties for "cortina,gemini-pata" compatible: +- sata: a phande to the Gemini PATA to SATA bridge, see + cortina,gemini-sata-bridge.txt for details. + +Example: + +ata@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x100>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; +}; From patchwork Sun Jun 4 08:50:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 101351 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp447798qgd; Sun, 4 Jun 2017 01:50:31 -0700 (PDT) X-Received: by 10.98.205.65 with SMTP id o62mr14728508pfg.105.1496566231419; Sun, 04 Jun 2017 01:50:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496566231; cv=none; d=google.com; s=arc-20160816; b=NMBAN9vwT2Q5amvaq8nfkXG20Wd/9wYy4dvyJnoFyUmbVqU+ZwVTv1ABYax2jrlPLK NtyU+QuLA7IcEssdyZErjWnFvW4KZPufuz9uslWhRwuH/zQzorePL/IqbDmiweG1IfeQ nrv1pv+p6xulNVGkwO+dLUIcvsK5pvCFQefWT8yXTTKchQFYyUMAkwv8x21j2Sqq3DcJ 43YcIgWpE0nfxDjNUf8rv7qh974l7xW2DjrI3GcDD+P+2p16XiQzeg0vSfXj6YLisCgh fpYg9qa2uHledpDSVzQC01mNa8Io1fX/S3MaWRR3aHlxJg+uYD2rf2Orpu7NM689TdXs g2ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=66D/d8rokEyTmRx2eBJgfTd0QMsFU8tVxMjrrpRVDYE=; b=IwzT3cbvieoQTbvrf3rq6soIWJuTMudc/lQEmD9/2/hufImI53ViCjgmK1UqlXZaw3 aojxO4BgPLvwJP8p7dUiYe1f3vKq473Eb2MTvMkF0RUhitXss87EgD+H+Dtglcy5qx3s 2ZdyUjvYsgjap4BA408bzoDGOvcD0Fjn9SlMQHvZJ9bl/dCwLV2N+C1fkUIc2kJOAny0 D1ZtrKQk3SmsfbQgkVUW8P5PlHrTg1NRnSnkVY0wuU9VfCMxq3xKy0+/r6GTQ0DSuyCa q8MPu0eCzLjNFTbOghSeF8kLJu9giLqwdKlPGE5BRtK9qUBznOvAgMIdry6p+S+VAhwk c/1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.121.4]) by smtp.gmail.com with ESMTPSA id a88sm1440462ljb.54.2017.06.04.01.50.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 04 Jun 2017 01:50:25 -0700 (PDT) From: Linus Walleij To: Tejun Heo , Bartlomiej Zolnierkiewicz , linux-ide@vger.kernel.org Cc: Janos Laube , Paulius Zaleckas , linux-arm-kernel@lists.infradead.org, Hans Ulli Kroll , Florian Fainelli , Linus Walleij , devicetree@vger.kernel.org, John Feng-Hsin Chiang , Greentime Hu Subject: [PATCH 2/4 v4] ata: Add DT bindings for the Gemini SATA bridge Date: Sun, 4 Jun 2017 10:50:07 +0200 Message-Id: <20170604085009.11902-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170604085009.11902-1-linus.walleij@linaro.org> References: <20170604085009.11902-1-linus.walleij@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Cortina Systems Gemini PATA to SATA bridge. Cc: devicetree@vger.kernel.org Cc: John Feng-Hsin Chiang Cc: Greentime Hu Acked-by: Hans Ulli Kroll Acked-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - No changes, just resending to keep the patch set together. ChangeLog v2->v3: - No changes, just resending to keep the patch set together. ChangeLog v1->v2: - Fix ata0 misspelled as ata1 in one place. --- .../bindings/ata/cortina,gemini-sata-bridge.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt -- 2.9.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt b/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt new file mode 100644 index 000000000000..1c3d3cc70051 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt @@ -0,0 +1,55 @@ +* Cortina Systems Gemini SATA Bridge + +The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that +takes two Faraday Technology FTIDE010 PATA controllers and bridges +them in different configurations to two SATA ports. + +Required properties: +- compatible: should be + "cortina,gemini-sata-bridge" +- reg: registers and size for the block +- resets: phandles to the reset lines for both SATA bridges +- reset-names: must be "sata0", "sata1" +- clocks: phandles to the compulsory peripheral clocks +- clock-names: must be "SATA0_PCLK", "SATA1_PCLK" +- syscon: a phandle to the global Gemini system controller +- cortina,gemini-ata-muxmode: tell the desired multiplexing mode for + the ATA controller and SATA bridges. Values 0..3: + Mode 0: ata0 master <-> sata0 + ata1 master <-> sata1 + ata0 slave interface brought out on IDE pads + Mode 1: ata0 master <-> sata0 + ata1 master <-> sata1 + ata1 slave interface brought out on IDE pads + Mode 2: ata1 master <-> sata1 + ata1 slave <-> sata0 + ata0 master and slave interfaces brought out + on IDE pads + Mode 3: ata0 master <-> sata0 + ata0 slave <-> sata1 + ata1 master and slave interfaces brought out + on IDE pads + +Optional boolean properties: +- cortina,gemini-enable-ide-pins: enables the PATA to IDE connection. + The muxmode setting decides whether ATA0 or ATA1 is brought out, + and whether master, slave or both interfaces get brought out. +- cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge + inside the Gemnini SoC. The Muxmode decides what PATA blocks will + be muxed out and how. + +Example: + +sata: sata@46000000 { + compatible = "cortina,gemini-sata-bridge"; + reg = <0x46000000 0x100>; + resets = <&rcon 26>, <&rcon 27>; + reset-names = "sata0", "sata1"; + clocks = <&gcc GEMINI_CLK_GATE_SATA0>, + <&gcc GEMINI_CLK_GATE_SATA1>; + clock-names = "SATA0_PCLK", "SATA1_PCLK"; + syscon = <&syscon>; + cortina,gemini-ata-muxmode = <3>; + cortina,gemini-enable-ide-pins; + cortina,gemini-enable-sata-bridge; +};