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[92.154.90.120]) by smtp.gmail.com with ESMTPSA id z17sm22268820wrv.2.2018.12.26.05.25.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Dec 2018 05:25:37 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 26 Dec 2018 14:25:28 +0100 Message-Id: <20181226132530.8445-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181226132530.8445-1-ard.biesheuvel@linaro.org> References: <20181226132530.8445-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 1/3] Silicon/SynQuacer/AcpiTables: don't use PCD for PL011 base X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of using the generic PcdSerialRegisterBase PCD for generating the DSDT object for the PL011 UART, add PL011 base and size #defines to the memory map header file, and use those instead. This will allow us to switch to a different UART for DEBUG and/or serial console output in a future patch. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 1 - Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 2 +- Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 3 ++- 4 files changed, 7 insertions(+), 3 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf index afee50df5c63..6fbdf4d67a88 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf @@ -59,7 +59,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index fff760477488..28d4afabd2c8 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -72,4 +72,8 @@ #define SYNQUACER_MMIO_TIMER_CTL_BASE 0x2A810000 #define SYNQUACER_MMIO_TIMER_CNT_BASE0 0x2A830000 +// PL011 UART +#define SYNQUACER_UART0_BASE 0x2A400000 +#define SYNQUACER_UART0_SIZE SIZE_4KB + #endif diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index 7c7677f1fea0..ddb456d1dc70 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -137,7 +137,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", Name (_HID, "ARMH0011") Name (_UID, Zero) Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), 0x1000) + Memory32Fixed (ReadWrite, SYNQUACER_UART0_BASE, SYNQUACER_UART0_SIZE) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 } }) } diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc index 699e79e1bf59..c549a9781c8c 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc @@ -19,6 +19,7 @@ #include #include +#include #include "AcpiTables.h" @@ -47,7 +48,7 @@ STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { 32, 0, EFI_ACPI_5_1_DWORD, - FixedPcdGet32 (PcdSerialRegisterBase) + SYNQUACER_UART0_BASE }, // // InterruptType From patchwork Wed Dec 26 13:25:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 154524 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5835545ljp; Wed, 26 Dec 2018 05:25:46 -0800 (PST) X-Google-Smtp-Source: ALg8bN6UKwg/hO2xNAzQsxEqBV0yEzoga0fZekfPFlkNmEdnJGarARCHB4eS8JkxlRKxv1zj7uxK X-Received: by 2002:a63:9402:: with SMTP id m2mr18223577pge.93.1545830746801; Wed, 26 Dec 2018 05:25:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545830746; cv=none; d=google.com; s=arc-20160816; b=zQPNtVLNQyzl3529qd4voIbeGsUhFQtROt7FvYQ9FKLsTagmBjiRm7JT7bArm1RB9d cZqXvToStyj9QFR27AjYgOtvvPAd0VOMburBUn9m21EvI5gXJAD/hhuXiGkoFKZW2ULV +rfoEBPVcG/Z8NP3PUsXKQ+jpHfpmi/UN0XqXKAPeB4Hl57t1a1CsP4igXfVZrrtcXgH C3ERMPZZthBm5VIoWACqDoMCD3IjvDtJKtj/STdMjUK4WRNhBOr+o1gba1s32OCTIQBK LUPoJ29rfxWSR1JmG1rlmL8I+Mf1Z4bAUJ8rHZcotBaAsGNRg0OZJGKcwDNQDF89Ck0D tGIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:delivered-to; bh=v1O2UweG+c47U+V+zkddwI3HMO04Z0W/qWOO3mYc7UU=; b=oSTs1LR0CQWfu80bLdOH+8G65gD410pk3AzjTOgeoKi7ILEls1KekcJaca+c6m/SYr Vty2SjqclzxQ+F6IxnuvLOBQzsREdq76P8BeRMQEHq0bbV0c1DsQRXZoSMQXXz03qCLp uRShE543VwxdvI+LTp5kh0YYPImmuvoM55Z7OMyNMc/X/5m5vYMg/QA9KWjQamEvFATd jfqleuOi7E0+TiAgEwZdUTJrjeLlQtZwbsFxV4GSsquIMa1AneftEad69st6mNTBrxim BoiVOb2YmbHH2WQhO8YZzzRPGJtpNwULd7rw+ozVX0RBJRvBxwRitaPkVDoyi1W6f8Zn JpbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IuMWjLvg; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[92.154.90.120]) by smtp.gmail.com with ESMTPSA id z17sm22268820wrv.2.2018.12.26.05.25.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Dec 2018 05:25:38 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 26 Dec 2018 14:25:29 +0100 Message-Id: <20181226132530.8445-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181226132530.8445-1-ard.biesheuvel@linaro.org> References: <20181226132530.8445-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 2/3] Silicon/SynQuacer/AcpiTables: expose second UART to the OS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Align the DSDT with the device tree, which already exposes the second UART to the OS. Since existing OSes will not support the SCX0006 HID (which has only been allocated very recently), expose the DesignWare FUART with a compatible ID (CID) of 'HISI0031', which is associated with the same driver in Linux since at least release v4.9. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index 28d4afabd2c8..b0fcc306c1ae 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -76,4 +76,8 @@ #define SYNQUACER_UART0_BASE 0x2A400000 #define SYNQUACER_UART0_SIZE SIZE_4KB +// DesignWare FUART +#define SYNQUACER_UART1_BASE 0x51040000 +#define SYNQUACER_UART1_SIZE SIZE_4KB + #endif diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index ddb456d1dc70..aab4fbf0e6b4 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -142,6 +142,25 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", }) } + // DesignWare FUART + Device (COM1) { + Name (_HID, "SCX0006") + Name (_CID, "HISI0031") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_UART1_BASE, SYNQUACER_UART1_SIZE) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 200 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 62500000 }, + Package () { "reg-io-width", 4 }, + Package () { "reg-shift", 2 }, + } + }) + } + Device (NET0) { Name (_HID, "SCX0001") Name (_UID, Zero) From patchwork Wed Dec 26 13:25:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 154525 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5835589ljp; Wed, 26 Dec 2018 05:25:50 -0800 (PST) X-Google-Smtp-Source: AFSGD/XjnZIkkc0MnqLBsI81AUcFHwfseQcxSDm1agd6PcMSjqVbxMw0qyr0DP1fOSkUYnMAdAQ6 X-Received: by 2002:a62:2f06:: with SMTP id v6mr20459455pfv.216.1545830750022; Wed, 26 Dec 2018 05:25:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545830750; cv=none; d=google.com; s=arc-20160816; b=ocSdd2NdCQkEMTw84pM3vZXokmhoduYXWg7mvNIMSMv6Zp7GQ9JzN56dL3uTtPGOZj 6XjmUKO3MxDEBvpqGPD68nww2Bz6g2WxgHkpPvxd6BnU2vJe32A3WzDNBVu5Nm1xJbSt xIFS0MJ/ayhA60Yo+xf6bg7+4jKsWmQLbvIbPyD0TV2n9R8ohBQH/uhZoFKxp8AX8DTU /g24Vk3gGaTwF/2A/+uwzmVzA3z9PUccoxhY/Yq1JLOFeG8WYVfb8vj366+WC3PTR1AU ZUfR70MMYQ83C1d8rb7ncotPKaLUUJOKZ0yNh11MVqUNky15SSZCUBq0XCSzDMaonFZQ X/6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:delivered-to; bh=mHqNFtitYTv3w0U/miJqVCXzGPyt0oQnWaqqz8uOFVM=; b=dQZjy0K3vVnfWOaIjg/lHOqcT88KBHMPKSKghNXLyEPtfsJMFW6HcGh2yILC0Prasn UDQm562FQ1TfIItdckME2lk6A9MZUv1RbmDryFeQze8uvB9EDq2O/TRos/Ka3vGBvECc bB7Y8izJzN+ECT1Gs69byC9QwUGzIH59oG2xqPnCi9JrnC/qu4UMmvliWrx64ghmHvjl IEJWbePAxiPgFcdXkMWW1JtVCUC6rJOhz3uhqjVFQUzpIQNXY48Hr4NVbR/JKTFyxwCr WI/xCvMRB/PCQ2U0wEN0dA1Jvz9sPYBwHA2kbrFEqSVg8IRGjzy3JDgJjCod9mxwK4aB NLuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="MNvfQZ/f"; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[92.154.90.120]) by smtp.gmail.com with ESMTPSA id z17sm22268820wrv.2.2018.12.26.05.25.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Dec 2018 05:25:39 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 26 Dec 2018 14:25:30 +0100 Message-Id: <20181226132530.8445-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181226132530.8445-1-ard.biesheuvel@linaro.org> References: <20181226132530.8445-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 3/3] Silicon/SynQuacer: add support for DEBUG output on second UART X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" On headless server systems where the PL011 serial port is the primary console, having DEBUG output on the same port can be annoying, since DEBUG output gets lost when the console driver clears the screen or positions the cursor using control characters. So add the ability to emit the DEBUG output on the DesignWare FUART (which is exposed via the LS connector on DeveloperBox) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 42 +++++++++++++++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 ++ 2 files changed, 40 insertions(+), 5 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index ed11aed798b7..da450a132798 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -28,6 +28,8 @@ FLASH_DEFINITION = Platform/Socionext/DeveloperBox/DeveloperBox.fdf BUILD_NUMBER = 1 + DEFINE DEBUG_ON_UART1 = FALSE + [BuildOptions] RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0 @@ -120,9 +122,17 @@ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf - SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf +!if $(DEBUG_ON_UART1) == FALSE + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf +!else + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf +!endif + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf @@ -253,13 +263,26 @@ !endif ## PL011 - Serial Terminal - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2a400000 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 gArmPlatformTokenSpaceGuid.PL011UartInteger|0 gArmPlatformTokenSpaceGuid.PL011UartFractional|0 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|62500000 + ## DesignWare FUART + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|62500000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + + ## Shared UART settings + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + +!if $(DEBUG_ON_UART1) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2a400000 +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x51040000 +!endif + # # ARM Generic Interrupt Controller # @@ -505,7 +528,16 @@ } MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf { +!if $(DEBUG_ON_UART1) == TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2a400000 + + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + # suppress debug output from SerialDxe itself which would go to the PL011 + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + } MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index 1402ecafce4a..e68997e05573 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -118,6 +118,9 @@ STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { // NETSEC/eMMC SMMU ARM_DEVICE_REGION (SYNQUACER_SCB_SMMU_BASE, SYNQUACER_SCB_SMMU_SIZE), + + // DesignWare FUART + ARM_DEVICE_REGION (SYNQUACER_UART1_BASE, SYNQUACER_UART1_SIZE), }; STATIC