From patchwork Fri May 6 15:41:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matthew.gerlach@linux.intel.com X-Patchwork-Id: 570572 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AF37C4332F for ; Fri, 6 May 2022 15:41:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1443040AbiEFPpE (ORCPT ); Fri, 6 May 2022 11:45:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1443015AbiEFPpD (ORCPT ); Fri, 6 May 2022 11:45:03 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15EC35A5AF; Fri, 6 May 2022 08:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651851680; x=1683387680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FWT6jw3GZouNsnsxe8PgLhXGFpHvTWFkYY8DekcvT40=; b=Ewc2a2PeMfWrcFFw5rui6jTZB73Os1kvenn48cDlYzIC5hhNHnFDRCSt dvxaHTqcc391ipWJByWrXeuRPJ0bw+KqSwoK/5FMMkGiaz434sfSvUAhE 1WB15QBZ7YTtMyRr9m/rno2dyIXo5Rkh1VmbPe2+7BJfCgn52Q2y7MVU7 dlGc/Db/u9lHt7vN/g6Cxxs4aPHJnH9tkfgx0hgDAI1AreH67hQkM5j95 OxDQZ7s3azGtP7YR62FsRObMgwLWhgXt7jxpfOscCaCRwX8v104uHK4L0 y7IDmKwc0qlMIOV/gR80xETWdqEgvJzcTGbBedi33snj3mH5C1YSb6Xh/ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10339"; a="354932054" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="354932054" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2022 08:41:18 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="632980315" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2022 08:41:18 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach Subject: [PATCH v3 1/3] dt-bindings: soc: add bindings for Intel HPS Copy Engine Date: Fri, 6 May 2022 08:41:14 -0700 Message-Id: <20220506154116.365235-2-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506154116.365235-1-matthew.gerlach@linux.intel.com> References: <20220506154116.365235-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Matthew Gerlach Add device tree bindings documentation for the Intel Hard Processor System (HPS) Copy Engine. Signed-off-by: Matthew Gerlach --- v3: - remove unused label - move from misc to soc - remove 0x from #address-cells/#size-cells values - change hps_cp_eng@0 to dma-controller@0 - remote inaccurate 'items:' tag --- .../bindings/soc/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/intel,hps-copy-engine.yaml diff --git a/Documentation/devicetree/bindings/soc/intel,hps-copy-engine.yaml b/Documentation/devicetree/bindings/soc/intel,hps-copy-engine.yaml new file mode 100644 index 000000000000..606208233b67 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel,hps-copy-engine.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022, Intel Corporation +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/intel,hps-copy-engine.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel HPS Copy Engine + +maintainers: + - Matthew Gerlach + +description: | + The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy + a bootable image from host memory to HPS DDR. Additionally, there is a + register the HPS can use to indicate the state of booting the copied image as + well as a keep-a-live indication to the host. + +properties: + compatible: + const: intel,hps-copy-engine + + '#dma-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus@80000000 { + compatible = "simple-bus"; + reg = <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names = "axi_h2f", "axi_h2f_lw"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>; + + dma-controller@0 { + compatible = "intel,hps-copy-engine"; + reg = <0x00000000 0x00000000 0x00001000>; + #dma-cells = <1>; + }; + }; From patchwork Fri May 6 15:41:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matthew.gerlach@linux.intel.com X-Patchwork-Id: 570283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE4BBC433EF for ; Fri, 6 May 2022 15:41:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1443023AbiEFPpE (ORCPT ); Fri, 6 May 2022 11:45:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345596AbiEFPpD (ORCPT ); Fri, 6 May 2022 11:45:03 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B50E5BE41; Fri, 6 May 2022 08:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651851680; x=1683387680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7k1HLML8EiHrtt/rP2Re4XQ7J53RxaR/YSDTSazTTZk=; b=cT5rQ7rhBdiTj+uZcauWiduf4hEepq7/wAQeu6CS8i8bxCB7s6z9aah5 KkhwaOrJGosaN5FzawkLlaxxajxZCMwk2+/Ruhekd/kxKItsB5dneWsml 5OC9n5ELG0llwAI76IF159hV7lr/EorPrm9z+vL4G74XHrseSar34zpCl TJ+gYZuKALnQRT99RDC/nX7lO5e70VgLa0g0Uwlyj29vFvEi3NkE6Uqkd xX8qGvp0kCnf5K900+2Jf33tyYMCMKXm1MsA6pVvewvYMoRkzOyGN17Hr oJHsuVoSB3cbaYbNoHePHfpoeoDncCeVQtoBT4RDxmxEQGjMUia0FUsc2 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10339"; a="354932056" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="354932056" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2022 08:41:19 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="632980316" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2022 08:41:18 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach , Krzysztof Kozlowski Subject: [PATCH v3 2/3] dt-bindings: intel: add binding for Intel n6000 Date: Fri, 6 May 2022 08:41:15 -0700 Message-Id: <20220506154116.365235-3-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506154116.365235-1-matthew.gerlach@linux.intel.com> References: <20220506154116.365235-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Matthew Gerlach Add the binding string for the Agilex based Intel n6000 board. Signed-off-by: Matthew Gerlach Acked-by: Krzysztof Kozlowski --- v3: - added Acked-by --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index 6e043459fcd5..61a454a40e87 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - intel,n5x-socdk + - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex From patchwork Fri May 6 15:41:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matthew.gerlach@linux.intel.com X-Patchwork-Id: 570282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C58C43217 for ; Fri, 6 May 2022 15:41:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1443054AbiEFPpF (ORCPT ); Fri, 6 May 2022 11:45:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1443024AbiEFPpE (ORCPT ); Fri, 6 May 2022 11:45:04 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0D3D5A5A9; Fri, 6 May 2022 08:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651851680; x=1683387680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=owflUxJwye43Jslm11MI/MaUZtH0owF4PzzUJNNfyZ0=; b=BTcyieE8Rf/sBywGgMrqX0CIPd1nNxbmT1vdU+gXpPZgMnwJb1q/Wv3s 5/pbCb4OZfrcAtgdLgC6pTG+LkdWgzlT7+ZBPeIDaZS3pfgwL7gFE2vg4 aD3AqzpSpNE9BfJE4REL4sVc7W1i/IzpcH41MqJudY7C3bZot4h3F0lb1 QMTLrhY6luAWwCjyFVSaFMJDIeyNz4kd6Wt84MXKD9RoXBWhDKdtczUcO JR24RTTUeMF41Cj/bl0UFW2Z5uy+pLo0wCJTiuYUmaLH6aWzbfR0cOyWw 6sovgM+3nc46IIyyNs/SQK4sEDWqH8dLp/bL1KDpGTno3TWafVRgtZOWT g==; X-IronPort-AV: E=McAfee;i="6400,9594,10339"; a="354932058" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="354932058" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2022 08:41:19 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="632980317" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2022 08:41:19 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach Subject: [PATCH v3 3/3] arm64: dts: intel: add device tree for n6000 Date: Fri, 6 May 2022 08:41:16 -0700 Message-Id: <20220506154116.365235-4-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506154116.365235-1-matthew.gerlach@linux.intel.com> References: <20220506154116.365235-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Matthew Gerlach Add a device tree for the n6000 instantiation of Agilex Hard Processor System (HPS). Signed-off-by: Matthew Gerlach --- v3: - add unit number to memory node - remove unused label - remove 0x from #address-cells/#size-cells values - change hps_cp_eng@0 to dma-controller@0 - remove spi node with unaccepted compatible value v2: - fix copy engine node name - fix compatible field for copy engine - remove redundant status field - add compatibility field for the board - fix SPDX - fix how osc1 clock frequency is set --- arch/arm64/boot/dts/intel/Makefile | 3 +- .../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 0b5477442263..c2a723838344 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \ +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ + socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts new file mode 100644 index 000000000000..6231a69204b1 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2022, Intel Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model = "SoCFPGA Agilex n6000"; + compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex"; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + bus@80000000 { + compatible = "simple-bus"; + reg = <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names = "axi_h2f", "axi_h2f_lw"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>; + + dma-controller@0 { + compatible = "intel,hps-copy-engine"; + reg = <0x00000000 0x00000000 0x00001000>; + #dma-cells = <1>; + }; + }; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&fpga_mgr { + status = "disabled"; +};