From patchwork Wed May 11 22:06:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 571863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58D2AC41535 for ; Wed, 11 May 2022 22:06:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348578AbiEKWGZ (ORCPT ); Wed, 11 May 2022 18:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348542AbiEKWGU (ORCPT ); Wed, 11 May 2022 18:06:20 -0400 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [IPv6:2001:4b7a:2000:18::162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B2BF220F0; Wed, 11 May 2022 15:06:17 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 42BD920862; Thu, 12 May 2022 00:06:15 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org, Bjorn Andersson Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] arm64: dts: qcom: pm660: Use unique ADC5_VCOIN address in node name Date: Thu, 12 May 2022 00:06:07 +0200 Message-Id: <20220511220613.1015472-2-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511220613.1015472-1-marijn.suijten@somainline.org> References: <20220511220613.1015472-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The register address in the node name is shadowing vph_pwr@83, whereas the ADC5_VCOIN register resolves to 0x85. Fix this copy-paste discrepancy. Fixes: 4bf097540506 ("arm64: dts: qcom: pm660: Add VADC and temp alarm nodes") Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.36.1 diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index c482663aad56..42f9c51b9c1e 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -163,7 +163,7 @@ vadc_vph_pwr: vph_pwr@83 { qcom,pre-scaling = <1 3>; }; - vcoin: vcoin@83 { + vcoin: vcoin@85 { reg = ; qcom,decimation = <1024>; qcom,pre-scaling = <1 3>; From patchwork Wed May 11 22:06:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 571550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBEF0C433EF for ; Wed, 11 May 2022 22:06:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348555AbiEKWGY (ORCPT ); Wed, 11 May 2022 18:06:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347467AbiEKWGU (ORCPT ); Wed, 11 May 2022 18:06:20 -0400 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [5.144.164.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18C391E3CE for ; Wed, 11 May 2022 15:06:18 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 0716220865; Thu, 12 May 2022 00:06:15 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org, Bjorn Andersson Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] dt-bindings: pinctrl: qcom-pmic-gpio: Add pm6125 compatible Date: Thu, 12 May 2022 00:06:08 +0200 Message-Id: <20220511220613.1015472-3-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511220613.1015472-1-marijn.suijten@somainline.org> References: <20220511220613.1015472-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The pm6125 comes with 9 GPIOs, without holes. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 22dbcba752d0..ef7a4a9450a4 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -20,6 +20,7 @@ properties: - qcom,pm2250-gpio - qcom,pm660-gpio - qcom,pm660l-gpio + - qcom,pm6125-gpio - qcom,pm6150-gpio - qcom,pm6150l-gpio - qcom,pm6350-gpio @@ -107,6 +108,7 @@ $defs: description: List of gpio pins affected by the properties specified in this subnode. Valid pins are + - gpio1-gpio9 for pm6125 - gpio1-gpio10 for pm6150 - gpio1-gpio12 for pm6150l - gpio1-gpio9 for pm6350 From patchwork Wed May 11 22:06:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 571549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 499E9C4167D for ; Wed, 11 May 2022 22:06:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348549AbiEKWG1 (ORCPT ); Wed, 11 May 2022 18:06:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348547AbiEKWGV (ORCPT ); Wed, 11 May 2022 18:06:21 -0400 Received: from relay04.th.seeweb.it (relay04.th.seeweb.it [5.144.164.165]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19A9422BD0 for ; Wed, 11 May 2022 15:06:18 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id BB17120864; Thu, 12 May 2022 00:06:16 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org, Bjorn Andersson Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] pinctrl: qcom: spmi-gpio: Add pm6125 compatible Date: Thu, 12 May 2022 00:06:09 +0200 Message-Id: <20220511220613.1015472-4-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511220613.1015472-1-marijn.suijten@somainline.org> References: <20220511220613.1015472-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The pm6125 has 9 GPIOs with no holes inbetween. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index a0c45b305981..fd5fff9adff0 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1146,6 +1146,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm6125-gpio", .data = (void *) 9 }, { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 }, From patchwork Wed May 11 22:06:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 571864 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A15D6C43217 for ; Wed, 11 May 2022 22:06:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348566AbiEKWG0 (ORCPT ); Wed, 11 May 2022 18:06:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348549AbiEKWGY (ORCPT ); Wed, 11 May 2022 18:06:24 -0400 Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [5.144.164.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5B7D22B07 for ; Wed, 11 May 2022 15:06:19 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 621FF2085B; Thu, 12 May 2022 00:06:17 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org, Bjorn Andersson Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Jonathan Cameron , Lars-Peter Clausen , linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] iio: adc: qcom-spmi-adc5: Add missing VCOIN/AMUX_THM3/GPIO# channels Date: Thu, 12 May 2022 00:06:10 +0200 Message-Id: <20220511220613.1015472-5-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511220613.1015472-1-marijn.suijten@somainline.org> References: <20220511220613.1015472-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org These channels are specified in downstream kernels [1] and actively used by ie. the Sony Seine platform on the SM6125 SoC. [1]: https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/drivers/iio/adc/qcom-spmi-adc5.c?h=LA.UM.7.11.r1-05200-NICOBAR.0#n688 Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno --- drivers/iio/adc/qcom-spmi-adc5.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 87438d1e5c0b..69c7fd44d34c 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -526,6 +526,8 @@ static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = { SCALE_HW_CALIB_DEFAULT) [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1, SCALE_HW_CALIB_DEFAULT) + [ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 1, + SCALE_HW_CALIB_DEFAULT) [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0, SCALE_HW_CALIB_PMIC_THERM) [ADC5_USB_IN_I] = ADC5_CHAN_VOLT("usb_in_i_uv", 0, @@ -549,6 +551,16 @@ static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = { SCALE_HW_CALIB_THERM_100K_PULLUP) [ADC5_AMUX_THM2] = ADC5_CHAN_TEMP("amux_thm2", 0, SCALE_HW_CALIB_PM5_SMB_TEMP) + [ADC5_AMUX_THM3] = ADC5_CHAN_TEMP("amux_thm3", 0, + SCALE_HW_CALIB_PM5_SMB_TEMP) + [ADC5_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_100k_pu", 0, + SCALE_HW_CALIB_THERM_100K_PULLUP) + [ADC5_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_100k_pu", 0, + SCALE_HW_CALIB_THERM_100K_PULLUP) + [ADC5_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_100k_pu", 0, + SCALE_HW_CALIB_THERM_100K_PULLUP) + [ADC5_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_100k_pu", 0, + SCALE_HW_CALIB_THERM_100K_PULLUP) }; static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = { From patchwork Wed May 11 22:06:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 571547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2A9CC38A06 for ; Wed, 11 May 2022 22:06:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348562AbiEKWG2 (ORCPT ); Wed, 11 May 2022 18:06:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348579AbiEKWGZ (ORCPT ); Wed, 11 May 2022 18:06:25 -0400 Received: from relay03.th.seeweb.it (relay03.th.seeweb.it [IPv6:2001:4b7a:2000:18::164]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0827C286CA; Wed, 11 May 2022 15:06:21 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 7D22C20856; Thu, 12 May 2022 00:06:18 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org, Bjorn Andersson Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] arm64: dts: qcom: Add PM6125 PMIC Date: Thu, 12 May 2022 00:06:11 +0200 Message-Id: <20220511220613.1015472-6-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511220613.1015472-1-marijn.suijten@somainline.org> References: <20220511220613.1015472-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This PMIC is commonly used on boards with an SM6125 SoC and looks very similar in layout to the PM6150. Downstream declares more nodes to be available, but these have been omitted from this patch: the pwm/lpg block is unused on my reference device making it impossible to test/validate, and the spmi-clkdiv does not have a single device-tree binding using this driver yet, hence inclusion is better postponed until ie. audio which uses these clocks is brought up. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm6125.dtsi | 156 +++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm6125.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi new file mode 100644 index 000000000000..5028001f8213 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include +#include +#include + +/ { + thermal-zones { + pm6125-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm6125_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@0 { + compatible = "qcom,pm6125", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6125_pon: pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pon_pwrkey: pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + linux,code = ; + bias-pull-up; + status = "disabled"; + }; + + pon_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + pm6125_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm6125_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm6125_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vph-pwr@83 { + reg = ; + qcom,pre-scaling = <1 3>; + }; + + vcoin@85 { + reg = ; + qcom,pre-scaling = <1 3>; + }; + + xo-therm@4c { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + }; + + pm6125_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pm6125_rtc: rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + pm6125_gpio: gpios@c000 { + compatible = "qcom,pm6125-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm6125_gpio 0 0 9>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pm6125", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; From patchwork Wed May 11 22:06:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 571862 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F571C433FE for ; Wed, 11 May 2022 22:06:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348579AbiEKWGa (ORCPT ); Wed, 11 May 2022 18:06:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348563AbiEKWGY (ORCPT ); Wed, 11 May 2022 18:06:24 -0400 Received: from relay04.th.seeweb.it (relay04.th.seeweb.it [IPv6:2001:4b7a:2000:18::165]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCD042899C for ; Wed, 11 May 2022 15:06:21 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 2B9452086B; Thu, 12 May 2022 00:06:19 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org, Bjorn Andersson Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] arm64: dts: qcom: sm6125-seine: Include PM6125 and configure PON Date: Thu, 12 May 2022 00:06:12 +0200 Message-Id: <20220511220613.1015472-7-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511220613.1015472-1-marijn.suijten@somainline.org> References: <20220511220613.1015472-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Sony Xperia Seine board uses the PM6125; include it and configure the PON buttons that provide the power and volume-up key. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 038970c0b68e..c5967140d028 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -6,8 +6,8 @@ /dts-v1/; #include "sm6125.dtsi" +#include "pm6125.dtsi" #include -#include #include / { @@ -88,6 +88,15 @@ &hsusb_phy1 { status = "okay"; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + &sdc2_off_state { sd-cd { pins = "gpio98"; From patchwork Wed May 11 22:06:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 571548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37F00C352A7 for ; Wed, 11 May 2022 22:06:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348587AbiEKWG1 (ORCPT ); Wed, 11 May 2022 18:06:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348581AbiEKWGZ (ORCPT ); Wed, 11 May 2022 18:06:25 -0400 Received: from relay04.th.seeweb.it (relay04.th.seeweb.it [5.144.164.165]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD058289B0; Wed, 11 May 2022 15:06:21 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id D463E207D3; Thu, 12 May 2022 00:06:19 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org, Bjorn Andersson Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: qcom: sm6125-seine: Configure additional trinket thermistors Date: Thu, 12 May 2022 00:06:13 +0200 Message-Id: <20220511220613.1015472-8-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511220613.1015472-1-marijn.suijten@somainline.org> References: <20220511220613.1015472-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In addition to PMIC-specific (pm6125) thermistors downstream extends this set with the rf-pa0/rf-pa1, quiet, camera-flash and UFS/eMMC thermistors in sm6125 (trinket) board and seine-specific DT files. All thermistors report sensible temperature readings in userspace. The sensors are also added to their respective Thermal Monitor node, with thermal zones to match where applicable: emmc-ufs and camera-flash are not available on the TM5 block, hence cannot be configured with a tripping point and will not have a thermal zone. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno --- .../qcom/sm6125-sony-xperia-seine-pdx201.dts | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index c5967140d028..ca7f074a62a9 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -82,12 +82,162 @@ cmdline_mem: memory@ffd00000 { no-map; }; }; + + thermal-zones { + rf-pa0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6125_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + quiet-thermal { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-sensors = <&pm6125_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6125_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + rf-pa1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6125_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; }; &hsusb_phy1 { status = "okay"; }; +&pm6125_adc { + pinctrl-names = "default"; + pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>; + + rf-pa0-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera-flash-therm@52 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + emmc-ufs-therm@54 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + rf-pa1-therm@55 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_adc_tm { + status = "okay"; + + rf-pa0-therm@0 { + reg = <0>; + io-channels = <&pm6125_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pm6125_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo-therm@2 { + reg = <2>; + io-channels = <&pm6125_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + rf-pa1-therm@3 { + reg = <3>; + io-channels = <&pm6125_adc ADC5_GPIO4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6125_gpio { + camera_flash_therm: camera-flash-therm { + pins = "gpio3"; + function = "normal"; + bias-high-impedance; + }; + + emmc_ufs_therm: emmc-ufs-therm { + pins = "gpio6"; + function = "normal"; + bias-high-impedance; + }; + + rf_pa1_therm: rf-pa1-therm { + pins = "gpio7"; + function = "normal"; + bias-high-impedance; + }; +}; + &pon_pwrkey { status = "okay"; };