From patchwork Wed May 11 13:18:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 571880 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A627C433F5 for ; Wed, 11 May 2022 13:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232115AbiEKNTN (ORCPT ); Wed, 11 May 2022 09:19:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243364AbiEKNTA (ORCPT ); Wed, 11 May 2022 09:19:00 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B02E9D041; Wed, 11 May 2022 06:18:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652275135; x=1683811135; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=90D8lqmzfGf0V/YMvKVQhQzEgHgPEPwsMRPeHW4f4zc=; b=H0Y2KLy2pDGCgyr0nZqAUPyN4JZX9hykE9lIG+BLfzJbwG71ezF3C8w+ OJ35afPSz5T+VhxBOGc2q1fqQgrHAmZoAWZmhiRky1IozAfnKsz2rU7KK UYjB4rWVvf/MNp6LoyXcTiRNdebFsRDjAJ+TptngTPOz3aP3oIYpmkp8E 8=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 11 May 2022 06:18:55 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 06:18:54 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:18:54 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:18:50 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 1/9] dt-bindings: mfd: pm8008: Add reset-gpios Date: Wed, 11 May 2022 18:48:25 +0530 Message-ID: <1652275113-10277-2-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add reset-gpios property for pm8008. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- Changes in V12: - None. Changes in V11: - Change the GPIO_ACTIVE_HIGH flag to GPIO_ACTIVE_LOW. Changes in V10: - None. Changes in V9: - Undo the changes from V8 and only add reset-gpios. Leave interrupts as required properties and do not change compatible. Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml index ec3138c..a89649c 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml @@ -44,6 +44,9 @@ properties: "#size-cells": const: 0 + reset-gpios: + maxItems: 1 + patternProperties: "^gpio@[0-9a-f]+$": type: object @@ -92,6 +95,7 @@ required: - "#address-cells" - "#size-cells" - "#interrupt-cells" + - reset-gpios additionalProperties: false @@ -99,6 +103,7 @@ examples: - | #include #include + #include qupv3_se13_i2c { #address-cells = <1>; #size-cells = <0>; @@ -113,6 +118,8 @@ examples: interrupt-parent = <&tlmm>; interrupts = <32 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&pm8350c_gpios 4 GPIO_ACTIVE_LOW>; + pm8008_gpios: gpio@c000 { compatible = "qcom,pm8008-gpio", "qcom,spmi-gpio"; reg = <0xc000>; From patchwork Wed May 11 13:18:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 571569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CFA6C433FE for ; Wed, 11 May 2022 13:19:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243415AbiEKNTJ (ORCPT ); Wed, 11 May 2022 09:19:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243730AbiEKNTB (ORCPT ); Wed, 11 May 2022 09:19:01 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 615AEC5DB4; Wed, 11 May 2022 06:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652275140; x=1683811140; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=MLNi7pUoudqMH9W7heubpLK4kQeusR8F/h13s9TEF8k=; b=nl9TXeD+FCJZPVWCsBCXrHnbN1ecrxL4es//PUb2cfw2GedWIIfZKvYr n22CyR6wFX3OBRyyEcumKNzMOd4alT7tVKLs1zr1gYigTybIxzTswDHu9 ukvYHuUm5cP4Y0C5UKl/kpO9GKwGxiqTpxk7b3dY//ufIBEhja5jb6U/q w=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 11 May 2022 06:19:00 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 06:18:59 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:18:59 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:18:54 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 2/9] dt-bindings: mfd: pm8008: Change the address cells Date: Wed, 11 May 2022 18:48:26 +0530 Message-ID: <1652275113-10277-3-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the address cells as '2' so that the first cell describes the i2c address offset of the clients. This helps us to define the child nodes of all clients under the same parent mfd node, instead of adding separate mfd DT nodes. Change the gpios reg value accordingly. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- Changes in V12: - None. Changes in V11: - New patch added from V11. Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml index a89649c..a41618e 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml @@ -39,7 +39,7 @@ properties: interrupt-controller: true "#address-cells": - const: 1 + const: 2 "#size-cells": const: 0 @@ -48,7 +48,7 @@ properties: maxItems: 1 patternProperties: - "^gpio@[0-9a-f]+$": + "^gpio@[0],[0-9a-f]+$": type: object description: | @@ -61,7 +61,7 @@ patternProperties: - const: qcom,spmi-gpio reg: - description: Peripheral address of one of the two GPIO peripherals. + description: Peripheral offset and address of one of the two GPIO peripherals. maxItems: 1 gpio-controller: true @@ -110,7 +110,7 @@ examples: pm8008i@8 { compatible = "qcom,pm8008"; reg = <0x8>; - #address-cells = <1>; + #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -120,9 +120,9 @@ examples: reset-gpios = <&pm8350c_gpios 4 GPIO_ACTIVE_LOW>; - pm8008_gpios: gpio@c000 { + pm8008_gpios: gpio@0,c000 { compatible = "qcom,pm8008-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; + reg = <0x0 0xc000>; gpio-controller; gpio-ranges = <&pm8008_gpios 0 0 2>; #gpio-cells = <2>; From patchwork Wed May 11 13:18:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 571568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70724C433F5 for ; Wed, 11 May 2022 13:19:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243391AbiEKNT3 (ORCPT ); Wed, 11 May 2022 09:19:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243464AbiEKNTF (ORCPT ); Wed, 11 May 2022 09:19:05 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1C1723677A; Wed, 11 May 2022 06:19:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652275145; x=1683811145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=U2kacXGJOPEe5GjtzLxRzXO9xMIgNAgjBN70Rg8weF4=; b=qWkI0n1vYp4xKpmd2u6gcRR2ZvK/0k24Ll4Mom7YR36BrLs6PbK6S7U7 j+YBdgExFzOLbnGukij/LAswyFyRUFL0V54tyk9SIYaqA3wxyRwrjN3Ab XJ+neYSQScemGmqZZgm+z7ikCBkWcDoz8LyWfhvXvkHp4dvgWe/puALPg 4=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 11 May 2022 06:19:04 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 06:19:04 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:04 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:18:59 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 3/9] dt-bindings: mfd: pm8008: Add regulators for pm8008 Date: Wed, 11 May 2022 18:48:27 +0530 Message-ID: <1652275113-10277-4-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add regulators and their parent supplies along with example. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- Changes in V12: - None. Changes in V11: - Add ldos directly under pm8008@8 node, remove the intermediate "regulators" node. Changes in V10: - Regulators are added as a part of pm8008@8 device. Change bindings doc accordingly. Changes in V9: - Remove description for reg and drop unused phandle from example. Changes in V8: - This is split from pm8008.yaml binding. .../devicetree/bindings/mfd/qcom,pm8008.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml index a41618e..231aaf0 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml @@ -47,6 +47,21 @@ properties: reset-gpios: maxItems: 1 + vdd_l1_l2-supply: + description: Input supply phandle of ldo1 and ldo2 regulators. + + vdd_l3_l4-supply: + description: Input supply phandle of ldo3 and ldo4 regulators. + + vdd_l5-supply: + description: Input supply phandle of ldo5 regulator. + + vdd_l6-supply: + description: Input supply phandle of ldo6 regulator. + + vdd_l7-supply: + description: Input supply phandle of ldo7 regulator. + patternProperties: "^gpio@[0],[0-9a-f]+$": type: object @@ -88,6 +103,27 @@ patternProperties: additionalProperties: false + "^ldo[1-7]@[1],[0-9a-f]+$": + type: object + + $ref: "/schemas/regulator/regulator.yaml#" + + description: PM8008 regulator peripherals of PM8008 regulator device. + + properties: + compatible: + const: qcom,pm8008-regulator + + reg: + description: Peripheral offset and address of the ldo regulator. + maxItems: 1 + + required: + - compatible + - reg + + unevaluatedProperties: false + required: - compatible - reg @@ -120,6 +156,12 @@ examples: reset-gpios = <&pm8350c_gpios 4 GPIO_ACTIVE_LOW>; + vdd_l1_l2-supply = <&vreg_s8b_1p2>; + vdd_l3_l4-supply = <&vreg_s1b_1p8>; + vdd_l5-supply = <&vreg_bob>; + vdd_l6-supply = <&vreg_bob>; + vdd_l7-supply = <&vreg_bob>; + pm8008_gpios: gpio@0,c000 { compatible = "qcom,pm8008-gpio", "qcom,spmi-gpio"; reg = <0x0 0xc000>; @@ -129,6 +171,14 @@ examples: interrupt-controller; #interrupt-cells = <2>; }; + + ldo1@1,4000 { + compatible = "qcom,pm8008-regulator"; + reg = <0x1 0x4000>; + regulator-name = "pm8008_ldo1"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + }; }; }; From patchwork Wed May 11 13:18:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 571879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B04A5C433EF for ; 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Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 11 May 2022 06:19:08 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 06:19:08 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:08 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:04 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 4/9] mfd: pm8008: Add reset-gpios Date: Wed, 11 May 2022 18:48:28 +0530 Message-ID: <1652275113-10277-5-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the reset-gpio toggling in the pm8008_probe() to bring pm8008 chip out of reset instead of doing it in DT node using "output-high" property. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd --- Changes in V12: - Move reset_gpio acquiring above probe_irq_peripherals in pm8008_probe. Changes in V11: - Use local variable for reset_gpios as it is not used outside of probe. - Use GPIOD_OUT_LOW flag to initialize the gpio and remove below line as it is not required "gpiod_set_value(chip->reset_gpio, 1);". Changes in V10: - This has been split from [V9,3/6] as per comments here [1] [1] https://patchwork.kernel.org/project/linux-arm-msm/patch/1649166633-25872-4-git-send-email-quic_c_skakit@quicinc.com/#24803409 drivers/mfd/qcom-pm8008.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index c472d7f..5a670b0 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -221,6 +222,7 @@ static int pm8008_probe(struct i2c_client *client) { int rc; struct pm8008_data *chip; + struct gpio_desc *reset_gpio; chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); if (!chip) @@ -233,6 +235,10 @@ static int pm8008_probe(struct i2c_client *client) i2c_set_clientdata(client, chip); + reset_gpio = devm_gpiod_get(chip->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(reset_gpio)) + return PTR_ERR(reset_gpio); + if (of_property_read_bool(chip->dev->of_node, "interrupt-controller")) { rc = pm8008_probe_irq_peripherals(chip, client->irq); if (rc) From patchwork Wed May 11 13:18:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 571567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CE7DC433EF for ; Wed, 11 May 2022 13:19:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243615AbiEKNTf (ORCPT ); Wed, 11 May 2022 09:19:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243646AbiEKNTO (ORCPT ); Wed, 11 May 2022 09:19:14 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88DF9239796; Wed, 11 May 2022 06:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652275153; x=1683811153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Kf9i1b84UdMEp0GD80S9JuNplX2II5q6cyioxZsM/4s=; b=LAbr8X/c8hBQ1fuDGUrX930TLv3sScexKH7hFbiV6O47mw1X9dnJSt/T JRvm3W3WMUxCI4wsJMLwnABHmTiQk+MlNAfhXNDACC2Wd+rbJNVUy/3U8 QdbHQF5k3s/iJWtHo5VI+QE/z5X9iWNP3GxkFkQx5l1UOqIZ46va/xcwi M=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 11 May 2022 06:19:13 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 06:19:13 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:12 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:08 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 5/9] mfd: pm8008: Remove the regmap member from pm8008_data struct Date: Wed, 11 May 2022 18:48:29 +0530 Message-ID: <1652275113-10277-6-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the regmap member from pm8008_data struct as it is not used outside of probe. Add a local variable for regmap and pass it to the pm8008_probe_irq_peripherals() API in pm8008_probe. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd --- Changes in V12: - None. Changes in V11: - New patch added from V11. drivers/mfd/qcom-pm8008.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 5a670b0..569ffd50 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -57,7 +57,6 @@ enum { struct pm8008_data { struct device *dev; - struct regmap *regmap; int irq; struct regmap_irq_chip_data *irq_data; }; @@ -151,7 +150,7 @@ static struct regmap_config qcom_mfd_regmap_cfg = { .max_register = 0xFFFF, }; -static int pm8008_init(struct pm8008_data *chip) +static int pm8008_init(struct regmap *regmap) { int rc; @@ -161,32 +160,32 @@ static int pm8008_init(struct pm8008_data *chip) * This is required to enable the writing of TYPE registers in * regmap_irq_sync_unlock(). */ - rc = regmap_write(chip->regmap, + rc = regmap_write(regmap, (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); if (rc) return rc; /* Do the same for GPIO1 and GPIO2 peripherals */ - rc = regmap_write(chip->regmap, + rc = regmap_write(regmap, (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); if (rc) return rc; - rc = regmap_write(chip->regmap, + rc = regmap_write(regmap, (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); return rc; } static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, - int client_irq) + struct regmap *regmap, int client_irq) { int rc, i; struct regmap_irq_type *type; struct regmap_irq_chip_data *irq_data; - rc = pm8008_init(chip); + rc = pm8008_init(regmap); if (rc) { dev_err(chip->dev, "Init failed: %d\n", rc); return rc; @@ -208,7 +207,7 @@ static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW); } - rc = devm_regmap_add_irq_chip(chip->dev, chip->regmap, client_irq, + rc = devm_regmap_add_irq_chip(chip->dev, regmap, client_irq, IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data); if (rc) { dev_err(chip->dev, "Failed to add IRQ chip: %d\n", rc); @@ -223,14 +222,15 @@ static int pm8008_probe(struct i2c_client *client) int rc; struct pm8008_data *chip; struct gpio_desc *reset_gpio; + struct regmap *regmap; chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; chip->dev = &client->dev; - chip->regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg); - if (!chip->regmap) + regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg); + if (!regmap) return -ENODEV; i2c_set_clientdata(client, chip); @@ -240,7 +240,7 @@ static int pm8008_probe(struct i2c_client *client) return PTR_ERR(reset_gpio); if (of_property_read_bool(chip->dev->of_node, "interrupt-controller")) { - rc = pm8008_probe_irq_peripherals(chip, client->irq); + rc = pm8008_probe_irq_peripherals(chip, regmap, client->irq); if (rc) dev_err(chip->dev, "Failed to probe irq periphs: %d\n", rc); } From patchwork Wed May 11 13:18:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 571878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A43B8C433F5 for ; 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Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 11 May 2022 06:19:18 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 06:19:17 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:17 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:12 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 6/9] mfd: pm8008: Use i2c_new_dummy_device() API Date: Wed, 11 May 2022 18:48:30 +0530 Message-ID: <1652275113-10277-7-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use i2c_new_dummy_device() to register pm8008-regulator client present at a different address space, instead of defining a separate DT node. This avoids calling the probe twice for the same chip, once for each client pm8008-infra and pm8008-regulator. As a part of this define pm8008_regmap_init() to do regmap init for both the clients and define pm8008_get_regmap() to pass the regmap to the regulator driver. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd --- Changes in V12: - Make chip as const in pm8008_get_regmap() definition. - Use EXPORT_SYMBOL_GPL() for pm8008_get_regmap. - Add linux/mfd/qcom_pm8008.h to avoid error. Changes in V11: - Remove the for loop and register dummy directly as there are only 2 clients. - Define pm8008_regmap_init() API to do the redundant init part. Changes in V10: - Implement i2c_new_dummy_device to register extra clients. drivers/mfd/qcom-pm8008.c | 34 ++++++++++++++++++++++++++++++++-- include/linux/mfd/qcom_pm8008.h | 8 ++++++++ 2 files changed, 40 insertions(+), 2 deletions(-) create mode 100644 include/linux/mfd/qcom_pm8008.h diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 569ffd50..55e2a8e 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,7 @@ enum { struct pm8008_data { struct device *dev; + struct regmap *regulators_regmap; int irq; struct regmap_irq_chip_data *irq_data; }; @@ -150,6 +152,12 @@ static struct regmap_config qcom_mfd_regmap_cfg = { .max_register = 0xFFFF, }; +struct regmap *pm8008_get_regmap(const struct pm8008_data *chip) +{ + return chip->regulators_regmap; +} +EXPORT_SYMBOL_GPL(pm8008_get_regmap); + static int pm8008_init(struct regmap *regmap) { int rc; @@ -217,11 +225,25 @@ static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, return 0; } +static struct regmap *pm8008_regmap_init(struct i2c_client *client, + struct pm8008_data *chip) +{ + struct regmap *regmap; + + regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg); + if (!regmap) + return NULL; + + i2c_set_clientdata(client, chip); + return regmap; +} + static int pm8008_probe(struct i2c_client *client) { int rc; struct pm8008_data *chip; struct gpio_desc *reset_gpio; + struct i2c_client *regulators_client; struct regmap *regmap; chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); @@ -229,11 +251,19 @@ static int pm8008_probe(struct i2c_client *client) return -ENOMEM; chip->dev = &client->dev; - regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg); + regmap = pm8008_regmap_init(client, chip); if (!regmap) return -ENODEV; - i2c_set_clientdata(client, chip); + regulators_client = i2c_new_dummy_device(client->adapter, client->addr + 1); + if (IS_ERR(regulators_client)) { + dev_err(&client->dev, "can't attach client\n"); + return PTR_ERR(regulators_client); + } + + chip->regulators_regmap = pm8008_regmap_init(regulators_client, chip); + if (!chip->regulators_regmap) + return -ENODEV; reset_gpio = devm_gpiod_get(chip->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(reset_gpio)) diff --git a/include/linux/mfd/qcom_pm8008.h b/include/linux/mfd/qcom_pm8008.h new file mode 100644 index 0000000..d5db9a2 --- /dev/null +++ b/include/linux/mfd/qcom_pm8008.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __QCOM_PM8008_H__ +#define __QCOM_PM8008_H__ + +struct pm8008_data; +struct regmap *pm8008_get_regmap(const struct pm8008_data *chip); + +#endif From patchwork Wed May 11 13:18:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 571566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5968BC4332F for ; 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Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 11 May 2022 06:19:22 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 06:19:21 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:21 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:17 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 7/9] regulator: Add a regulator driver for the PM8008 PMIC Date: Wed, 11 May 2022 18:48:31 +0530 Message-ID: <1652275113-10277-8-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm Technologies, Inc. PM8008 is an I2C controlled PMIC containing 7 LDO regulators. Add a PM8008 regulator driver to support PMIC regulator management via the regulator framework. Signed-off-by: Satya Priya Reported-by: kernel test robot Reported-by: Dan Carpenter --- Changes in V12: - Get base from reg property in DT node. Changes in V11: - Added of_device_id table and compatible to register the ldos. Changes in V10: - Changed the driver name. - Removed unused header. - Use get_voltage_sel. Changes in V9: - Nothing has changed. Changes in V8: - Changed the regulators_data struct name to pm8008_regulator_data drivers/regulator/Kconfig | 9 ++ drivers/regulator/Makefile | 1 + drivers/regulator/qcom-pm8008-regulator.c | 221 ++++++++++++++++++++++++++++++ 3 files changed, 231 insertions(+) create mode 100644 drivers/regulator/qcom-pm8008-regulator.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index cbe0f96..2c6d9c2 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -925,6 +925,15 @@ config REGULATOR_PWM This driver supports PWM controlled voltage regulators. PWM duty cycle can increase or decrease the voltage. +config REGULATOR_QCOM_PM8008 + tristate "Qualcomm Technologies, Inc. PM8008 PMIC regulators" + depends on MFD_QCOM_PM8008 + help + Select this option to get support for the voltage regulators + of Qualcomm Technologies, Inc. PM8008 PMIC chip. PM8008 has 7 LDO + regulators. This driver provides support for basic operations like + set/get voltage and enable/disable. + config REGULATOR_QCOM_RPM tristate "Qualcomm RPM regulator driver" depends on MFD_QCOM_RPM diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 8d3ee8b..169e686 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o obj-$(CONFIG_REGULATOR_MTK_DVFSRC) += mtk-dvfsrc-regulator.o obj-$(CONFIG_REGULATOR_QCOM_LABIBB) += qcom-labibb-regulator.o +obj-$(CONFIG_REGULATOR_QCOM_PM8008) += qcom-pm8008-regulator.o obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o obj-$(CONFIG_REGULATOR_QCOM_RPMH) += qcom-rpmh-regulator.o obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o diff --git a/drivers/regulator/qcom-pm8008-regulator.c b/drivers/regulator/qcom-pm8008-regulator.c new file mode 100644 index 0000000..0361f02 --- /dev/null +++ b/drivers/regulator/qcom-pm8008-regulator.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VSET_STEP_MV 8 +#define VSET_STEP_UV (VSET_STEP_MV * 1000) + +#define LDO_ENABLE_REG(base) ((base) + 0x46) +#define ENABLE_BIT BIT(7) + +#define LDO_VSET_LB_REG(base) ((base) + 0x40) + +#define LDO_STEPPER_CTL_REG(base) ((base) + 0x3b) +#define DEFAULT_VOLTAGE_STEPPER_RATE 38400 +#define STEP_RATE_MASK GENMASK(1, 0) + +struct pm8008_regulator_data { + const char *name; + const char *supply_name; + int min_uv; + int max_uv; + int min_dropout_uv; + const struct linear_range *voltage_range; +}; + +struct pm8008_regulator { + struct device *dev; + struct regmap *regmap; + struct regulator_desc rdesc; + u16 base; + int step_rate; + int voltage_selector; +}; + +static const struct linear_range nldo_ranges[] = { + REGULATOR_LINEAR_RANGE(528000, 0, 122, 8000), +}; + +static const struct linear_range pldo_ranges[] = { + REGULATOR_LINEAR_RANGE(1504000, 0, 237, 8000), +}; + +static const struct pm8008_regulator_data reg_data[] = { + /* name parent min_uv max_uv headroom_uv voltage_range */ + { "ldo1", "vdd_l1_l2", 528000, 1504000, 225000, nldo_ranges, }, + { "ldo2", "vdd_l1_l2", 528000, 1504000, 225000, nldo_ranges, }, + { "ldo3", "vdd_l3_l4", 1504000, 3400000, 300000, pldo_ranges, }, + { "ldo4", "vdd_l3_l4", 1504000, 3400000, 300000, pldo_ranges, }, + { "ldo5", "vdd_l5", 1504000, 3400000, 200000, pldo_ranges, }, + { "ldo6", "vdd_l6", 1504000, 3400000, 200000, pldo_ranges, }, + { "ldo7", "vdd_l7", 1504000, 3400000, 200000, pldo_ranges, }, +}; + +static int pm8008_regulator_get_voltage(struct regulator_dev *rdev) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + + return pm8008_reg->voltage_selector; +} + +static inline int pm8008_write_voltage(struct pm8008_regulator *pm8008_reg, + int mV) +{ + __le16 vset_raw; + + vset_raw = cpu_to_le16(mV); + + return regmap_bulk_write(pm8008_reg->regmap, + LDO_VSET_LB_REG(pm8008_reg->base), + (const void *)&vset_raw, sizeof(vset_raw)); +} + +static int pm8008_regulator_set_voltage_time(struct regulator_dev *rdev, + int old_uV, int new_uv) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + + return DIV_ROUND_UP(abs(new_uv - old_uV), pm8008_reg->step_rate); +} + +static int pm8008_regulator_set_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + int rc, mV; + + /* voltage control register is set with voltage in millivolts */ + mV = DIV_ROUND_UP(regulator_list_voltage_linear_range(rdev, selector), + 1000); + if (mV < 0) + return mV; + + rc = pm8008_write_voltage(pm8008_reg, mV); + if (rc < 0) + return rc; + + pm8008_reg->voltage_selector = selector; + dev_dbg(&rdev->dev, "voltage set to %d\n", mV * 1000); + return 0; +} + +static const struct regulator_ops pm8008_regulator_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_voltage_sel = pm8008_regulator_set_voltage, + .get_voltage_sel = pm8008_regulator_get_voltage, + .list_voltage = regulator_list_voltage_linear, + .set_voltage_time = pm8008_regulator_set_voltage_time, +}; + +static int pm8008_regulator_probe(struct platform_device *pdev) +{ + int rc, i; + u32 base; + unsigned int reg; + const char *name; + struct device *dev = &pdev->dev; + struct regulator_config reg_config = {}; + struct regulator_dev *rdev; + const struct pm8008_data *chip = dev_get_drvdata(pdev->dev.parent); + struct pm8008_regulator *pm8008_reg; + + pm8008_reg = devm_kzalloc(dev, sizeof(*pm8008_reg), GFP_KERNEL); + if (!pm8008_reg) + return -ENOMEM; + + pm8008_reg->regmap = pm8008_get_regmap(chip); + if (!pm8008_reg->regmap) { + dev_err(dev, "parent regmap is missing\n"); + return -EINVAL; + } + + pm8008_reg->dev = dev; + + rc = of_property_read_string(dev->of_node, "regulator-name", &name); + if (rc) + return rc; + + /* get the required regulator data */ + for (i = 0; i < ARRAY_SIZE(reg_data); i++) + if (strstr(name, reg_data[i].name)) + break; + + rc = of_property_read_u32_index(dev->of_node, "reg", 1, &base); + if (rc < 0) { + dev_err(dev, "%s: failed to get regulator base rc=%d\n", name, rc); + return rc; + } + pm8008_reg->base = base; + + /* get slew rate */ + rc = regmap_bulk_read(pm8008_reg->regmap, + LDO_STEPPER_CTL_REG(pm8008_reg->base), ®, 1); + if (rc < 0) { + dev_err(dev, "failed to read step rate configuration rc=%d\n", rc); + return rc; + } + reg &= STEP_RATE_MASK; + pm8008_reg->step_rate = DEFAULT_VOLTAGE_STEPPER_RATE >> reg; + + pm8008_reg->rdesc.type = REGULATOR_VOLTAGE; + pm8008_reg->rdesc.ops = &pm8008_regulator_ops; + pm8008_reg->rdesc.name = reg_data[i].name; + pm8008_reg->rdesc.supply_name = reg_data[i].supply_name; + pm8008_reg->rdesc.of_match = reg_data[i].name; + pm8008_reg->rdesc.uV_step = VSET_STEP_UV; + pm8008_reg->rdesc.min_uV = reg_data[i].min_uv; + pm8008_reg->rdesc.n_voltages + = ((reg_data[i].max_uv - reg_data[i].min_uv) + / pm8008_reg->rdesc.uV_step) + 1; + pm8008_reg->rdesc.linear_ranges = reg_data[i].voltage_range; + pm8008_reg->rdesc.n_linear_ranges = 1; + pm8008_reg->rdesc.enable_reg = LDO_ENABLE_REG(pm8008_reg->base); + pm8008_reg->rdesc.enable_mask = ENABLE_BIT; + pm8008_reg->rdesc.min_dropout_uV = reg_data[i].min_dropout_uv; + pm8008_reg->voltage_selector = -ENOTRECOVERABLE; + + reg_config.dev = dev->parent; + reg_config.driver_data = pm8008_reg; + reg_config.regmap = pm8008_reg->regmap; + + rdev = devm_regulator_register(dev, &pm8008_reg->rdesc, ®_config); + if (IS_ERR(rdev)) { + rc = PTR_ERR(rdev); + dev_err(dev, "%s: failed to register regulator rc=%d\n", + reg_data[i].name, rc); + return rc; + } + + return 0; +} + +static const struct of_device_id pm8008_regulator_match_table[] = { + { .compatible = "qcom,pm8008-regulator", }, + { } +}; +MODULE_DEVICE_TABLE(of, pm8008_regulator_match_table); + +static struct platform_driver pm8008_regulator_driver = { + .driver = { + .name = "qcom-pm8008-regulator", + .of_match_table = pm8008_regulator_match_table, + }, + .probe = pm8008_regulator_probe, +}; + +module_platform_driver(pm8008_regulator_driver); + +MODULE_DESCRIPTION("Qualcomm PM8008 PMIC Regulator Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed May 11 13:18:32 2022 Content-Type: text/plain; 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Wed, 11 May 2022 06:19:21 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 8/9] arm64: dts: qcom: pm8008: Add base dts file Date: Wed, 11 May 2022 18:48:32 +0530 Message-ID: <1652275113-10277-9-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add base DTS file for pm8008. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd --- Changes in V12: - None. Changes in V11: - Remove intermediate regulators node and add the ldos under pm8008@8 node. - change the address cells as 2 for pm8008 parent mfd node. - add compatible to register the ldos. - add reg with i2c client offset and address. Changes in V10: - Add regulators under pm8008@8 i.e main mfd node. Changes in V9: - Add single dt file for pm8008 instead of adding files like in V8. arch/arm64/boot/dts/qcom/pm8008.dtsi | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8008.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8008.dtsi b/arch/arm64/boot/dts/qcom/pm8008.dtsi new file mode 100644 index 0000000..5606344 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8008.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2022, The Linux Foundation. All rights reserved. + +&pm8008_bus { + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + #address-cells = <2>; + #size-cells = <0>; + #interrupt-cells = <2>; + + pm8008_l1: ldo1@1,4000 { + compatible = "qcom,pm8008-regulator"; + reg = <0x1 0x4000>; + regulator-name = "pm8008_ldo1"; + }; + + pm8008_l2: ldo2@1,4100 { + compatible = "qcom,pm8008-regulator"; + reg = <0x1 0x4100>; + regulator-name = "pm8008_ldo2"; + }; + + pm8008_l3: ldo3@1,4200 { + compatible = "qcom,pm8008-regulator"; + reg = <0x1 0x4200>; + regulator-name = "pm8008_ldo3"; + }; + + pm8008_l4: ldo4@1,4300 { + compatible = "qcom,pm8008-regulator"; + reg = <0x1 0x4300>; + regulator-name = "pm8008_ldo4"; + }; + + pm8008_l5: ldo5@1,4400 { + compatible = "qcom,pm8008-regulator"; + reg = <0x1 0x4400>; + regulator-name = "pm8008_ldo5"; + }; + + pm8008_l6: ldo6@1,4500 { + compatible = "qcom,pm8008-regulator"; + reg = <0x1 0x4500>; + regulator-name = "pm8008_ldo6"; + }; + + pm8008_l7: ldo7@1,4600 { + compatible = "qcom,pm8008-regulator"; + reg = <0x1 0x4600>; + regulator-name = "pm8008_ldo7"; + }; + }; +}; From patchwork Wed May 11 13:18:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 571877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA8A5C4332F for ; Wed, 11 May 2022 13:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242684AbiEKNU1 (ORCPT ); Wed, 11 May 2022 09:20:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243748AbiEKNTz (ORCPT ); Wed, 11 May 2022 09:19:55 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7360623E2A3; Wed, 11 May 2022 06:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652275191; x=1683811191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=YfT0+uqzgXTXi9KT06D+ODz4hYpjjNqdprrMGF2uXdk=; b=sj2nSzrWC6xq/LR58ixItIuYKRAhL86QE/k61K1uAqlKRuvC5Lf9N3Ai 6BCQ112UX3KDrdkVfSuxL5E8WvqVb075EJftH2hfPEB4WlY6hOH3+Ab+X t5oSwsDYZ7xpp4ra0/2L3CNkMVCP7pWqB8KsqJFZTI7FEY4fnY3Tvo8lk E=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 11 May 2022 06:19:51 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 06:19:50 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:30 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 06:19:26 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V12 9/9] arm64: dts: qcom: sc7280: Add pm8008 support for sc7280-idp Date: Wed, 11 May 2022 18:48:33 +0530 Message-ID: <1652275113-10277-10-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> References: <1652275113-10277-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add pm8008 infra and regulators support for sc7280 idp. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd --- Changes in V12: - None. Changes in V11: - Add ldos and parent supplies directly under pm8008@8 node. Changes in V10: - None. Changes in V9: - Added interrupts properties. Changes in V8: - Add an extra phandle "pm8008_bus" and then include pm8008 dtsi files inside it. - Remove output-high from pm8008_active node. arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 66 ++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 5eb6689..166812e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -271,6 +271,63 @@ }; }; +pm8008_bus: &i2c1 { + status = "okay"; +}; + +#include "pm8008.dtsi" + +&pm8008 { + interrupt-parent = <&tlmm>; + interrupts = <24 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active>; + + reset-gpios = <&pm8350c_gpios 4 GPIO_ACTIVE_LOW>; + + vdd_l1_l2-supply = <&vreg_s8b_1p2>; + vdd_l3_l4-supply = <&vreg_s1b_1p8>; + vdd_l5-supply = <&vreg_bob>; + vdd_l6-supply = <&vreg_bob>; + vdd_l7-supply = <&vreg_bob>; +}; + +&pm8008_l1 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; +}; + +&pm8008_l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1250000>; +}; + +&pm8008_l3 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3000000>; +}; + +&pm8008_l4 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1600000>; +}; + +&pm8008_l5 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3000000>; +}; + +&pm8008_l6 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3000000>; +}; + +&pm8008_l7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; +}; + &qfprom { vcc-supply = <&vreg_l1c_1p8>; }; @@ -383,6 +440,15 @@ drive-strength = <2>; }; +&pm8350c_gpios { + pm8008_active: pm8008-active { + pins = "gpio4"; + function = "normal"; + bias-disable; + power-source = <0>; + }; +}; + &qspi_cs0 { bias-disable; };