From patchwork Thu May 12 17:39:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 572312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78AFCC433F5 for ; Thu, 12 May 2022 17:39:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357125AbiELRji (ORCPT ); Thu, 12 May 2022 13:39:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355439AbiELRji (ORCPT ); Thu, 12 May 2022 13:39:38 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 398C6267096; Thu, 12 May 2022 10:39:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652377177; x=1683913177; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=57zZUQo2XpYyqv/Fq0Q307fjDwWri2ChI3FAS8rHfMs=; b=BIk7ms8iFTjQbBOZm40PjyGlMEmeSHzMZcEWwi2mGIjOhoTXxBeTeNGH LBNJ45zWVBOU1kFs9zE2yNnwDe9sON8/Sg4hFBmfKprcWIHjo0Uq4BFTc X4cCv6xonVfvjvkvOYOKBm2Q7Mlr0T2ea+qgc1LO7KX2MXWU404zGMOyt yEECKrUH6lDbGjoLiGWy4t/S9eu3vWA7ZVoGhTmJBF6BPRirXDqGtI/4+ KONCCoN5EJMz0yM7hPdufBgalhNoAb9j6/9UjLxaDHx00GxOJqleZAsou UiGMZiMaz6ubMC0yq8mfgRptTVEaqBhA6Mn1EXuWBpY0KCdnWhxZUffJa g==; X-IronPort-AV: E=McAfee;i="6400,9594,10345"; a="330691118" X-IronPort-AV: E=Sophos;i="5.91,220,1647327600"; d="scan'208";a="330691118" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2022 10:39:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,220,1647327600"; d="scan'208";a="594787760" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga008.jf.intel.com with ESMTP; 12 May 2022 10:39:33 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 378A9CE; Thu, 12 May 2022 20:39:32 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Marc Zyngier , Hans de Goede , linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Mika Westerberg , Andy Shevchenko Subject: [PATCH v1 1/5] Documentation: gpio: Fix IRQ mask and unmask examples Date: Thu, 12 May 2022 20:39:17 +0300 Message-Id: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org After switching to immutable IRQ chips for GPIO drivers the examples become uncompilable due to wrong IRQ API, i.e. irq_desc_get_handler_data() in use. Replace it with proper irq_data_get_irq_chip_data() call where it applies. Fixes: 5644b66a9c63 ("Documentation: Update the recommended pattern for GPIO irqchips") Signed-off-by: Andy Shevchenko Reviewed-by: Linus Walleij --- Documentation/driver-api/gpio/driver.rst | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/driver-api/gpio/driver.rst index a1ddefa1f55f..964d09118d17 100644 --- a/Documentation/driver-api/gpio/driver.rst +++ b/Documentation/driver-api/gpio/driver.rst @@ -429,7 +429,7 @@ call into the core gpiolib code: static void my_gpio_mask_irq(struct irq_data *d) { - struct gpio_chip *gc = irq_desc_get_handler_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); /* * Perform any necessary action to mask the interrupt, @@ -442,7 +442,7 @@ call into the core gpiolib code: static void my_gpio_unmask_irq(struct irq_data *d) { - struct gpio_chip *gc = irq_desc_get_handler_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); gpiochip_enable_irq(gc, d->hwirq); @@ -501,7 +501,7 @@ the interrupt separately and go with it: static void my_gpio_mask_irq(struct irq_data *d) { - struct gpio_chip *gc = irq_desc_get_handler_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); /* * Perform any necessary action to mask the interrupt, @@ -514,7 +514,7 @@ the interrupt separately and go with it: static void my_gpio_unmask_irq(struct irq_data *d) { - struct gpio_chip *gc = irq_desc_get_handler_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); gpiochip_enable_irq(gc, d->hwirq); @@ -576,7 +576,7 @@ In this case the typical set-up will look like this: static void my_gpio_mask_irq(struct irq_data *d) { - struct gpio_chip *gc = irq_desc_get_handler_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); /* * Perform any necessary action to mask the interrupt, @@ -590,7 +590,7 @@ In this case the typical set-up will look like this: static void my_gpio_unmask_irq(struct irq_data *d) { - struct gpio_chip *gc = irq_desc_get_handler_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); gpiochip_enable_irq(gc, d->hwirq); From patchwork Thu May 12 17:39:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 572310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B8F9C433EF for ; Thu, 12 May 2022 17:42:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357168AbiELRmC (ORCPT ); Thu, 12 May 2022 13:42:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357183AbiELRl5 (ORCPT ); Thu, 12 May 2022 13:41:57 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BD2E60BAB; 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d="scan'208";a="712025245" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 12 May 2022 10:39:34 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 4609A45; Thu, 12 May 2022 20:39:33 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Marc Zyngier , Hans de Goede , linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Mika Westerberg , Andy Shevchenko Subject: [PATCH v1 2/5] Documentation: gpio: Advertise irqd_to_hwirq() helper in the examples Date: Thu, 12 May 2022 20:39:18 +0300 Message-Id: <20220512173921.8210-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> References: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Instead of direct dereferencing the IRQ data in order to get HW IRQ number use the irqd_to_hwirq() helper. Fixes: 5644b66a9c63 ("Documentation: Update the recommended pattern for GPIO irqchips") Signed-off-by: Andy Shevchenko --- Documentation/driver-api/gpio/driver.rst | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/driver-api/gpio/driver.rst index 964d09118d17..70ff43ac4fcc 100644 --- a/Documentation/driver-api/gpio/driver.rst +++ b/Documentation/driver-api/gpio/driver.rst @@ -430,6 +430,7 @@ call into the core gpiolib code: static void my_gpio_mask_irq(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); /* * Perform any necessary action to mask the interrupt, @@ -437,14 +438,15 @@ call into the core gpiolib code: * state. */ - gpiochip_disable_irq(gc, d->hwirq); + gpiochip_disable_irq(gc, hwirq); } static void my_gpio_unmask_irq(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); - gpiochip_enable_irq(gc, d->hwirq); + gpiochip_enable_irq(gc, hwirq); /* * Perform any necessary action to unmask the interrupt, @@ -502,6 +504,7 @@ the interrupt separately and go with it: static void my_gpio_mask_irq(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); /* * Perform any necessary action to mask the interrupt, @@ -509,14 +512,15 @@ the interrupt separately and go with it: * state. */ - gpiochip_disable_irq(gc, d->hwirq); + gpiochip_disable_irq(gc, hwirq); } static void my_gpio_unmask_irq(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); - gpiochip_enable_irq(gc, d->hwirq); + gpiochip_enable_irq(gc, hwirq); /* * Perform any necessary action to unmask the interrupt, @@ -577,6 +581,7 @@ In this case the typical set-up will look like this: static void my_gpio_mask_irq(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); /* * Perform any necessary action to mask the interrupt, @@ -584,15 +589,16 @@ In this case the typical set-up will look like this: * state. */ - gpiochip_disable_irq(gc, d->hwirq); + gpiochip_disable_irq(gc, hwirq); irq_mask_mask_parent(d); } static void my_gpio_unmask_irq(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); - gpiochip_enable_irq(gc, d->hwirq); + gpiochip_enable_irq(gc, hwirq); /* * Perform any necessary action to unmask the interrupt, From patchwork Thu May 12 17:39:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 571920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58661C433EF for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10345"; a="330691123" X-IronPort-AV: E=Sophos;i="5.91,220,1647327600"; d="scan'208";a="330691123" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2022 10:39:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,220,1647327600"; d="scan'208";a="594787761" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga008.jf.intel.com with ESMTP; 12 May 2022 10:39:34 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 4F3ACD2; Thu, 12 May 2022 20:39:33 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Marc Zyngier , Hans de Goede , linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Mika Westerberg , Andy Shevchenko Subject: [PATCH v1 3/5] pinctrl: baytrail: make irq_chip immutable Date: Thu, 12 May 2022 20:39:19 +0300 Message-Id: <20220512173921.8210-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> References: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch to use hwirq variable instead of offset for the sake of consistency. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-baytrail.c | 42 ++++++++++++++---------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index f89c9fcd4e1b..31f8f271628c 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1350,15 +1350,15 @@ static void byt_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *vg = gpiochip_get_data(gc); - unsigned int offset = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); void __iomem *reg; - reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG); + reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG); if (!reg) return; raw_spin_lock(&byt_lock); - writel(BIT(offset % 32), reg); + writel(BIT(hwirq % 32), reg); raw_spin_unlock(&byt_lock); } @@ -1366,20 +1366,24 @@ static void byt_irq_mask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *vg = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(d); - byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); + byt_gpio_clear_triggering(vg, hwirq); + gpiochip_disable_irq(gc, hwirq); } static void byt_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *vg = gpiochip_get_data(gc); - unsigned int offset = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); unsigned long flags; void __iomem *reg; u32 value; - reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); + gpiochip_enable_irq(gc, hwirq); + + reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); if (!reg) return; @@ -1412,12 +1416,13 @@ static void byt_irq_unmask(struct irq_data *d) static int byt_irq_type(struct irq_data *d, unsigned int type) { struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); - u32 offset = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); u32 value; unsigned long flags; - void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); + void __iomem *reg; - if (!reg || offset >= vg->chip.ngpio) + reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); + if (!reg) return -EINVAL; raw_spin_lock_irqsave(&byt_lock, flags); @@ -1447,6 +1452,16 @@ static int byt_irq_type(struct irq_data *d, unsigned int type) return 0; } +static const struct irq_chip byt_gpio_irq_chip = { + .name = "BYT-GPIO", + .irq_ack = byt_irq_ack, + .irq_mask = byt_irq_mask, + .irq_unmask = byt_irq_unmask, + .irq_set_type = byt_irq_type, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static void byt_gpio_irq_handler(struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); @@ -1633,15 +1648,8 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) if (irq > 0) { struct gpio_irq_chip *girq; - vg->irqchip.name = "BYT-GPIO", - vg->irqchip.irq_ack = byt_irq_ack, - vg->irqchip.irq_mask = byt_irq_mask, - vg->irqchip.irq_unmask = byt_irq_unmask, - vg->irqchip.irq_set_type = byt_irq_type, - vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED, - girq = &gc->irq; - girq->chip = &vg->irqchip; + gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip); girq->init_hw = byt_gpio_irq_init_hw; girq->init_valid_mask = byt_init_irq_valid_mask; girq->parent_handler = byt_gpio_irq_handler; From patchwork Thu May 12 17:39:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 572311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1838FC4332F for ; Thu, 12 May 2022 17:39:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357138AbiELRjn (ORCPT ); Thu, 12 May 2022 13:39:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357130AbiELRjj (ORCPT ); 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12 May 2022 10:39:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,220,1647327600"; d="scan'208";a="698140588" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga004.jf.intel.com with ESMTP; 12 May 2022 10:39:34 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 5D60E109; Thu, 12 May 2022 20:39:33 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Marc Zyngier , Hans de Goede , linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Mika Westerberg , Andy Shevchenko Subject: [PATCH v1 4/5] pinctrl: cherryview: make irq_chip immutable Date: Thu, 12 May 2022 20:39:20 +0300 Message-Id: <20220512173921.8210-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> References: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch to use hwirq variable instead of pin for the sake of consistency. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 65 +++++++++++++--------- 1 file changed, 38 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 1d5818269076..b696f9392789 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1242,12 +1242,12 @@ static void chv_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); - int pin = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); u32 intr_line; raw_spin_lock(&chv_lock); - intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0); + intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); intr_line &= CHV_PADCTRL0_INTSEL_MASK; intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line)); @@ -1255,17 +1255,16 @@ static void chv_gpio_irq_ack(struct irq_data *d) raw_spin_unlock(&chv_lock); } -static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) +static void chv_gpio_irq_mask_unmask(struct irq_data *d, irq_hw_number_t hwirq, bool mask) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); - int pin = irqd_to_hwirq(d); u32 value, intr_line; unsigned long flags; raw_spin_lock_irqsave(&chv_lock, flags); - intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0); + intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); intr_line &= CHV_PADCTRL0_INTSEL_MASK; intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; @@ -1281,12 +1280,20 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) static void chv_gpio_irq_mask(struct irq_data *d) { - chv_gpio_irq_mask_unmask(d, true); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + chv_gpio_irq_mask_unmask(d, hwirq, true); + gpiochip_disable_irq(gc, hwirq); } static void chv_gpio_irq_unmask(struct irq_data *d) { - chv_gpio_irq_mask_unmask(d, false); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + gpiochip_enable_irq(gc, hwirq); + chv_gpio_irq_mask_unmask(d, hwirq, false); } static unsigned chv_gpio_irq_startup(struct irq_data *d) @@ -1306,17 +1313,17 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) struct intel_pinctrl *pctrl = gpiochip_get_data(gc); struct device *dev = pctrl->dev; struct intel_community_context *cctx = &pctrl->context.communities[0]; - unsigned int pin = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); irq_flow_handler_t handler; unsigned long flags; u32 intsel, value; raw_spin_lock_irqsave(&chv_lock, flags); - intsel = chv_readl(pctrl, pin, CHV_PADCTRL0); + intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0); intsel &= CHV_PADCTRL0_INTSEL_MASK; intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; - value = chv_readl(pctrl, pin, CHV_PADCTRL1); + value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) handler = handle_level_irq; else @@ -1324,9 +1331,9 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { irq_set_handler_locked(d, handler); - dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %u\n", - intsel, pin); - cctx->intr_lines[intsel] = pin; + dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n", + intsel, hwirq); + cctx->intr_lines[intsel] = hwirq; } raw_spin_unlock_irqrestore(&chv_lock, flags); } @@ -1392,14 +1399,14 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); - unsigned int pin = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); unsigned long flags; u32 value; int ret; raw_spin_lock_irqsave(&chv_lock, flags); - ret = chv_gpio_set_intr_line(pctrl, pin); + ret = chv_gpio_set_intr_line(pctrl, hwirq); if (ret) goto out_unlock; @@ -1416,8 +1423,8 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) * 2. If the pin cfg is not locked in BIOS: * Driver programs the IntWakeCfg bits and save the mapping. */ - if (!chv_pad_locked(pctrl, pin)) { - value = chv_readl(pctrl, pin, CHV_PADCTRL1); + if (!chv_pad_locked(pctrl, hwirq)) { + value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; value &= ~CHV_PADCTRL1_INVRXTX_MASK; @@ -1434,7 +1441,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) value |= CHV_PADCTRL1_INVRXTX_RXDATA; } - chv_writel(pctrl, pin, CHV_PADCTRL1, value); + chv_writel(pctrl, hwirq, CHV_PADCTRL1, value); } if (type & IRQ_TYPE_EDGE_BOTH) @@ -1448,6 +1455,17 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) return ret; } +static const struct irq_chip chv_gpio_irq_chip = { + .name = "chv-gpio", + .irq_startup = chv_gpio_irq_startup, + .irq_ack = chv_gpio_irq_ack, + .irq_mask = chv_gpio_irq_mask, + .irq_unmask = chv_gpio_irq_unmask, + .irq_set_type = chv_gpio_irq_type, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static void chv_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); @@ -1611,15 +1629,8 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) chip->base = -1; pctrl->irq = irq; - pctrl->irqchip.name = "chv-gpio"; - pctrl->irqchip.irq_startup = chv_gpio_irq_startup; - pctrl->irqchip.irq_ack = chv_gpio_irq_ack; - pctrl->irqchip.irq_mask = chv_gpio_irq_mask; - pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask; - pctrl->irqchip.irq_set_type = chv_gpio_irq_type; - pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE; - - chip->irq.chip = &pctrl->irqchip; + + gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip); chip->irq.init_hw = chv_gpio_irq_init_hw; chip->irq.parent_handler = chv_gpio_irq_handler; chip->irq.num_parents = 1; From patchwork Thu May 12 17:39:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 571919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90FC1C433FE for ; Thu, 12 May 2022 17:40:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356983AbiELRkQ (ORCPT ); Thu, 12 May 2022 13:40:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357140AbiELRkO (ORCPT ); Thu, 12 May 2022 13:40:14 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 029EA26C4C5; Thu, 12 May 2022 10:40:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652377214; x=1683913214; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lfHOk3NbKnCzKqrFFON5C5D8NThthEjbjuQAmQX0Sco=; b=iNYtBVvUHVu/lm8x6WVos/NsUubUpvWOj80OmAzEyLs26iD56KOJq+rv 4NNkpWIzMrzLSOIeKcUSSeMznfY7Y3hBH72ujY8tgbu3vZkbqg49GuxkV s3DswyUo9QpHJa1cTxxWt+s3ZiQejO3G6Kh3TNh4ySfFhv0qOti75rb3o QFyc/xkliO0IT9p5UA8qBZZvSf7n0rcxeuELxTSlzBXxGr4UlUTM/k725 soj/hCgV+y/0mZ+B2POK5qraJgwSH+Vd7moCW/mvLOULGwM5+P+/pfUSW Iqa1tbm9B4COc7nWxok5DUuXlzuIi0P2WD1979hqY9RsLV2TjvjUOXvvG A==; X-IronPort-AV: E=McAfee;i="6400,9594,10345"; a="257634327" X-IronPort-AV: E=Sophos;i="5.91,220,1647327600"; d="scan'208";a="257634327" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2022 10:39:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,220,1647327600"; d="scan'208";a="542883705" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga006.jf.intel.com with ESMTP; 12 May 2022 10:39:34 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 6698C103; Thu, 12 May 2022 20:39:33 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Marc Zyngier , Hans de Goede , linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Mika Westerberg , Andy Shevchenko Subject: [PATCH v1 5/5] pinctrl: lynxpoint: make irq_chip immutable Date: Thu, 12 May 2022 20:39:21 +0300 Message-Id: <20220512173921.8210-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> References: <20220512173921.8210-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch hwirq variable to use the correct type for the sake of consistency. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 26 ++++++++++++++--------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 561fa322b0b4..4fb39eb30902 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -663,7 +663,7 @@ static void lp_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *lg = gpiochip_get_data(gc); - u32 hwirq = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); unsigned long flags; @@ -684,10 +684,12 @@ static void lp_irq_enable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *lg = gpiochip_get_data(gc); - u32 hwirq = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); unsigned long flags; + gpiochip_enable_irq(gc, hwirq); + raw_spin_lock_irqsave(&lg->lock, flags); iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); raw_spin_unlock_irqrestore(&lg->lock, flags); @@ -697,30 +699,33 @@ static void lp_irq_disable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *lg = gpiochip_get_data(gc); - u32 hwirq = irqd_to_hwirq(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); unsigned long flags; raw_spin_lock_irqsave(&lg->lock, flags); iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); raw_spin_unlock_irqrestore(&lg->lock, flags); + + gpiochip_disable_irq(gc, hwirq); } static int lp_irq_set_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *lg = gpiochip_get_data(gc); - u32 hwirq = irqd_to_hwirq(d); - void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); + irq_hw_number_t hwirq = irqd_to_hwirq(d); unsigned long flags; + void __iomem *reg; u32 value; - if (hwirq >= lg->chip.ngpio) + reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); + if (!reg) return -EINVAL; /* Fail if BIOS reserved pin for ACPI use */ if (lp_gpio_acpi_use(lg, hwirq)) { - dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq); + dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq); return -EBUSY; } @@ -755,7 +760,7 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type) return 0; } -static struct irq_chip lp_irqchip = { +static const struct irq_chip lp_irqchip = { .name = "LP-GPIO", .irq_ack = lp_irq_ack, .irq_mask = lp_irq_mask, @@ -763,7 +768,8 @@ static struct irq_chip lp_irqchip = { .irq_enable = lp_irq_enable, .irq_disable = lp_irq_disable, .irq_set_type = lp_irq_set_type, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static int lp_gpio_irq_init_hw(struct gpio_chip *chip) @@ -884,7 +890,7 @@ static int lp_gpio_probe(struct platform_device *pdev) struct gpio_irq_chip *girq; girq = &gc->irq; - girq->chip = &lp_irqchip; + gpio_irq_chip_set_chip(girq, &lp_irqchip); girq->init_hw = lp_gpio_irq_init_hw; girq->parent_handler = lp_gpio_irq_handler; girq->num_parents = 1;