From patchwork Fri May 13 17:16:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 572263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B664C4332F for ; Fri, 13 May 2022 17:16:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382807AbiEMRQb (ORCPT ); Fri, 13 May 2022 13:16:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382380AbiEMRQ0 (ORCPT ); Fri, 13 May 2022 13:16:26 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 572E5DE96; Fri, 13 May 2022 10:16:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 5AB5E1F463B2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652462183; bh=BzU2sp5uWjhJVZc+Pbqb4F7Rd9WBetm2NBJji/SvJBY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OJc97YFlkTW3xxg3GtC7OakusKIMZYM+wuXAKWighauBw2uJyGzcfsqcZsz5VqAFV RWishoAgfjZz2c6TXEZNMSIdNs+CdyUZq4pOwkTSmAWDwR7mlPxF06Ms0g4FvKVO2f vufJLWmDKnassIyseehNSh9pnQItHF4Ey6NLn0MpTqGGDMdX1PZviBrxkfrwOiDQAz gg76nc47QF79upQAdOhoce2wBekySwSMBh1LptMzI5CT/bV1vtJDymEgo78rIZZsYS r2q4xDGBHHNcTGYr2AwhPET+H9AeuKw80Ff/tt8gh7iZ/s+HG81g5spjKk/fCsUB7J sJ/QYWoHK2ijg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com, AngeloGioacchino Del Regno Subject: [PATCH 1/7] arm64: dts: mediatek: mt6795: Create soc bus node and move mmio devices Date: Fri, 13 May 2022 19:16:11 +0200 Message-Id: <20220513171617.504430-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> References: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MMIO devices should be inside of a soc bus node, as it's done for the vast majority of ARM64 devicetrees, and for almost all MTK devicetrees. Create a simple-bus soc node and move all devices with a MMIO address space in there. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 105 ++++++++++++----------- 1 file changed, 56 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index c85659d0ff5d..167f90bd991a 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -117,59 +117,66 @@ timer { (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6795-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt6795-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; - gic: interrupt-controller@10221000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10221000 0 0x1000>, - <0 0x10222000 0 0x2000>, - <0 0x10224000 0 0x2000>, - <0 0x10226000 0 0x2000>; - }; + gic: interrupt-controller@10221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10221000 0 0x1000>, + <0 0x10222000 0 0x2000>, + <0 0x10224000 0 0x2000>, + <0 0x10226000 0 0x2000>; + }; - uart0: serial@11002000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; + uart0: serial@11002000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; - uart1: serial@11003000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; + uart1: serial@11003000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; - uart2: serial@11004000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; + uart2: serial@11004000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; - uart3: serial@11005000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; + uart3: serial@11005000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; }; }; From patchwork Fri May 13 17:16:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 572264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1A09C43217 for ; Fri, 13 May 2022 17:16:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382801AbiEMRQ2 (ORCPT ); Fri, 13 May 2022 13:16:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382779AbiEMRQ1 (ORCPT ); Fri, 13 May 2022 13:16:27 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DEB463A0; Fri, 13 May 2022 10:16:25 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 4B9C61F463B6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652462184; bh=6b5Fn00QFN3S8pk3LiXp3oowU6+YetKGNFXGTWU1NeQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S5rfzoUU1xMstwvoem9aQMqhyD6+D+l3IzMQ2gv3FhEHZWP3irW9F1hY5Z1u8Ge2b rhu8YwtB/1D5un8uqnNgU7CvrQRvgFRAXXc/LZnuBb3tZ5gEkRa8NRCvd502VTygfH T+b7LhLPTB60WIS2Kfwm62TMUPcYw9tY5p2C4B4seDTSnwiJ8Exy9NymG7b3HV/oM0 eQ+UAANxW41CqUsPR8XZRzcw18NyQbGSP7MUpTwtUflaIMwYf/qvJX6gEhASghzPF9 ZJyveqBm5OhnjoyeEYmq0/PwID7d9/u7Qm/dkJZFRV0Tg9cvCc1TLZmOiqTrnbRxWr dBldG/nYsyYWA== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com, AngeloGioacchino Del Regno Subject: [PATCH 2/7] arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache Date: Fri, 13 May 2022 19:16:12 +0200 Message-Id: <20220513171617.504430-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> References: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This SoC is HMP and has two clusters with four Cortex-A53 cores each: declare a cpu map and, while at it, also add the next-level-cache properties. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 56 ++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 167f90bd991a..1456b9035336 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -34,6 +34,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x000>; + next-level-cache = <&l2_0>; }; cpu1: cpu@1 { @@ -41,6 +42,7 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x001>; + next-level-cache = <&l2_0>; }; cpu2: cpu@2 { @@ -48,6 +50,7 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x002>; + next-level-cache = <&l2_0>; }; cpu3: cpu@3 { @@ -55,6 +58,7 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x003>; + next-level-cache = <&l2_0>; }; cpu4: cpu@100 { @@ -62,6 +66,7 @@ cpu4: cpu@100 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x100>; + next-level-cache = <&l2_1>; }; cpu5: cpu@101 { @@ -69,6 +74,7 @@ cpu5: cpu@101 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x101>; + next-level-cache = <&l2_1>; }; cpu6: cpu@102 { @@ -76,6 +82,7 @@ cpu6: cpu@102 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x102>; + next-level-cache = <&l2_1>; }; cpu7: cpu@103 { @@ -83,6 +90,55 @@ cpu7: cpu@103 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x103>; + next-level-cache = <&l2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; }; }; From patchwork Fri May 13 17:16:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 572665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F9CEC433EF for ; Fri, 13 May 2022 17:16:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382805AbiEMRQ3 (ORCPT ); Fri, 13 May 2022 13:16:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382780AbiEMRQ1 (ORCPT ); Fri, 13 May 2022 13:16:27 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25E5363FF; Fri, 13 May 2022 10:16:26 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 3C4F31F463B9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652462185; bh=+SNQosugZ3rRLzeC91179/d1xD7fpoErRAwb547pmRM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XWKopfN0gCAevdMs64GrFGRQOoXOWOZ5dEbZuDUJ/CfmDvVIP/DIRM49p9aEv0Erv pLkOpeIUHtpk8LLXs0b0zqommLAo6ctdZ5HVztrATXa8QHC5UX1Ig4h3dQwwkgFM+M SrrejUVWOGN6ACEUd17B2N6ov+dEJneNr+JWygg37z9Ntf0VqS1wtJWj72TqiA26v7 v7xWklVkDa3B4Bs8dglaW3EV9GFo3cBMe/PAOY72ZF0AEQ7A9V9BVNliog63roMQV3 2CGMUCEOd6yiR/hwHKASMEmD1rDPF4epMoLeTIFcuoze2UFxscKK9x4Qey/2mvgBQ6 cAnqszV9VLFKw== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com, AngeloGioacchino Del Regno Subject: [PATCH 3/7] arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes Date: Fri, 13 May 2022 19:16:13 +0200 Message-Id: <20220513171617.504430-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> References: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the required nodes to enable the PMU on this SoC. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 1456b9035336..639104b3f693 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -160,6 +160,15 @@ uart_clk: dummy26m { #clock-cells = <0>; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; From patchwork Fri May 13 17:16:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 572664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BBF9C43217 for ; Fri, 13 May 2022 17:16:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382819AbiEMRQc (ORCPT ); Fri, 13 May 2022 13:16:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382803AbiEMRQ3 (ORCPT ); Fri, 13 May 2022 13:16:29 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91BFDAE62; Fri, 13 May 2022 10:16:27 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 2C9D51F463BB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652462186; bh=a4rg/JyrfKEPVSNVifJkG8mIf7X7Pe0ajY4dp1vpzts=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AfWFvY/LXmYBQIPzMB7wxWUuxS6pAK8vApDF+K4NY2W+Ul10s0F1N8Z2HVG/akls8 p4im//lbntV6csv9ohgvSXR3dNxOMGh/Yqm3r+0zTPXFDZDerhVGR9pm9NcaATYuNm izkpuaOCaD6epbiQ6Uc0fqHcnNfLkoqetDY8MBwdg3tdj6fwPH16s0yiNsXgom+2W0 Gv1RRZwHaIDMHKH3GDiyKQVvz5R1+9HQ5kjGDx0cze0iM1Z0/M2VUlWyR+37NPEWof JJB59E1OrlcgnVIIVH2c6PrqiVxR8mFtiI4h0LVgwvJmDBhCLuzKCCfAL7UKEB16dn Gm1HPnQcylfgg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com, AngeloGioacchino Del Regno Subject: [PATCH 4/7] arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts Date: Fri, 13 May 2022 19:16:14 +0200 Message-Id: <20220513171617.504430-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> References: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At least on commercial devices like some smartphones, the bootloader will initialize the SoC watchdog and set it to reboot the board when it times out. The last pet that this watchdog is getting is right before booting the kernel and left it enabled as a protection against boot failure: this means that Linux is expected to initialize this device and pet as soon as possible, or it will bark and reset the AP. In order to prevent that, add the required watchdog node as default enabled: this will have no side effects on boards that are not performing the aforementioned watchdog setup before booting Linux. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 639104b3f693..363fa25b4edc 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -188,6 +188,14 @@ soc { compatible = "simple-bus"; ranges; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6795-wdt"; + reg = <0 0x10007000 0 0x100>; + interrupts = ; + #reset-cells = <1>; + timeout-sec = <20>; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq"; From patchwork Fri May 13 17:16:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 572663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D832AC433EF for ; Fri, 13 May 2022 17:16:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382852AbiEMRQu (ORCPT ); Fri, 13 May 2022 13:16:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382835AbiEMRQk (ORCPT ); Fri, 13 May 2022 13:16:40 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E7CA3122B; Fri, 13 May 2022 10:16:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 9A82C1F463B2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652462187; bh=xHDizGEAS5CEUxEZaxa3laKX/jFEH45gEkIh0l+Zvvk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=norOKTi32tuUwqGq38L3Hc4rQbrVKvPwvxJ3Nj/2aEw5sd8upvUxOAaR+YWmKI9F3 nDQr2MUsdwQ1ksgr94q5xytYzl83x9hX2EpZeGZWdTbJZyqTBcdmqPpIqEJVYecyfn inVEIsFvYifnB9JyLEl+KF0FmKDrDInSYiycOwl8lllrx23et5EUFJCry+ubx34xkf PwA3j7UpPVQo8DIeH/PxUp915eKaJfU8eVC0KKxg3+TXWAKl7Hu++qOmYHeAGuuf7g xwRRpCFR6sH2uuC12t92Uh88FOSOmcA8QZFp1MhDJTiRFggczrDajx03dIagDPp7J0 zLXrReUdCMDeA== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com, AngeloGioacchino Del Regno Subject: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs Date: Fri, 13 May 2022 19:16:15 +0200 Message-Id: <20220513171617.504430-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> References: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to provide a good initial clock spec, since this SoC features two always on oscillators running at the aforementioned frequencies. While at it, since the UART clock is actually referring to the 26MHz oscillator, remove it and assign clk26m as "baud" clock for the UARTs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 363fa25b4edc..b6f7681cc151 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -142,21 +142,23 @@ l2_1: l2-cache1 { }; }; - system_clk: dummy13m { + clk26m: oscillator-26m { compatible = "fixed-clock"; - clock-frequency = <13000000>; #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; }; - rtc_clk: dummy32k { + clk32k: oscillator-32k { compatible = "fixed-clock"; - clock-frequency = <32000>; #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; }; - uart_clk: dummy26m { + system_clk: dummy13m { compatible = "fixed-clock"; - clock-frequency = <26000000>; + clock-frequency = <13000000>; #clock-cells = <0>; }; @@ -221,7 +223,7 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -230,7 +232,7 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -239,7 +241,7 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -248,7 +250,7 @@ uart3: serial@11005000 { "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; }; From patchwork Fri May 13 17:16:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 572262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06AACC433F5 for ; Fri, 13 May 2022 17:16:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382872AbiEMRQu (ORCPT ); Fri, 13 May 2022 13:16:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382848AbiEMRQn (ORCPT ); Fri, 13 May 2022 13:16:43 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 198E831352; Fri, 13 May 2022 10:16:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 488201F463D1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652462198; bh=bX8kZUebSBXb8b4ayhewUrKLvLfjaP3abnUzIjQpOJE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JVxyWUmI1D7+Pv0K9rI8B+kMa+Iv79PWC62wZch+NECBujlLvTGnlfYypq14w+eQZ JbudmRcwzweCDGRENMHNh1kiduLAWBZ9i514IpI3Oqxr0DRBOA+jz3lnBGSpvZneJi hkPm0YhLaWBjr6xSZiuUtf4CYo4zDwfaA/WixD+3eu33EWGcf5dqkZoGbSN+5IXbkY oapP2AXY/gk2WaoLKCraHhackKyybLjJmahDX4SCQQ0LT+XyFD7qx1CXkJU8Sya7Jx 4jpqQX5zeRud7w8cRgk5RMKJNrmjyKl6EBhvGfanIzaV5UXyLxn7D5OgEwWGFwiV/8 D4gsrJWsY6OtA== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com, AngeloGioacchino Del Regno Subject: [PATCH 6/7] arm64: dts: mediatek: mt6795: Add general purpose timer node Date: Fri, 13 May 2022 19:16:16 +0200 Message-Id: <20220513171617.504430-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> References: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the timer node, enabling two GPTs, of which one will be used as sched_clock. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index b6f7681cc151..217d99621558 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -198,6 +198,14 @@ watchdog: watchdog@10007000 { timeout-sec = <20>; }; + timer: timer@10008000 { + compatible = "mediatek,mt6795-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = ; + clocks = <&system_clk>, <&clk32k>; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq"; From patchwork Fri May 13 17:16:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 572261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B663C4332F for ; Fri, 13 May 2022 17:16:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382911AbiEMRQw (ORCPT ); Fri, 13 May 2022 13:16:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382864AbiEMRQt (ORCPT ); Fri, 13 May 2022 13:16:49 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05639DF93; Fri, 13 May 2022 10:16:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 275411F463B0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652462198; bh=u2SRqTpnqi7EaYL6hrMeHhetZF1DSjSsk+5BaLSaDYU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZeWZhdG9YtV3hpkjxhdOPtmSe3qvvFh+9VjDugbUZDzCglh5Qperba9fLxK7mMFZW A/fCGOvGjD08wpU9biJQVkR8gLlVlZB6kAcRKQ+9InH+sShRXLKiPWJmiB8kLVD/SS rGVz4MqGzv8s1yiQQINsRHigYZ3BcYkP7QQvt//GCRcg+blgNV2BPhCeeZUiEF8S7N nXEwS3yWdbS42g1dHcHU9gOxhcqePwK0loK1h90mkVj3HzG/qpYXYmfhOfQWGk12ou 1to3/yU4wjy+BqpkH70qwqhBWJ9ckOz/vbkpkB9stSxMydRV7JFWYNwGd12/qDDyVo rLmJ4ye5ggRVw== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com, AngeloGioacchino Del Regno Subject: [PATCH 7/7] arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs Date: Fri, 13 May 2022 19:16:17 +0200 Message-Id: <20220513171617.504430-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> References: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This SoC features an ARM CCI-400 IP: add the required node and assign the cci control ports to the CPU cores. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 217d99621558..db1f24b3b9a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -34,6 +34,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x000>; + cci-control-port = <&cci_control2>; next-level-cache = <&l2_0>; }; @@ -42,6 +43,7 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x001>; + cci-control-port = <&cci_control2>; next-level-cache = <&l2_0>; }; @@ -50,6 +52,7 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x002>; + cci-control-port = <&cci_control2>; next-level-cache = <&l2_0>; }; @@ -58,6 +61,7 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x003>; + cci-control-port = <&cci_control2>; next-level-cache = <&l2_0>; }; @@ -66,6 +70,7 @@ cpu4: cpu@100 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x100>; + cci-control-port = <&cci_control1>; next-level-cache = <&l2_1>; }; @@ -74,6 +79,7 @@ cpu5: cpu@101 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x101>; + cci-control-port = <&cci_control1>; next-level-cache = <&l2_1>; }; @@ -82,6 +88,7 @@ cpu6: cpu@102 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x102>; + cci-control-port = <&cci_control1>; next-level-cache = <&l2_1>; }; @@ -90,6 +97,7 @@ cpu7: cpu@103 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x103>; + cci-control-port = <&cci_control1>; next-level-cache = <&l2_1>; }; @@ -226,6 +234,42 @@ gic: interrupt-controller@10221000 { <0 0x10226000 0 0x2000>; }; + cci: cci@10390000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x10390000 0 0x1000>; + ranges = <0 0 0x10390000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = , + , + , + , + ; + }; + }; + uart0: serial@11002000 { compatible = "mediatek,mt6795-uart", "mediatek,mt6577-uart";