From patchwork Mon May 16 16:06:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 573077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0E98C43217 for ; Mon, 16 May 2022 16:07:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245217AbiEPQHx (ORCPT ); Mon, 16 May 2022 12:07:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245725AbiEPQHp (ORCPT ); Mon, 16 May 2022 12:07:45 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98D9737A90; Mon, 16 May 2022 09:07:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 33DD760FF0; Mon, 16 May 2022 16:07:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C11BBC385AA; Mon, 16 May 2022 16:07:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717262; bh=jjinRlKFxifScyEw3OjetYoQ52Kq5EtAMT5xBGYx7aA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EpwkWTUByEhFiRMI9BJxFC8C1LSTZEt75kW4RdxXupXCUZQXPHs1VspfG6Xp+FR+n TrjRKGpPPxt3YzZuGaYvgdgB5ldyt3q4bxkzE3krvqQDEudVof11C2r3PytplSOqlo PJYb2L3W4oAG81w4BJzxT9ngbRZq6pjRn2iPcXcN/ZoVQhvknMf7PC/yTS77hr+0t9 PukHu6Fwa/e+QAADrDMP/UPnqAKCeZtLzqN4U11m7D1oSoT1+LpbVeJrfouKaCKYQH ocKAeCR9k/e7v6VDXA/3dxQrsAmC2cpImLezD/vQHZ5REdlyUpdAJyl3CMqEEqDr6J jf6r9YmrP+dBA== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 01/15] arm64: dts: mediatek: mt7986: introduce ethernet nodes Date: Mon, 16 May 2022 18:06:28 +0200 Message-Id: <2d74a009757a558a26f74d7c9c8070af57926be5.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce ethernet nodes in mt7986 bindings in order to enable mt7986a/mt7986b ethernet support. Co-developed-by: Sam Shih Signed-off-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 74 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 39 +++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 70 ++++++++++++++++++ 3 files changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 21e420829572..882277a52b69 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -25,6 +25,80 @@ memory@40000000 { }; }; +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 694acf8f5b70..d2636a0ed152 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -222,6 +222,45 @@ ethsys: syscon@15000000 { #reset-cells = <1>; }; + eth: ethernet@15100000 { + compatible = "mediatek,mt7986-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGMII0_TX250M_EN>, + <&sgmiisys0 CLK_SGMII0_RX250M_EN>, + <&sgmiisys0 CLK_SGMII0_CDR_REF>, + <&sgmiisys0 CLK_SGMII0_CDR_FB>, + <&sgmiisys1 CLK_SGMII1_TX250M_EN>, + <&sgmiisys1 CLK_SGMII1_RX250M_EN>, + <&sgmiisys1 CLK_SGMII1_CDR_REF>, + <&sgmiisys1 CLK_SGMII1_CDR_FB>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index d73467ea3641..0f49d5764ff3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -28,3 +28,73 @@ memory@40000000 { &uart0 { status = "okay"; }; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; From patchwork Mon May 16 16:06:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 573076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8077C433EF for ; Mon, 16 May 2022 16:07:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245638AbiEPQHz (ORCPT ); Mon, 16 May 2022 12:07:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245260AbiEPQHx (ORCPT ); Mon, 16 May 2022 12:07:53 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CC1037A90; Mon, 16 May 2022 09:07:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id BF6BECE16E4; Mon, 16 May 2022 16:07:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5873EC34113; Mon, 16 May 2022 16:07:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717269; bh=zo+PQVFuA+GxPo/d6/CtXgd7jFrLzi0gI150KZBcaLA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FUjrw4Hx8KjxReUXnNdcEyzFAfRLwM59ktxCL724Q6Pm3d6WPZ3pf/ceINM+NVUym NkAXEX+CuiKec6gxClNPld9HxIl+hVX7yXCMQtIdWNBOF10JILmFlgiRkSEp1TYakl 6iF+t3ZsmUKV7gHY9n+EZ86FlzAJHRxtbyBcyvrKoP3eUGoNWLSmJ6QE81HU9D4nj/ tJ9FvyTZqmToUwswqYKPVDA55AiAIYxLs+VQ7S1/VLJpofPjNz5U7EuFmp9jku3Gsv QH4bOKRRpIet5686a8sREg9FN6S1dAobGXDL26vDVZ6/Q1itCu2cAL37Nq024YqlSs BxgvNDcuALvJg== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 03/15] net: ethernet: mtk_eth_soc: move tx dma desc configuration in mtk_tx_set_dma_desc Date: Mon, 16 May 2022 18:06:30 +0200 Message-Id: <56f87927844502969dd6929e9137c47e54c99c00.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move tx dma descriptor configuration in mtk_tx_set_dma_desc routine. This is a preliminary patch to introduce mt7986 ethernet support since it relies on a different tx dma descriptor layout. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 105 +++++++++++--------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++ 2 files changed, 67 insertions(+), 49 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 31c5da5d6b72..085c740779de 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -918,18 +918,51 @@ static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, } } +static void mtk_tx_set_dma_desc(struct net_device *dev, struct mtk_tx_dma *desc, + struct mtk_tx_dma_desc_info *info) +{ + struct mtk_mac *mac = netdev_priv(dev); + u32 data; + + WRITE_ONCE(desc->txd1, info->addr); + + data = TX_DMA_SWC | TX_DMA_PLEN0(info->size); + if (info->last) + data |= TX_DMA_LS0; + WRITE_ONCE(desc->txd3, data); + + data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ + if (info->first) { + if (info->gso) + data |= TX_DMA_TSO; + /* tx checksum offload */ + if (info->csum) + data |= TX_DMA_CHKSUM; + /* vlan header offload */ + if (info->vlan) + data |= TX_DMA_INS_VLAN | info->vlan_tci; + } + WRITE_ONCE(desc->txd4, data); +} + static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, int tx_num, struct mtk_tx_ring *ring, bool gso) { + struct mtk_tx_dma_desc_info txd_info = { + .size = skb_headlen(skb), + .gso = gso, + .csum = skb->ip_summed == CHECKSUM_PARTIAL, + .vlan = skb_vlan_tag_present(skb), + .vlan_tci = skb_vlan_tag_get(skb), + .first = true, + .last = !skb_is_nonlinear(skb), + }; struct mtk_mac *mac = netdev_priv(dev); struct mtk_eth *eth = mac->hw; struct mtk_tx_dma *itxd, *txd; struct mtk_tx_dma *itxd_pdma, *txd_pdma; struct mtk_tx_buf *itx_buf, *tx_buf; - dma_addr_t mapped_addr; - unsigned int nr_frags; int i, n_desc = 1; - u32 txd4 = 0, fport; int k = 0; itxd = ring->next_free; @@ -937,49 +970,32 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, if (itxd == ring->last_free) return -ENOMEM; - /* set the forward port */ - fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; - txd4 |= fport; - itx_buf = mtk_desc_to_tx_buf(ring, itxd); memset(itx_buf, 0, sizeof(*itx_buf)); - if (gso) - txd4 |= TX_DMA_TSO; - - /* TX Checksum offload */ - if (skb->ip_summed == CHECKSUM_PARTIAL) - txd4 |= TX_DMA_CHKSUM; - - /* VLAN header offload */ - if (skb_vlan_tag_present(skb)) - txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); - - mapped_addr = dma_map_single(eth->dma_dev, skb->data, - skb_headlen(skb), DMA_TO_DEVICE); - if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr))) + txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, + DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) return -ENOMEM; - WRITE_ONCE(itxd->txd1, mapped_addr); + mtk_tx_set_dma_desc(dev, itxd, &txd_info); + itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; - setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), + setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, k++); /* TX SG offload */ txd = itxd; txd_pdma = qdma_to_pdma(ring, txd); - nr_frags = skb_shinfo(skb)->nr_frags; - for (i = 0; i < nr_frags; i++) { + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; unsigned int offset = 0; int frag_size = skb_frag_size(frag); while (frag_size) { - bool last_frag = false; - unsigned int frag_map_size; bool new_desc = true; if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || @@ -994,23 +1010,17 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, new_desc = false; } - - frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); - mapped_addr = skb_frag_dma_map(eth->dma_dev, frag, offset, - frag_map_size, - DMA_TO_DEVICE); - if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr))) + memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); + txd_info.size = min(frag_size, MTK_TX_DMA_BUF_LEN); + txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && + !(frag_size - txd_info.size); + txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, + offset, txd_info.size, + DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) goto err_dma; - if (i == nr_frags - 1 && - (frag_size - frag_map_size) == 0) - last_frag = true; - - WRITE_ONCE(txd->txd1, mapped_addr); - WRITE_ONCE(txd->txd3, (TX_DMA_SWC | - TX_DMA_PLEN0(frag_map_size) | - last_frag * TX_DMA_LS0)); - WRITE_ONCE(txd->txd4, fport); + mtk_tx_set_dma_desc(dev, txd, &txd_info); tx_buf = mtk_desc_to_tx_buf(ring, txd); if (new_desc) @@ -1020,20 +1030,17 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; - setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, - frag_map_size, k++); + setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, + txd_info.size, k++); - frag_size -= frag_map_size; - offset += frag_map_size; + frag_size -= txd_info.size; + offset += txd_info.size; } } /* store skb to cleanup */ itx_buf->skb = skb; - WRITE_ONCE(itxd->txd4, txd4); - WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | - (!nr_frags * TX_DMA_LS0))); if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { if (k & 0x1) txd_pdma->txd2 |= TX_DMA_LS0; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index b04977fa84f6..5d940315c7ba 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -844,6 +844,17 @@ enum mkt_eth_capabilities { MTK_MUX_U3_GMAC2_TO_QPHY | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) +struct mtk_tx_dma_desc_info { + dma_addr_t addr; + u32 size; + u16 vlan_tci; + u8 gso:1; + u8 csum:1; + u8 vlan:1; + u8 first:1; + u8 last:1; +}; + /* struct mtk_eth_data - This is the structure holding all differences * among various plaforms * @ana_rgc3: The offset for register ANA_RGC3 related to From patchwork Mon May 16 16:06:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 573075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E421DC433EF for ; Mon, 16 May 2022 16:08:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245577AbiEPQIK (ORCPT ); Mon, 16 May 2022 12:08:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245658AbiEPQIA (ORCPT ); Mon, 16 May 2022 12:08:00 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5D9C37BE3; Mon, 16 May 2022 09:07:58 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0433DB8125F; Mon, 16 May 2022 16:07:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0FF0C34115; Mon, 16 May 2022 16:07:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717275; bh=La4DfYogy1OZ7h+SajH4VcUJwX9hHdoQB3uCgc5dP00=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l3ZL7vmOBzmBvQok17XKRQckajdm7HayZ0KgyJslXuOC+vSVu0jBoRzaHaMooI6yv rEILzktFKPcwCnBINIFSy843I+aovwMcGAmlCjMIB3hdHiRccgznayaPo1albC2GOr R5G1sa6WfUlHEIuCvY3XFXqIpwHB4jDM9oVB0uWN8iqJA8rxV4cvgMR9AnkKaWUW86 TSDKTru+AkcvAIy5ZkuNbrVoAzzDB+YaVjJn+WASqQR9VaUEgXOZfm+urA4Xtr8goV zeSApdVACOqJr35j3xsnICxVlK8KY9ypT5Qh5lyJSnuRWa6/QMXspzkMnCMD5p/Web AbyFgSY1rn+Zw== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 05/15] net: ethernet: mtk_eth_soc: rely on txd_size in mtk_tx_alloc/mtk_tx_clean Date: Mon, 16 May 2022 18:06:32 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 39 ++++++++++++--------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index cde66463bf98..a48e93792db1 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1568,25 +1568,30 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget) static int mtk_tx_alloc(struct mtk_eth *eth) { + const struct mtk_soc_data *soc = eth->soc; struct mtk_tx_ring *ring = ð->tx_ring; - int i, sz = sizeof(*ring->dma); + struct mtk_tx_dma *txd; + int i; ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), GFP_KERNEL); if (!ring->buf) goto no_tx_mem; - ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, + ring->dma = dma_alloc_coherent(eth->dma_dev, + MTK_DMA_SIZE * soc->txrx.txd_size, &ring->phys, GFP_ATOMIC); if (!ring->dma) goto no_tx_mem; for (i = 0; i < MTK_DMA_SIZE; i++) { int next = (i + 1) % MTK_DMA_SIZE; - u32 next_ptr = ring->phys + next * sz; + u32 next_ptr = ring->phys + next * soc->txrx.txd_size; - ring->dma[i].txd2 = next_ptr; - ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; + txd = (void *)ring->dma + i * soc->txrx.txd_size; + txd->txd2 = next_ptr; + txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; + txd->txd4 = 0; } /* On MT7688 (PDMA only) this driver uses the ring->dma structs @@ -1594,9 +1599,9 @@ static int mtk_tx_alloc(struct mtk_eth *eth) * descriptors in ring->dma_pdma. */ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { - ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, - &ring->phys_pdma, - GFP_ATOMIC); + ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, + MTK_DMA_SIZE * soc->txrx.txd_size, + &ring->phys_pdma, GFP_ATOMIC); if (!ring->dma_pdma) goto no_tx_mem; @@ -1609,8 +1614,9 @@ static int mtk_tx_alloc(struct mtk_eth *eth) ring->dma_size = MTK_DMA_SIZE; atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); ring->next_free = &ring->dma[0]; - ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; - ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); + ring->last_free = (void *)txd; + ring->last_free_ptr = (u32)(ring->phys + + (MTK_DMA_SIZE - 1) * soc->txrx.txd_size); ring->thresh = MAX_SKB_FRAGS; /* make sure that all changes to the dma ring are flushed before we @@ -1622,7 +1628,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); mtk_w32(eth, - ring->phys + ((MTK_DMA_SIZE - 1) * sz), + ring->phys + (MTK_DMA_SIZE - 1) * soc->txrx.txd_size, MTK_QTX_CRX_PTR); mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, @@ -1642,6 +1648,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) static void mtk_tx_clean(struct mtk_eth *eth) { + const struct mtk_soc_data *soc = eth->soc; struct mtk_tx_ring *ring = ð->tx_ring; int i; @@ -1654,17 +1661,15 @@ static void mtk_tx_clean(struct mtk_eth *eth) if (ring->dma) { dma_free_coherent(eth->dma_dev, - MTK_DMA_SIZE * sizeof(*ring->dma), - ring->dma, - ring->phys); + MTK_DMA_SIZE * soc->txrx.txd_size, + ring->dma, ring->phys); ring->dma = NULL; } if (ring->dma_pdma) { dma_free_coherent(eth->dma_dev, - MTK_DMA_SIZE * sizeof(*ring->dma_pdma), - ring->dma_pdma, - ring->phys_pdma); + MTK_DMA_SIZE * soc->txrx.txd_size, + ring->dma_pdma, ring->phys_pdma); ring->dma_pdma = NULL; } } From patchwork Mon May 16 16:06:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 573074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A67CAC433EF for ; Mon, 16 May 2022 16:08:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245656AbiEPQIa (ORCPT ); Mon, 16 May 2022 12:08:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242263AbiEPQIQ (ORCPT ); Mon, 16 May 2022 12:08:16 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29005381A8; Mon, 16 May 2022 09:08:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id D524ACE16D3; Mon, 16 May 2022 16:08:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73D72C34116; Mon, 16 May 2022 16:07:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717282; bh=/7JibGmqxINAAC2OLNWW7h4NBtLSDt9RP8nVknEhicc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kfXRNgO2WskOdTn3GnqwOmDwAZhkdOQoiCrQZqwaN2h9LiIGhhMZ6BqKT0ii2/URU tk+NvpBbRlOFdOzQPLYnYxfiWpHa95JIHohZxJCSIW6j368UO5K+fN7G39PZhB386A es2tUU3jSnVmX5INwWrS9lGle8J/FH/RTLRB2qq8rZgD9QC2qxbghjoERXxRK2UqOt Z4QQsRDMoW6qaRv5jdMx65i4GUBMvk4yejBDztaqSAwMVF3WW/WkeleQRRC/56TwvK Q1/JtwGAHl9HwHGwHTCmjmYnEghnvoP+/WArW2wIqRrrd15J6MuAoqUUe4WIqz8Xnv pzaK0cD66eglw== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 07/15] net: ethernet: mtk_eth_soc: rely on txd_size in txd_to_idx Date: Mon, 16 May 2022 18:06:34 +0200 Message-Id: <4e672c71564e1071ff1c94691984173ae9b0b54d.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 5f0082f92cc7..a67b22dbaac7 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -852,9 +852,10 @@ static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, return ring->dma_pdma - ring->dma + dma; } -static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) +static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma, + u32 txd_size) { - return ((void *)dma - (void *)ring->dma) / sizeof(*dma); + return ((void *)dma - (void *)ring->dma) / txd_size; } static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, @@ -1070,8 +1071,10 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, !netdev_xmit_more()) mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); } else { - int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), - ring->dma_size); + int next_idx; + + next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), + ring->dma_size); mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); } From patchwork Mon May 16 16:06:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 573073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92793C433EF for ; Mon, 16 May 2022 16:08:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245736AbiEPQIk (ORCPT ); Mon, 16 May 2022 12:08:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245695AbiEPQIR (ORCPT ); Mon, 16 May 2022 12:08:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D571637BE3; Mon, 16 May 2022 09:08:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 71BBF60FF0; Mon, 16 May 2022 16:08:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08663C36AE3; Mon, 16 May 2022 16:08:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717288; bh=t9Pe6TXTNALE+q/ldJlquf7ThnvPV79cToZ2NboGpxs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X0D/+6G8mP/AWzIsQLvSuw0LSpd18Bv0OLjcNWim29BH7jtv1nZGuB3jv5F8SHuFX crOzUQyqTCOVNLcPDsUePdv2wV4QCFoVrnMV4Qtg1Mdj0/JxQU0paIHbmFDUWJ/1c/ cqUy/pvwTP/q1vLydTH4y+dqiWVogccDDblqvdr4O+k4swkQA0O+2R5KojnVg94fHA HXYJw1Y3cV24YPFkpVk+2Co8XDW1Zt9OMEwsMFDPLqmTYGG+NOYE3BNARTyoY2LC+Z fNIN3UkmKkDGGLzFGGCPYH0TOsuP2W38+Zi8Db6Eu4mlkPZNSroEbxTrepfvCwsxuU 76IiZ90ujIIQQ== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 09/15] net: ethernet: mtk_eth_soc: rely on txd_size field in mtk_poll_tx/mtk_poll_rx Date: Mon, 16 May 2022 18:06:36 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is a preliminary to ad mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index bb628b65a9e5..d431311578e8 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1211,9 +1211,12 @@ static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) return ð->rx_ring[0]; for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { + struct mtk_rx_dma *rxd; + ring = ð->rx_ring[i]; idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); - if (ring->dma[idx].rxd2 & RX_DMA_DONE) { + rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; + if (rxd->rxd2 & RX_DMA_DONE) { ring->calc_idx_update = true; return ring; } @@ -1264,7 +1267,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, goto rx_done; idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); - rxd = &ring->dma[idx]; + rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; data = ring->data[idx]; if (!mtk_rx_get_desc(&trxd, rxd)) @@ -1453,7 +1456,7 @@ static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, mtk_tx_unmap(eth, tx_buf, true); - desc = &ring->dma[cpu]; + desc = (void *)ring->dma + cpu * eth->soc->txrx.txd_size; ring->last_free = desc; atomic_inc(&ring->free_count); From patchwork Mon May 16 16:06:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 573072 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FFC0C433EF for ; Mon, 16 May 2022 16:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245695AbiEPQIm (ORCPT ); Mon, 16 May 2022 12:08:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245713AbiEPQIY (ORCPT ); Mon, 16 May 2022 12:08:24 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28DEB37BED; Mon, 16 May 2022 09:08:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 9EBE3B8125A; Mon, 16 May 2022 16:08:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94B7AC34115; Mon, 16 May 2022 16:08:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717295; bh=iMrlZwNouCsE2/lev2Gal4DO5Wl2oRqF5YpiHwwXe6A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RFSyEEAPCprMk7bpOFnhRl8HuZ466OOyjQ/mkFkNVGxg9dHN46si0Lx9GK36Qlct2 1+Zu18+xg9VjHGyRLnfdEEdWN58I4HKxkTith3r1DnEG/G3ki3+/Xyhsv8ycF6LBZh U96W65JRKAdgkvSRgFb5VgYa9KMspIjwtgbuuriUtmPGrF8Iyp9yW/ihUEexugNEA+ zuOZDt9DdE0GRaoeMTrB37ehVlJWyQgnX38Cm+JBIc6qYWd+jfXa1/q+Enn7BFgEne qhDIFWuGmBjMm6zBBodFU7jrObhKdWNhxvFzjxYRpChHiIoDSqV0nwfbMeG5YSkMrq ZrTflFc7FcXAw== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 11/15] net: ethernet: mtk_eth_soc: introduce device register map Date: Mon, 16 May 2022 18:06:38 +0200 Message-Id: <78e8c6ed230130b75aae77e6d05a9b35e298860a.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce reg_map structure to add the capability to support different register definitions. This is a preliminary patch to introduce mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 17 +++ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 160 +++++++++++++------- 2 files changed, 121 insertions(+), 56 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 1e2fddc2bdcb..4dfd43023d80 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -34,6 +34,17 @@ MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); #define MTK_ETHTOOL_STAT(x) { #x, \ offsetof(struct mtk_hw_stats, x) / sizeof(u64) } +static const u32 mtk_reg_map[] = { + [MTK_PDMA_BASE] = 0x0800, + [MTK_PDMA_LRO_CTRL] = 0x0980, + [MTK_PDMA_ALT_SCORE_DELTA_BASE] = 0x0a4c, + [MTK_PDMA_LRO_RX_RING_DIP_BASE] = 0x0b04, + [MTK_PDMA_LRO_RX_RING_CTRL_BASE] = 0x0b28, + [MTK_QDMA_BASE] = 0x1800, + [MTK_GDM1_TX_STAT_BASE] = 0x2400, + [MTK_PDMA_RSS_GLO_BASE] = 0x3000, +}; + /* strings used by ethtool */ static const struct mtk_ethtool_stats { char str[ETH_GSTRING_LEN]; @@ -3376,6 +3387,7 @@ static int mtk_remove(struct platform_device *pdev) } static const struct mtk_soc_data mt2701_data = { + .reg_map = mtk_reg_map, .caps = MT7623_CAPS | MTK_HWLRO, .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, @@ -3387,6 +3399,7 @@ static const struct mtk_soc_data mt2701_data = { }; static const struct mtk_soc_data mt7621_data = { + .reg_map = mtk_reg_map, .caps = MT7621_CAPS, .hw_features = MTK_HW_FEATURES, .required_clks = MT7621_CLKS_BITMAP, @@ -3399,6 +3412,7 @@ static const struct mtk_soc_data mt7621_data = { }; static const struct mtk_soc_data mt7622_data = { + .reg_map = mtk_reg_map, .ana_rgc3 = 0x2028, .caps = MT7622_CAPS | MTK_HWLRO, .hw_features = MTK_HW_FEATURES, @@ -3412,6 +3426,7 @@ static const struct mtk_soc_data mt7622_data = { }; static const struct mtk_soc_data mt7623_data = { + .reg_map = mtk_reg_map, .caps = MT7623_CAPS | MTK_HWLRO, .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, @@ -3424,6 +3439,7 @@ static const struct mtk_soc_data mt7623_data = { }; static const struct mtk_soc_data mt7629_data = { + .reg_map = mtk_reg_map, .ana_rgc3 = 0x128, .caps = MT7629_CAPS | MTK_HWLRO, .hw_features = MTK_HW_FEATURES, @@ -3436,6 +3452,7 @@ static const struct mtk_soc_data mt7629_data = { }; static const struct mtk_soc_data rt5350_data = { + .reg_map = mtk_reg_map, .caps = MT7628_CAPS, .hw_features = MTK_HW_FEATURES_MT7628, .required_clks = MT7628_CLKS_BITMAP, diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 150d692633fa..2b98f0812655 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -19,6 +19,18 @@ #include #include "mtk_ppe.h" +enum mtk_reg_base { + MTK_PDMA_BASE, + MTK_PDMA_LRO_CTRL, + MTK_PDMA_ALT_SCORE_DELTA_BASE, + MTK_PDMA_LRO_RX_RING_DIP_BASE, + MTK_PDMA_LRO_RX_RING_CTRL_BASE, + MTK_PDMA_RSS_GLO_BASE, + MTK_GDM1_TX_STAT_BASE, + MTK_QDMA_BASE, + __MT_BASE_MAX, +}; + #define MTK_QDMA_PAGE_SIZE 2048 #define MTK_MAX_RX_LENGTH 1536 #define MTK_MAX_RX_LENGTH_2K 2048 @@ -100,43 +112,67 @@ #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) /* PDMA RX Base Pointer Register */ -#define MTK_PRX_BASE_PTR0 0x900 +#define MTK_PRX_BASE_PTR0 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x100) #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) /* PDMA RX Maximum Count Register */ -#define MTK_PRX_MAX_CNT0 0x904 +#define MTK_PRX_MAX_CNT0 (MTK_PRX_BASE_PTR0 + 0x04) #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) /* PDMA RX CPU Pointer Register */ -#define MTK_PRX_CRX_IDX0 0x908 +#define MTK_PRX_CRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x08) #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) +/* PDMA RX DMA Pointer Register */ +#define MTK_PRX_DRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x0c) +#define MTK_PRX_DRX_IDX_CFG(x) (MTK_PRX_DRX_IDX0 + (x * 0x10)) + /* PDMA HW LRO Control Registers */ -#define MTK_PDMA_LRO_CTRL_DW0 0x980 +#define MTK_PDMA_LRO_CTRL_DW0 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL]) #define MTK_LRO_EN BIT(0) #define MTK_L3_CKS_UPD_EN BIT(7) #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) -#define MTK_PDMA_LRO_CTRL_DW1 0x984 -#define MTK_PDMA_LRO_CTRL_DW2 0x988 -#define MTK_PDMA_LRO_CTRL_DW3 0x98c +#define MTK_PDMA_LRO_CTRL_DW1 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x04) +#define MTK_PDMA_LRO_CTRL_DW2 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x08) +#define MTK_PDMA_LRO_CTRL_DW3 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x0c) #define MTK_ADMA_MODE BIT(15) #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) +/* PDMA RSS Control Registers */ +#define MTK_RSS_EN BIT(0) +#define MTK_RSS_CFG_REQ BIT(2) +#define MTK_RSS_IPV6_STATIC_HASH (0x7 << 8) +#define MTK_RSS_IPV4_STATIC_HASH (0x7 << 12) +#define MTK_RSS_INDR_TABLE_DW0 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x50) +#define MTK_RSS_INDR_TABLE_DW1 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x54) +#define MTK_RSS_INDR_TABLE_DW2 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x58) +#define MTK_RSS_INDR_TABLE_DW3 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x5c) +#define MTK_RSS_INDR_TABLE_DW4 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x60) +#define MTK_RSS_INDR_TABLE_DW5 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x64) +#define MTK_RSS_INDR_TABLE_DW6 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x68) +#define MTK_RSS_INDR_TABLE_DW7 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x6c) +#define MTK_RSS_INDR_TABLE_SIZE4 0x44444444 + /* PDMA Global Configuration Register */ -#define MTK_PDMA_GLO_CFG 0xa04 +#define MTK_PDMA_GLO_CFG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x204) #define MTK_MULTI_EN BIT(10) #define MTK_PDMA_SIZE_8DWORDS (1 << 4) +/* PDMA Global Configuration Register */ +#define MTK_PDMA_RX_CFG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x210) +#define MTK_PDMA_LRO_SDL 0x3000 +#define MTK_RX_CFG_SDL_OFFSET 16 + /* PDMA Reset Index Register */ -#define MTK_PDMA_RST_IDX 0xa08 +#define MTK_PDMA_RST_IDX (eth->soc->reg_map[MTK_PDMA_BASE] + 0x208) #define MTK_PST_DRX_IDX0 BIT(16) #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) /* PDMA Delay Interrupt Register */ -#define MTK_PDMA_DELAY_INT 0xa0c +#define MTK_PDMA_DELAY_INT (eth->soc->reg_map[MTK_PDMA_BASE] + 0x20c) #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) #define MTK_PDMA_DELAY_RX_EN BIT(15) #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 @@ -151,27 +187,34 @@ #define MTK_PDMA_DELAY_PTIME_MASK 0xff /* PDMA Interrupt Status Register */ -#define MTK_PDMA_INT_STATUS 0xa20 +#define MTK_PDMA_INT_STATUS (eth->soc->reg_map[MTK_PDMA_BASE] + 0x220) /* PDMA Interrupt Mask Register */ -#define MTK_PDMA_INT_MASK 0xa28 +#define MTK_PDMA_INT_MASK (eth->soc->reg_map[MTK_PDMA_BASE] + 0x228) /* PDMA HW LRO Alter Flow Delta Register */ -#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c +#define MTK_PDMA_LRO_ALT_SCORE_DELTA (eth->soc->reg_map[MTK_PDMA_ALT_SCORE_DELTA_BASE]) /* PDMA Interrupt grouping registers */ -#define MTK_PDMA_INT_GRP1 0xa50 -#define MTK_PDMA_INT_GRP2 0xa54 +#define MTK_PDMA_INT_GRP1 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x250) +#define MTK_PDMA_INT_GRP2 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x254) /* PDMA HW LRO IP Setting Registers */ -#define MTK_LRO_RX_RING0_DIP_DW0 0xb04 +#define MTK_LRO_RX_RING0_DIP_DW0 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_DIP_BASE]) #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) #define MTK_RING_MYIP_VLD BIT(9) +/* PDMA HW LRO ALT Debug Registers */ +#define MTK_LRO_ALT_DBG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x440) +#define MTK_LRO_ALT_INDEX_OFFSET (8) + +/* PDMA HW LRO ALT Data Registers */ +#define MTK_LRO_ALT_DBG_DATA (eth->soc->reg_map[MTK_PDMA_BASE] + 0x444) + /* PDMA HW LRO Ring Control Registers */ -#define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 -#define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c -#define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 +#define MTK_LRO_RX_RING0_CTRL_DW1 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE]) +#define MTK_LRO_RX_RING0_CTRL_DW2 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE] + 0x4) +#define MTK_LRO_RX_RING0_CTRL_DW3 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE] + 0x8) #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) @@ -184,26 +227,29 @@ #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) /* QDMA TX Queue Configuration Registers */ -#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) +#define MTK_QTX_CFG(x) (eth->soc->reg_map[MTK_QDMA_BASE] + ((x) * 0x10)) #define QDMA_RES_THRES 4 /* QDMA TX Queue Scheduler Registers */ -#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) +#define MTK_QTX_SCH(x) (eth->soc->reg_map[MTK_QDMA_BASE] + 4 + ((x) * 0x10)) /* QDMA RX Base Pointer Register */ -#define MTK_QRX_BASE_PTR0 0x1900 +#define MTK_QRX_BASE_PTR0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x100) +#define MTK_QRX_BASE_PTR_CFG(x) (MTK_QRX_BASE_PTR0 + ((x) * 0x10)) /* QDMA RX Maximum Count Register */ -#define MTK_QRX_MAX_CNT0 0x1904 +#define MTK_QRX_MAX_CNT0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x104) +#define MTK_QRX_MAX_CNT_CFG(x) (MTK_QRX_MAX_CNT0 + ((x) * 0x10)) /* QDMA RX CPU Pointer Register */ -#define MTK_QRX_CRX_IDX0 0x1908 +#define MTK_QRX_CRX_IDX0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x108) +#define MTK_QRX_CRX_IDX_CFG(x) (MTK_QRX_CRX_IDX0 + ((x) * 0x10)) /* QDMA RX DMA Pointer Register */ -#define MTK_QRX_DRX_IDX0 0x190C +#define MTK_QRX_DRX_IDX0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x10c) /* QDMA Global Configuration Register */ -#define MTK_QDMA_GLO_CFG 0x1A04 +#define MTK_QDMA_GLO_CFG (eth->soc->reg_map[MTK_QDMA_BASE] + 0x204) #define MTK_RX_2B_OFFSET BIT(31) #define MTK_RX_BT_32DWORDS (3 << 11) #define MTK_NDP_CO_PRO BIT(10) @@ -216,19 +262,19 @@ #define MTK_DMA_BUSY_TIMEOUT_US 1000000 /* QDMA Reset Index Register */ -#define MTK_QDMA_RST_IDX 0x1A08 +#define MTK_QDMA_RST_IDX (eth->soc->reg_map[MTK_QDMA_BASE] + 0x208) /* QDMA Delay Interrupt Register */ -#define MTK_QDMA_DELAY_INT 0x1A0C +#define MTK_QDMA_DELAY_INT (eth->soc->reg_map[MTK_QDMA_BASE] + 0x20c) /* QDMA Flow Control Register */ -#define MTK_QDMA_FC_THRES 0x1A10 +#define MTK_QDMA_FC_THRES (eth->soc->reg_map[MTK_QDMA_BASE] + 0x210) #define FC_THRES_DROP_MODE BIT(20) #define FC_THRES_DROP_EN (7 << 16) #define FC_THRES_MIN 0x4444 /* QDMA Interrupt Status Register */ -#define MTK_QDMA_INT_STATUS 0x1A18 +#define MTK_QDMA_INT_STATUS (eth->soc->reg_map[MTK_QDMA_BASE] + 0x218) #define MTK_RX_DONE_DLY BIT(30) #define MTK_TX_DONE_DLY BIT(28) #define MTK_RX_DONE_INT3 BIT(19) @@ -243,55 +289,55 @@ #define MTK_TX_DONE_INT MTK_TX_DONE_DLY /* QDMA Interrupt grouping registers */ -#define MTK_QDMA_INT_GRP1 0x1a20 -#define MTK_QDMA_INT_GRP2 0x1a24 +#define MTK_QDMA_INT_GRP1 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x220) +#define MTK_QDMA_INT_GRP2 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x224) #define MTK_RLS_DONE_INT BIT(0) /* QDMA Interrupt Status Register */ -#define MTK_QDMA_INT_MASK 0x1A1C +#define MTK_QDMA_INT_MASK (eth->soc->reg_map[MTK_QDMA_BASE] + 0x21c) /* QDMA Interrupt Mask Register */ -#define MTK_QDMA_HRED2 0x1A44 +#define MTK_QDMA_HRED2 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x244) /* QDMA TX Forward CPU Pointer Register */ -#define MTK_QTX_CTX_PTR 0x1B00 +#define MTK_QTX_CTX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x300) /* QDMA TX Forward DMA Pointer Register */ -#define MTK_QTX_DTX_PTR 0x1B04 +#define MTK_QTX_DTX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x304) /* QDMA TX Release CPU Pointer Register */ -#define MTK_QTX_CRX_PTR 0x1B10 +#define MTK_QTX_CRX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x310) /* QDMA TX Release DMA Pointer Register */ -#define MTK_QTX_DRX_PTR 0x1B14 +#define MTK_QTX_DRX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x314) /* QDMA FQ Head Pointer Register */ -#define MTK_QDMA_FQ_HEAD 0x1B20 +#define MTK_QDMA_FQ_HEAD (eth->soc->reg_map[MTK_QDMA_BASE] + 0x320) /* QDMA FQ Head Pointer Register */ -#define MTK_QDMA_FQ_TAIL 0x1B24 +#define MTK_QDMA_FQ_TAIL (eth->soc->reg_map[MTK_QDMA_BASE] + 0x324) /* QDMA FQ Free Page Counter Register */ -#define MTK_QDMA_FQ_CNT 0x1B28 +#define MTK_QDMA_FQ_CNT (eth->soc->reg_map[MTK_QDMA_BASE] + 0x328) /* QDMA FQ Free Page Buffer Length Register */ -#define MTK_QDMA_FQ_BLEN 0x1B2C +#define MTK_QDMA_FQ_BLEN (eth->soc->reg_map[MTK_QDMA_BASE] + 0x32c) /* GMA1 counter / statics register */ -#define MTK_GDM1_RX_GBCNT_L 0x2400 -#define MTK_GDM1_RX_GBCNT_H 0x2404 -#define MTK_GDM1_RX_GPCNT 0x2408 -#define MTK_GDM1_RX_OERCNT 0x2410 -#define MTK_GDM1_RX_FERCNT 0x2414 -#define MTK_GDM1_RX_SERCNT 0x2418 -#define MTK_GDM1_RX_LENCNT 0x241c -#define MTK_GDM1_RX_CERCNT 0x2420 -#define MTK_GDM1_RX_FCCNT 0x2424 -#define MTK_GDM1_TX_SKIPCNT 0x2428 -#define MTK_GDM1_TX_COLCNT 0x242c -#define MTK_GDM1_TX_GBCNT_L 0x2430 -#define MTK_GDM1_TX_GBCNT_H 0x2434 -#define MTK_GDM1_TX_GPCNT 0x2438 +#define MTK_GDM1_RX_GBCNT_L (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE]) +#define MTK_GDM1_RX_GBCNT_H (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x4) +#define MTK_GDM1_RX_GPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x8) +#define MTK_GDM1_RX_OERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x10) +#define MTK_GDM1_RX_FERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x14) +#define MTK_GDM1_RX_SERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x18) +#define MTK_GDM1_RX_LENCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x1c) +#define MTK_GDM1_RX_CERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x20) +#define MTK_GDM1_RX_FCCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x24) +#define MTK_GDM1_TX_SKIPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x28) +#define MTK_GDM1_TX_COLCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x2c) +#define MTK_GDM1_TX_GBCNT_L (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x30) +#define MTK_GDM1_TX_GBCNT_H (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x34) +#define MTK_GDM1_TX_GPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x38) #define MTK_STAT_OFFSET 0x40 #define MTK_WDMA0_BASE 0x2800 @@ -857,6 +903,7 @@ struct mtk_tx_dma_desc_info { /* struct mtk_eth_data - This is the structure holding all differences * among various plaforms + * @reg_map: Device register map * @ana_rgc3: The offset for register ANA_RGC3 related to * sgmiisys syscon * @caps Flags shown the extra capability for the SoC @@ -869,6 +916,7 @@ struct mtk_tx_dma_desc_info { * @rxd_size RX DMA descriptor size. */ struct mtk_soc_data { + const u32 *reg_map; u32 ana_rgc3; u32 caps; u32 required_clks; From patchwork Mon May 16 16:06:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 573071 Return-Path: X-Spam-Checker-Version: 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5A46DB81261; Mon, 16 May 2022 16:08:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 579EAC34115; Mon, 16 May 2022 16:08:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717302; bh=g+8ZHx5azfc9wFAICouyVaIiKamwB274z8h8s7EKO50=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n+bT1o961RfEthuRGTK+eC1Vxkq7IDhths0YeT9ujxeKaCKEBSFwtrYiS670ZQOmm Op77K6qCb4MWCahtuv8zCfQFoXZANS8318gHlVu4kf7IFpn9/OIBhUmSz1sugTF2bw vlHERXGn6eKmAnaqStvX0Q3ObytcJe49oAUguRVFQLjk1G9u7ducTfxV0bbQQY93PD UfIYOqbpVgaMR9Bg4t4rq3Df8M0a+WS90d1Es9L6rmijfe8AM1A43c1vHoMb/rPJNj dPwBmS+c/2G4mj8E683OFAVQKb6lX6vIsqi3iE5nzWS7CEWvdudIqCgnk+0cHZb4ae qGH937UWTMuPg== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 13/15] net: ethernet: mtk_eth_soc: convert ring dma pointer to void Date: Mon, 16 May 2022 18:06:40 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Simplify the code converting {tx,rx} ring dma pointer to void Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 32 +++++++++------------ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 +-- 2 files changed, 16 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 50ffdcb8d35a..4190172ba902 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -851,18 +851,15 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) return 0; } -static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) +static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) { - void *ret = ring->dma; - - return ret + (desc - ring->phys); + return ring->dma + (desc - ring->phys); } static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, - struct mtk_tx_dma *txd, - u32 txd_size) + void *txd, u32 txd_size) { - int idx = ((void *)txd - (void *)ring->dma) / txd_size; + int idx = (txd - ring->dma) / txd_size; return &ring->buf[idx]; } @@ -870,13 +867,12 @@ static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) { - return ring->dma_pdma - ring->dma + dma; + return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; } -static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma, - u32 txd_size) +static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) { - return ((void *)dma - (void *)ring->dma) / txd_size; + return (dma - ring->dma) / txd_size; } static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, @@ -1293,7 +1289,7 @@ static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) ring = ð->rx_ring[i]; idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); - rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; + rxd = ring->dma + idx * eth->soc->txrx.rxd_size; if (rxd->rxd2 & RX_DMA_DONE) { ring->calc_idx_update = true; return ring; @@ -1345,7 +1341,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, goto rx_done; idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); - rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; + rxd = ring->dma + idx * eth->soc->txrx.rxd_size; data = ring->data[idx]; if (!mtk_rx_get_desc(eth, &trxd, rxd)) @@ -1548,7 +1544,7 @@ static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, mtk_tx_unmap(eth, tx_buf, true); - desc = (void *)ring->dma + cpu * eth->soc->txrx.txd_size; + desc = ring->dma + cpu * eth->soc->txrx.txd_size; ring->last_free = desc; atomic_inc(&ring->free_count); @@ -1692,7 +1688,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) int next = (i + 1) % MTK_DMA_SIZE; u32 next_ptr = ring->phys + next * soc->txrx.txd_size; - txd = (void *)ring->dma + i * soc->txrx.txd_size; + txd = ring->dma + i * soc->txrx.txd_size; txd->txd2 = next_ptr; txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; txd->txd4 = 0; @@ -1723,7 +1719,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) ring->dma_size = MTK_DMA_SIZE; atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); - ring->next_free = &ring->dma[0]; + ring->next_free = ring->dma; ring->last_free = (void *)txd; ring->last_free_ptr = (u32)(ring->phys + (MTK_DMA_SIZE - 1) * soc->txrx.txd_size); @@ -1835,7 +1831,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) return -ENOMEM; - rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size; + rxd = ring->dma + i * eth->soc->txrx.rxd_size; rxd->rxd1 = (unsigned int)dma_addr; if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) @@ -1889,7 +1885,7 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) if (!ring->data[i]) continue; - rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size; + rxd = ring->dma + i * eth->soc->txrx.rxd_size; if (!rxd->rxd1) continue; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 654ad3b00154..57501dd5adcc 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -828,7 +828,7 @@ struct mtk_tx_buf { * are present */ struct mtk_tx_ring { - struct mtk_tx_dma *dma; + void *dma; struct mtk_tx_buf *buf; dma_addr_t phys; struct mtk_tx_dma *next_free; @@ -858,7 +858,7 @@ enum mtk_rx_flags { * @calc_idx: The current head of ring */ struct mtk_rx_ring { - struct mtk_rx_dma *dma; + void *dma; u8 **data; dma_addr_t phys; u16 frag_size; From patchwork Mon May 16 16:06:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 573070 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B36CEC433EF for ; Mon, 16 May 2022 16:08:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245690AbiEPQIu (ORCPT ); Mon, 16 May 2022 12:08:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245726AbiEPQIj (ORCPT ); Mon, 16 May 2022 12:08:39 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0798F38795; Mon, 16 May 2022 09:08:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 569B460FC9; Mon, 16 May 2022 16:08:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E46D9C385AA; Mon, 16 May 2022 16:08:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717308; bh=uM3ccAJWdxDoSZRLhAr0NaFqOgPx8bqnk2xxzO/IuVI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oO4zdUWmjDwrudVQk++1yhWHpuI30+WM5WktqlkYfCcNzj6W4Oe7NHz0BdvW0fj3G jJn551vhucEYa8Mb1+qKJdXOZRDWLF00DFr12zsxVmLF/21LeCQu2lkODd2NCR6U1m pCKtSLJ6twW+Mh+wftLj2j4+dkG5OgDtDIOOQax59mamKsLkiIZ6XbKpDXcg17tPap 5oeW295IHSZztTsRxmwT/ELdvhbY0l6+iVlcnhJf4iIBzeI0PBi6gwk9kkJmxGFuqe 7YPSOx3uWQmFoyHq+Se1l6JXTElwjfRH2Fg6+s4ONwqWhPenAl0CwgygP6kLcMqLCk Rhm338CZyo8SA== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 15/15] net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset Date: Mon, 16 May 2022 18:06:42 +0200 Message-Id: <5b8e9a0256bd1da216ff508d70bd5a8b9f3113f1.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for mt7986-eth driver available on mt7986 soc. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 29 ++++++++++++++++++++- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 18 +++++++++++++ 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 373d9733e66f..ce3c242f14fa 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -45,6 +45,17 @@ static const u32 mtk_reg_map[] = { [MTK_PDMA_RSS_GLO_BASE] = 0x3000, }; +static const u32 mt7986_reg_map[] = { + [MTK_PDMA_BASE] = 0x6000, + [MTK_PDMA_LRO_CTRL] = 0x6408, + [MTK_PDMA_ALT_SCORE_DELTA_BASE] = 0x641c, + [MTK_PDMA_LRO_RX_RING_DIP_BASE] = 0x6414, + [MTK_PDMA_LRO_RX_RING_CTRL_BASE] = 0x6438, + [MTK_QDMA_BASE] = 0x4400, + [MTK_GDM1_TX_STAT_BASE] = 0x1c00, + [MTK_PDMA_RSS_GLO_BASE] = 0x6800, +}; + /* strings used by ethtool */ static const struct mtk_ethtool_stats { char str[ETH_GSTRING_LEN]; @@ -68,7 +79,7 @@ static const char * const mtk_clks_source_name[] = { "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "eth2pll", + "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" }; void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) @@ -3625,6 +3636,21 @@ static const struct mtk_soc_data mt7629_data = { }, }; +static const struct mtk_soc_data mt7986_data = { + .reg_map = mt7986_reg_map, + .ana_rgc3 = 0x128, + .caps = MT7986_CAPS, + .required_clks = MT7986_CLKS_BITMAP, + .required_pctl = false, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), + .rx_irq_done_mask = MTK_RX_DONE_INT_V2, + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, + .dma_len_offset = 8, + }, +}; + static const struct mtk_soc_data rt5350_data = { .reg_map = mtk_reg_map, .caps = MT7628_CAPS, @@ -3647,6 +3673,7 @@ const struct of_device_id of_mtk_match[] = { { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, + { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, {}, }; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index d955af42ad93..1972bc18af0c 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -763,6 +763,10 @@ enum mtk_clks_map { MTK_CLK_SGMII2_CDR_FB, MTK_CLK_SGMII_CK, MTK_CLK_ETH2PLL, + MTK_CLK_WOCPU0, + MTK_CLK_WOCPU1, + MTK_CLK_NETSYS0, + MTK_CLK_NETSYS1, MTK_CLK_MAX }; @@ -793,6 +797,16 @@ enum mtk_clks_map { BIT(MTK_CLK_SGMII2_CDR_FB) | \ BIT(MTK_CLK_SGMII_CK) | \ BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) +#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ + BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ + BIT(MTK_CLK_SGMII_TX_250M) | \ + BIT(MTK_CLK_SGMII_RX_250M) | \ + BIT(MTK_CLK_SGMII_CDR_REF) | \ + BIT(MTK_CLK_SGMII_CDR_FB) | \ + BIT(MTK_CLK_SGMII2_TX_250M) | \ + BIT(MTK_CLK_SGMII2_RX_250M) | \ + BIT(MTK_CLK_SGMII2_CDR_REF) | \ + BIT(MTK_CLK_SGMII2_CDR_FB)) enum mtk_dev_state { MTK_HW_INIT, @@ -991,6 +1005,10 @@ enum mkt_eth_capabilities { MTK_MUX_U3_GMAC2_TO_QPHY | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) +#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) + struct mtk_tx_dma_desc_info { dma_addr_t addr; u32 size;