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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:41 +0000 Message-Id: <20190107163117.16269-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 01/37] target/arm: Convert ARM_TBFLAG_* to FIELDs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use "register" TBFLAG_ANY to indicate shared state between A32 and A64, and "registers" TBFLAG_A32 & TBFLAG_A64 for fields that are specific to the given cpu state. Move ARM_TBFLAG_BE_DATA to shared state, instead of its current placement within "Bit usage when in AArch32 state". Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181218164348.7127-1-richard.henderson@linaro.org [PMM: removed the renaming of BE_DATA flag to BE] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 102 ++++++++----------------------------- target/arm/helper.c | 49 +++++++++--------- target/arm/translate-a64.c | 22 ++++---- target/arm/translate.c | 40 ++++++++------- 4 files changed, 78 insertions(+), 135 deletions(-) -- 2.19.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c943f35dd92..fba1c578d30 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2944,102 +2944,40 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. */ -#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 -#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) -#define ARM_TBFLAG_MMUIDX_SHIFT 28 -#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) -#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 -#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) -#define ARM_TBFLAG_PSTATE_SS_SHIFT 26 -#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) +FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) +FIELD(TBFLAG_ANY, MMUIDX, 28, 3) +FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Target EL if we take a floating-point-disabled exception */ -#define ARM_TBFLAG_FPEXC_EL_SHIFT 24 -#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) +FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) +FIELD(TBFLAG_ANY, BE_DATA, 23, 1) /* Bit usage when in AArch32 state: */ -#define ARM_TBFLAG_THUMB_SHIFT 0 -#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) -#define ARM_TBFLAG_VECLEN_SHIFT 1 -#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) -#define ARM_TBFLAG_VECSTRIDE_SHIFT 4 -#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) -#define ARM_TBFLAG_VFPEN_SHIFT 7 -#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) -#define ARM_TBFLAG_CONDEXEC_SHIFT 8 -#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) -#define ARM_TBFLAG_SCTLR_B_SHIFT 16 -#define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) +FIELD(TBFLAG_A32, THUMB, 0, 1) +FIELD(TBFLAG_A32, VECLEN, 1, 3) +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, VFPEN, 7, 1) +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime */ -#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 -#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) +FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) /* Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -#define ARM_TBFLAG_NS_SHIFT 19 -#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) -#define ARM_TBFLAG_BE_DATA_SHIFT 20 -#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) +FIELD(TBFLAG_A32, NS, 19, 1) /* For M profile only, Handler (ie not Thread) mode */ -#define ARM_TBFLAG_HANDLER_SHIFT 21 -#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) +FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ -#define ARM_TBFLAG_STACKCHECK_SHIFT 22 -#define ARM_TBFLAG_STACKCHECK_MASK (1 << ARM_TBFLAG_STACKCHECK_SHIFT) +FIELD(TBFLAG_A32, STACKCHECK, 22, 1) /* Bit usage when in AArch64 state */ -#define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ -#define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) -#define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ -#define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) -#define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 -#define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) -#define ARM_TBFLAG_ZCR_LEN_SHIFT 4 -#define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) - -/* some convenience accessor macros */ -#define ARM_TBFLAG_AARCH64_STATE(F) \ - (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) -#define ARM_TBFLAG_MMUIDX(F) \ - (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) -#define ARM_TBFLAG_SS_ACTIVE(F) \ - (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) -#define ARM_TBFLAG_PSTATE_SS(F) \ - (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) -#define ARM_TBFLAG_FPEXC_EL(F) \ - (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) -#define ARM_TBFLAG_THUMB(F) \ - (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) -#define ARM_TBFLAG_VECLEN(F) \ - (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) -#define ARM_TBFLAG_VECSTRIDE(F) \ - (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) -#define ARM_TBFLAG_VFPEN(F) \ - (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) -#define ARM_TBFLAG_CONDEXEC(F) \ - (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) -#define ARM_TBFLAG_SCTLR_B(F) \ - (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) -#define ARM_TBFLAG_XSCALE_CPAR(F) \ - (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) -#define ARM_TBFLAG_NS(F) \ - (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) -#define ARM_TBFLAG_BE_DATA(F) \ - (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) -#define ARM_TBFLAG_HANDLER(F) \ - (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) -#define ARM_TBFLAG_STACKCHECK(F) \ - (((F) & ARM_TBFLAG_STACKCHECK_MASK) >> ARM_TBFLAG_STACKCHECK_SHIFT) -#define ARM_TBFLAG_TBI0(F) \ - (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) -#define ARM_TBFLAG_TBI1(F) \ - (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) -#define ARM_TBFLAG_SVEEXC_EL(F) \ - (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) -#define ARM_TBFLAG_ZCR_LEN(F) \ - (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) +FIELD(TBFLAG_A64, TBI0, 0, 1) +FIELD(TBFLAG_A64, TBI1, 1, 1) +FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) +FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 644599b29d6..f00c141ef96 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12955,16 +12955,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags; + uint32_t flags = 0; if (is_a64(env)) { ARMCPU *cpu = arm_env_get_cpu(env); *pc = env->pc; - flags = ARM_TBFLAG_AARCH64_STATE_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); /* Get control bits for tagged addresses */ - flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); - flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); + flags = FIELD_DP32(flags, TBFLAG_A64, TBI0, + arm_regime_tbi0(env, mmu_idx)); + flags = FIELD_DP32(flags, TBFLAG_A64, TBI1, + arm_regime_tbi1(env, mmu_idx)); if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el = sve_exception_el(env, current_el); @@ -12978,28 +12980,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } else { zcr_len = sve_zcr_len_for_el(env, current_el); } - flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; - flags |= zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } } else { *pc = env->regs[15]; - flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) - | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) - | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) - | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) - | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); - if (!(access_secure_reg(env))) { - flags |= ARM_TBFLAG_NS_MASK; - } + flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); + flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); + flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); + flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { - flags |= ARM_TBFLAG_VFPEN_MASK; + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - flags |= (extract32(env->cp15.c15_cpar, 0, 2) - << ARM_TBFLAG_XSCALE_CPAR_SHIFT); + flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -13009,24 +13008,24 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending */ if (arm_singlestep_active(env)) { - flags |= ARM_TBFLAG_SS_ACTIVE_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); if (is_a64(env)) { if (env->pstate & PSTATE_SS) { - flags |= ARM_TBFLAG_PSTATE_SS_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } } else { if (env->uncached_cpsr & PSTATE_SS) { - flags |= ARM_TBFLAG_PSTATE_SS_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } } } if (arm_cpu_data_is_big_endian(env)) { - flags |= ARM_TBFLAG_BE_DATA_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); } - flags |= fp_el << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); if (arm_v7m_is_handler_mode(env)) { - flags |= ARM_TBFLAG_HANDLER_MASK; + flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is @@ -13036,7 +13035,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, arm_feature(env, ARM_FEATURE_M) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags |= ARM_TBFLAG_STACKCHECK_MASK; + flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); } *pflags = flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e1da1e4d6f5..b7b6ab63716 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13380,7 +13380,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; ARMCPU *arm_cpu = arm_env_get_cpu(env); - int bound; + uint32_t tb_flags = dc->base.tb->flags; + int bound, core_mmu_idx; dc->isar = &arm_cpu->isar; dc->pc = dc->base.pc_first; @@ -13394,19 +13395,20 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; - dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags)); - dc->tbi0 = ARM_TBFLAG_TBI0(dc->base.tb->flags); - dc->tbi1 = ARM_TBFLAG_TBI1(dc->base.tb->flags); + core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); + dc->tbi0 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI0); + dc->tbi1 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI1); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); - dc->sve_excp_el = ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); - dc->sve_len = (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; + dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); + dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; @@ -13427,8 +13429,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); + dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); + dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c4675ffd8a..ed3db0c3946 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13021,6 +13021,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; ARMCPU *cpu = arm_env_get_cpu(env); + uint32_t tb_flags = dc->base.tb->flags; + uint32_t condexec, core_mmu_idx; dc->isar = &cpu->isar; dc->pc = dc->base.pc_first; @@ -13032,26 +13034,28 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb = ARM_TBFLAG_THUMB(dc->base.tb->flags); - dc->sctlr_b = ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); - dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) << 1; - dc->condexec_cond = ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags)); + dc->thumb = FIELD_EX32(tb_flags, TBFLAG_A32, THUMB); + dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; + condexec = FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC); + dc->condexec_mask = (condexec & 0xf) << 1; + dc->condexec_cond = condexec >> 4; + core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->ns = ARM_TBFLAG_NS(dc->base.tb->flags); - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); - dc->vfp_enabled = ARM_TBFLAG_VFPEN(dc->base.tb->flags); - dc->vec_len = ARM_TBFLAG_VECLEN(dc->base.tb->flags); - dc->vec_stride = ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); - dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); - dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(dc->base.tb->flags); + dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS); + dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); + dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER); dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck = ARM_TBFLAG_STACKCHECK(dc->base.tb->flags); + dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); dc->cp_regs = cpu->cp_regs; dc->features = env->features; @@ -13070,8 +13074,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); + dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); + dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ @@ -13516,11 +13520,11 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) DisasContext dc; const TranslatorOps *ops = &arm_translator_ops; - if (ARM_TBFLAG_THUMB(tb->flags)) { + if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) { ops = &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + if (FIELD_EX32(tb->flags, TBFLAG_ANY, AARCH64_STATE)) { ops = &aarch64_translator_ops; } #endif From patchwork Mon Jan 7 16:30:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154902 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3667608ljp; Mon, 7 Jan 2019 08:31:53 -0800 (PST) X-Google-Smtp-Source: ALg8bN5fg29+5uFNzOo8FnpZlV2SWYwwZZ9R8ziL9Ui/U8HUpxaTkXmX5z9bE0+iKnQiKE/91HSZ X-Received: by 2002:adf:83a7:: with SMTP id 36mr52724858wre.13.1546878713842; Mon, 07 Jan 2019 08:31:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546878713; cv=none; d=google.com; s=arc-20160816; b=AxtZqCH233pkXcUCcmuudzg8RPciCgaz0r5OcY1+jzjUCPC1NMfNW7HEqID6peOSpH NQtNawbKC8FbSQdvGu8wYcqIJ9/1Y/vs5tfbiBlHj8k4ijfg7jcyJG0qb3hAuhYhqH4S iA4hdbYipj4K/bkt1PY2vCc4WYaCs3084fv+dqQa8zfns0TaaPDbhUYnvQrPPwG01rm6 9K9fHfhmozYZ5LlSH+NwoyAhTCD20h23NtXHKdPNtuwsqSHFYJPXKQxfBYh4ipPpXYU7 93c3WyiutfVYiffHEUC92Ezm3uwWwyRoTTUFEoMIep5XKFVB17HYO7NxI6YnKWCiSJWe YwMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=vDv66PJYZ8IkWxNWsE5Oc2nyeU86TpAONaK01uxo88o=; b=A1UxYB5jC8P4/U4H6WENix3Z5e8A8m/7x70x4AGB15RNA/WV4aYX2QXNoDBvZrZlUi /NfRS3514u4xdFXZcJOf/jDQOiXQEuZDpom9KEp5Le/ge7Iukcqy2CvlRj8Fg1dXqzwh aP45Cr3gXlP4R9sZBH2Qb8dv+Ia/FOUxvLMXevz6Jcot6AcQ+4yCMvekIwX08izA7CaI I0SaUG72OUTTXItt34zZ3K4YSR8CMLqNFZKf124OUe2EWbXYXfdY/lSUhNjAVLfwp1jQ BVTJ7gILUrNHv/HPlplAQWBDXeQbn6MVtKg4dmlxbev4k0qpHDGvc2ilsCE+MGLLXtJ0 Njzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="foYto4/V"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:42 +0000 Message-Id: <20190107163117.16269-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 02/37] target/arm: SVE brk[ab] merging does not have s bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson While brk[ab] zeroing has a flags setting option, the merging variant does not. Retain the same argument structure, to share expansion but force the flag zero and do not decode bit 22. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Message-id: 20181226215003.31438-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/sve.decode | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.19.2 diff --git a/target/arm/sve.decode b/target/arm/sve.decode index e10b689454e..4f580a25e70 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -99,6 +99,7 @@ # Two operand with governing predicate, flags setting @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s +@pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 # Three operand with unused vector element size @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 @@ -667,8 +668,8 @@ BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s # SVE partition break condition BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s -BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s -BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s +BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 +BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 # SVE propagate break to next partition BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s From patchwork Mon Jan 7 16:30:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154909 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3673598ljp; Mon, 7 Jan 2019 08:37:55 -0800 (PST) X-Google-Smtp-Source: ALg8bN7JzOd0ly0w2a6ujcOUhRiTU2piqDuv01THKduI/SDxKXLG3Vh/i6qVFS7gLIm4kidf9PhX X-Received: by 2002:a7b:c7c7:: with SMTP id z7mr10011428wmk.74.1546879075243; Mon, 07 Jan 2019 08:37:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879075; cv=none; d=google.com; s=arc-20160816; b=T665c6YPsyM9ij/qRc5H+6LSeAQrTxqd5AIDh5QAU/Iw8Exl/B1EZ6+aZVXJj2z7ki 90jUSERK71fFAMPJGoWrUalVSsgN4VTCnXwBeEin8ESsi6tDnUJmKtPPAuT5ufO2MUSE RCA32EmXnJ73iodzeCz9qaT4Ta1hkOA/Esog/1EOqMxO73Djnnjcjfbw2RWLHRIQJSTX PhoADlhcFKW7UVJwHMZJfFOVQ7o1j0Sn3RSnvCEB0601yewNuqcoGuDdt8rz4z+cQ9Dx Swml/CfoTjIqyHSEaO+oyMDjBHEr0ypmsJx8j0TUc1V7g7HavqcMWkCszoygre6n+JjE 01aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5VuVI331ytNyDlTx9NKnef1XgHmbGjUAdHkiXIl1t78=; b=RYh6dWAGkxHJrCIAasa8aibeLldR22h9rBsFsxZmXBGbVHv1FBK4gGBOmv0IadOZxn A3jCnTC1Z68dPHHQc9MTHk4kGQGkYMogKj5zZ3dcNEkjtwjlW4ce1QzpFo254TB5im+i 2Fx5Y50Jv0RHoqIhMJus6NpOCLL6Ir+tTw3yrN/m39qmKFgKkeEAiGScnpjWJi219lhd Gtm2wXkWqYN1tMNRzunUm/LeM3eVnSL0HhAmQEUDRPuCqahbmvSXlCy/lDBwjE0MvDJF Tdc7tjCbiXS+K0mi8OS4rmpum5ZcWrImyXsnzYI2jk7/3/UB9+2KLYDMtXPlU46jsnQw /bvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JPEJhmgN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:43 +0000 Message-Id: <20190107163117.16269-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 03/37] hw/cpu: introduce CPU clusters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel This commit adds the cpu-cluster type. It aims at gathering CPUs from the same cluster in a machine. For now it only has a `cluster-id` property. Documentation in cluster.h written with the help of Peter Maydell. Signed-off-by: Luc Michel Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-2-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- hw/cpu/Makefile.objs | 2 +- include/hw/cpu/cluster.h | 58 ++++++++++++++++++++++++++++++++++++++++ hw/cpu/cluster.c | 50 ++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 ++ 4 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 include/hw/cpu/cluster.h create mode 100644 hw/cpu/cluster.c -- 2.19.2 diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs index cd52d20b652..8db9e8a7b3c 100644 --- a/hw/cpu/Makefile.objs +++ b/hw/cpu/Makefile.objs @@ -2,4 +2,4 @@ obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o obj-$(CONFIG_REALVIEW) += realview_mpcore.o obj-$(CONFIG_A9MPCORE) += a9mpcore.o obj-$(CONFIG_A15MPCORE) += a15mpcore.o -common-obj-y += core.o +common-obj-y += core.o cluster.o diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h new file mode 100644 index 00000000000..73818232437 --- /dev/null +++ b/include/hw/cpu/cluster.h @@ -0,0 +1,58 @@ +/* + * QEMU CPU cluster + * + * Copyright (c) 2018 GreenSocs SAS + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ +#ifndef HW_CPU_CLUSTER_H +#define HW_CPU_CLUSTER_H + +#include "qemu/osdep.h" +#include "hw/qdev.h" + +/* + * CPU Cluster type + * + * A cluster is a group of CPUs which are all identical and have the same view + * of the rest of the system. It is mainly an internal QEMU representation and + * does not necessarily match with the notion of clusters on the real hardware. + * + * If CPUs are not identical (for example, Cortex-A53 and Cortex-A57 CPUs in an + * Arm big.LITTLE system) they should be in different clusters. If the CPUs do + * not have the same view of memory (for example the main CPU and a management + * controller processor) they should be in different clusters. + */ + +#define TYPE_CPU_CLUSTER "cpu-cluster" +#define CPU_CLUSTER(obj) \ + OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) + +/** + * CPUClusterState: + * @cluster_id: The cluster ID. This value is for internal use only and should + * not be exposed directly to the user or to the guest. + * + * State of a CPU cluster. + */ +typedef struct CPUClusterState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + uint32_t cluster_id; +} CPUClusterState; + +#endif diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c new file mode 100644 index 00000000000..9d50a235d5c --- /dev/null +++ b/hw/cpu/cluster.c @@ -0,0 +1,50 @@ +/* + * QEMU CPU cluster + * + * Copyright (c) 2018 GreenSocs SAS + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "hw/cpu/cluster.h" +#include "qapi/error.h" +#include "qemu/module.h" + +static Property cpu_cluster_properties[] = { + DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void cpu_cluster_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = cpu_cluster_properties; +} + +static const TypeInfo cpu_cluster_type_info = { + .name = TYPE_CPU_CLUSTER, + .parent = TYPE_DEVICE, + .instance_size = sizeof(CPUClusterState), + .class_init = cpu_cluster_class_init, +}; + +static void cpu_cluster_register_types(void) +{ + type_register_static(&cpu_cluster_type_info); +} + +type_init(cpu_cluster_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 19792cfb2da..471161742de 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1195,7 +1195,9 @@ M: Marcel Apfelbaum S: Supported F: hw/core/machine.c F: hw/core/null-machine.c +F: hw/cpu/cluster.c F: include/hw/boards.h +F: include/hw/cpu/cluster.h T: git https://github.com/ehabkost/qemu.git machine-next Xtensa Machines From patchwork Mon Jan 7 16:30:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154910 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3674026ljp; Mon, 7 Jan 2019 08:38:23 -0800 (PST) X-Google-Smtp-Source: ALg8bN6WtJXQKyUCAnAMsCb+wiS+viIttyNgmIE/bgdn5GpXZ3DkXY1LDxm7G7YqOD9PJI3g5EPn X-Received: by 2002:adf:ee89:: with SMTP id b9mr54413318wro.246.1546879103702; Mon, 07 Jan 2019 08:38:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879103; cv=none; d=google.com; s=arc-20160816; b=BtHonriAihXbpo9rH63FW093vp8T0D9rKfbnWAio2cX6zVfXgDGA/Sg/yxwsxAB57u iocfIE3qqa72X/FheWsNqmyjkfEVOBn9kbEwSxAVqstaSpc02PXop90WL4IMr287x3/Q IUVta3ww/bVbjWA6VJyOGly51rQ1mnPJNvh2t7TED5U8w5oE7WUzJkQPJ39DDxzO8uQZ 50WK+V6ffIojrj2IHInfS4pAqHc6I6wx3Ks2cxjDi42hHeAzjlxiqc9L/CJBDPDbaS3d r/pBuSeiwbPfVMLeuio0sra4DrpgGsiTyuDar7TfQ2Mg7cO4vMdXtVXBDILuRrogWU71 aAUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=vMh6xY1GMYIdM+kfMAqkwNArXmtcSl7a//C6INwAbMg=; b=gQRzfyOtSLz83HflpZEL0Tb7mZ5Zpy2mwlMIgrsnEi/OrNQQTD56QRGaNOOZ+PR58n /a9OpT+D6J7o4hFGZwh9KMu7BdnQt0NajvT8ZSAHCqq1A+w0TytBjJ+PENAJt5tD/AIN GAtPkUQ/5ggeO/ScpOrzP1xhKOylHOsz7+pVXyn3JYwVPhfCsolPyN7osnxDsFr67m0h feD+OI2FCXPkcceiUSUJJVgyRRPXz2v7Tr2pqmF68fIig+PXXJMit/99mQ7JUSE09EjP vUSDKeuzjaKdpy75l1bfqr8RD0ggHKsS+sJA2v2Cm1l9wwIBGBmkSsZXEGtlYJJOc/NY kwrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ih4zsYxf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:44 +0000 Message-Id: <20190107163117.16269-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::332 Subject: [Qemu-devel] [PULL 04/37] gdbstub: introduce GDB processes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Add a structure GDBProcess that represents processes from the GDB semantic point of view. CPUs can be split into different processes, by grouping them under different cpu-cluster objects. Each occurrence of a cpu-cluster object implies the existence of the corresponding process in the GDB stub. The GDB process ID is derived from the corresponding cluster ID as follows: GDB PID = cluster ID + 1 This is because PIDs -1 and 0 are reserved in GDB and cannot be used by processes. A default process is created to handle CPUs that are not in a cluster. This process gets the PID of the last process PID + 1. Signed-off-by: Luc Michel Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181207090135.7651-3-luc.michel@greensocs.com [PMM: fixed checkpatch nit about block comment style] Signed-off-by: Peter Maydell --- gdbstub.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index c4e4f9f0821..9ac6f19a186 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -29,6 +29,7 @@ #include "chardev/char-fe.h" #include "sysemu/sysemu.h" #include "exec/gdbstub.h" +#include "hw/cpu/cluster.h" #endif #define MAX_PACKET_LENGTH 4096 @@ -296,6 +297,11 @@ typedef struct GDBRegisterState { struct GDBRegisterState *next; } GDBRegisterState; +typedef struct GDBProcess { + uint32_t pid; + bool attached; +} GDBProcess; + enum RSState { RS_INACTIVE, RS_IDLE, @@ -324,6 +330,9 @@ typedef struct GDBState { CharBackend chr; Chardev *mon_chr; #endif + bool multiprocess; + GDBProcess *processes; + int process_num; char syscall_buf[256]; gdb_syscall_complete_cb current_syscall_cb; } GDBState; @@ -1751,6 +1760,30 @@ void gdb_exit(CPUArchState *env, int code) #endif } +/* + * Create the process that will contain all the "orphan" CPUs (that are not + * part of a CPU cluster). Note that if this process contains no CPUs, it won't + * be attachable and thus will be invisible to the user. + */ +static void create_default_process(GDBState *s) +{ + GDBProcess *process; + int max_pid = 0; + + if (s->process_num) { + max_pid = s->processes[s->process_num - 1].pid; + } + + s->processes = g_renew(GDBProcess, s->processes, ++s->process_num); + process = &s->processes[s->process_num - 1]; + + /* We need an available PID slot for this process */ + assert(max_pid < UINT32_MAX); + + process->pid = max_pid + 1; + process->attached = false; +} + #ifdef CONFIG_USER_ONLY int gdb_handlesig(CPUState *cpu, int sig) @@ -1848,6 +1881,7 @@ static bool gdb_accept(void) s = g_malloc0(sizeof(GDBState)); s->c_cpu = first_cpu; s->g_cpu = first_cpu; + create_default_process(s); s->fd = fd; gdb_has_xml = false; @@ -2004,6 +2038,65 @@ static const TypeInfo char_gdb_type_info = { .class_init = char_gdb_class_init, }; +static int find_cpu_clusters(Object *child, void *opaque) +{ + if (object_dynamic_cast(child, TYPE_CPU_CLUSTER)) { + GDBState *s = (GDBState *) opaque; + CPUClusterState *cluster = CPU_CLUSTER(child); + GDBProcess *process; + + s->processes = g_renew(GDBProcess, s->processes, ++s->process_num); + + process = &s->processes[s->process_num - 1]; + + /* + * GDB process IDs -1 and 0 are reserved. To avoid subtle errors at + * runtime, we enforce here that the machine does not use a cluster ID + * that would lead to PID 0. + */ + assert(cluster->cluster_id != UINT32_MAX); + process->pid = cluster->cluster_id + 1; + process->attached = false; + + return 0; + } + + return object_child_foreach(child, find_cpu_clusters, opaque); +} + +static int pid_order(const void *a, const void *b) +{ + GDBProcess *pa = (GDBProcess *) a; + GDBProcess *pb = (GDBProcess *) b; + + if (pa->pid < pb->pid) { + return -1; + } else if (pa->pid > pb->pid) { + return 1; + } else { + return 0; + } +} + +static void create_processes(GDBState *s) +{ + object_child_foreach(object_get_root(), find_cpu_clusters, s); + + if (s->processes) { + /* Sort by PID */ + qsort(s->processes, s->process_num, sizeof(s->processes[0]), pid_order); + } + + create_default_process(s); +} + +static void cleanup_processes(GDBState *s) +{ + g_free(s->processes); + s->process_num = 0; + s->processes = NULL; +} + int gdbserver_start(const char *device) { trace_gdbstub_op_start(device); @@ -2060,11 +2153,15 @@ int gdbserver_start(const char *device) } else { qemu_chr_fe_deinit(&s->chr, true); mon_chr = s->mon_chr; + cleanup_processes(s); memset(s, 0, sizeof(GDBState)); s->mon_chr = mon_chr; } s->c_cpu = first_cpu; s->g_cpu = first_cpu; + + create_processes(s); + if (chr) { qemu_chr_fe_init(&s->chr, chr, &error_abort); qemu_chr_fe_set_handlers(&s->chr, gdb_chr_can_receive, gdb_chr_receive, From patchwork Mon Jan 7 16:30:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154905 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3669140ljp; Mon, 7 Jan 2019 08:33:18 -0800 (PST) X-Google-Smtp-Source: ALg8bN7kOR1h98JILURXVl4az/4bVVRZWkjG3UD692cgN2GjUvcnfMIRBomprGfHf8wtRCBFYB6T X-Received: by 2002:adf:bb44:: with SMTP id x4mr54877083wrg.24.1546878798521; Mon, 07 Jan 2019 08:33:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546878798; cv=none; d=google.com; s=arc-20160816; b=fGUOhTUhhm0yiaRGRCrpL0RrMUTpeHmfGXcDdh9dQjqX/00IqGCEybX8V1XyL+eIwU rlaFsNxTmONK5wZiEE6qDbpTcrq2+LPWoLKCiCTQE/4fpO3y3FWm5ahl3uAFkPkpkPvw erNzZcZAMlDRKJ2j51SWsiEMZriEylSWtCUSBx3YDYLc1UhpRi3chgPUOm5onDoAhCSV t/fC0MFnX7YWYHxrOc/vismcNgR6piHTUO1nFmMFV18/NnJhs7yNTGpAlxAaYxB/UI3z l/FYVvaeRYzn2bQxDh+PJNpUWttDr3AkLxibBR64VrOSAJfdjGKMQlpPnxboNorIRRjD FJtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aPHEkDUEPKX+Od0Ed7JXhMgvIC4t96wvbymS1WuuHm0=; b=xrjv3Y7hcOJuRj/Kh83VNBi2ZBkozPN4s10n+Ed0HGt/wLcf9PyjWxULiu9JzWvOT2 9Uf/8wKbFMp9A0369ktqXEpIXrtvUqv0W7PtemiAfCiaJ8Qlv8h5nI3rIzntb5I8zSeq OpExgwtZaxn9X54X2ovumZ84Xf5rrRRtfuXyIoH0LRQtiCzCD8QRL9PFkJHcA7U5jVKH oRf+y6bNV1h8Mj9U5Tl+WD1k0UX9jDBT6R/QNaT5gz7cv0ncMtY4f4jN2uDoQjSLM7KH MJIGMQrL0jEuMaQBrPBJ+CFA34CH17pP9WIXUgIy7Jgn3nER1FgUZqt4z85C3u0eOwwV 8Liw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WslWoJok; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:45 +0000 Message-Id: <20190107163117.16269-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 05/37] gdbstub: add multiprocess support to '?' packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel The gdb_get_cpu_pid() function does the PID lookup for the given CPU. It checks if the CPU is a direct child of a CPU cluster. If it is, the returned PID is the cluster ID plus one (cluster IDs start at 0, GDB PIDs at 1). When the CPU is not a child of such a container, the PID of the default process is returned. The gdb_fmt_thread_id() function generates the string to be used to identify a given thread, in a response packet for the peer. This function supports generating thread IDs when multiprocess mode is enabled (in the form `p.'). Use them in the reply to a '?' request. Signed-off-by: Luc Michel Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-4-luc.michel@greensocs.com [PMM: fixed checkpatch blockquote style nit] Signed-off-by: Peter Maydell --- gdbstub.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 2 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 9ac6f19a186..02beb44d973 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -640,6 +640,54 @@ static int memtox(char *buf, const char *mem, int len) return p - buf; } +static uint32_t gdb_get_cpu_pid(const GDBState *s, CPUState *cpu) +{ +#ifndef CONFIG_USER_ONLY + gchar *path, *name = NULL; + Object *obj; + CPUClusterState *cluster; + uint32_t ret; + + path = object_get_canonical_path(OBJECT(cpu)); + + if (path == NULL) { + /* Return the default process' PID */ + ret = s->processes[s->process_num - 1].pid; + goto out; + } + + name = object_get_canonical_path_component(OBJECT(cpu)); + assert(name != NULL); + + /* + * Retrieve the CPU parent path by removing the last '/' and the CPU name + * from the CPU canonical path. + */ + path[strlen(path) - strlen(name) - 1] = '\0'; + + obj = object_resolve_path_type(path, TYPE_CPU_CLUSTER, NULL); + + if (obj == NULL) { + /* Return the default process' PID */ + ret = s->processes[s->process_num - 1].pid; + goto out; + } + + cluster = CPU_CLUSTER(obj); + ret = cluster->cluster_id + 1; + +out: + g_free(name); + g_free(path); + + return ret; + +#else + /* TODO: In user mode, we should use the task state PID */ + return s->processes[s->process_num - 1].pid; +#endif +} + static const char *get_feature_xml(const char *p, const char **newp, CPUClass *cc) { @@ -909,6 +957,19 @@ static CPUState *find_cpu(uint32_t thread_id) return NULL; } +static char *gdb_fmt_thread_id(const GDBState *s, CPUState *cpu, + char *buf, size_t buf_size) +{ + if (s->multiprocess) { + snprintf(buf, buf_size, "p%02x.%02x", + gdb_get_cpu_pid(s, cpu), cpu_gdb_index(cpu)); + } else { + snprintf(buf, buf_size, "%02x", cpu_gdb_index(cpu)); + } + + return buf; +} + static int is_query_packet(const char *p, const char *query, char separator) { unsigned int query_len = strlen(query); @@ -1020,6 +1081,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) int ch, reg_size, type, res; uint8_t mem_buf[MAX_PACKET_LENGTH]; char buf[sizeof(mem_buf) + 1 /* trailing NUL */]; + char thread_id[16]; uint8_t *registers; target_ulong addr, len; @@ -1030,8 +1092,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) switch(ch) { case '?': /* TODO: Make this return the correct value for user-mode. */ - snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP, - cpu_gdb_index(s->c_cpu)); + snprintf(buf, sizeof(buf), "T%02xthread:%s;", GDB_SIGNAL_TRAP, + gdb_fmt_thread_id(s, s->c_cpu, thread_id, sizeof(thread_id))); put_packet(s, buf); /* Remove all the breakpoints when this query is issued, * because gdb is doing and initial connect and the state From patchwork Mon Jan 7 16:30:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154908 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3672492ljp; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:46 +0000 Message-Id: <20190107163117.16269-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 06/37] gdbstub: add multiprocess support to 'H' and 'T' packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Add a couple of helper functions to cope with GDB threads and processes. The gdb_get_process() function looks for a process given a pid. The gdb_get_cpu() function returns the CPU corresponding to the (pid, tid) pair given as parameters. The read_thread_id() function parses the thread-id sent by the peer. This function supports the multiprocess extension thread-id syntax. The return value specifies if the parsing failed, or if a special case was encountered (all processes or all threads). Use them in 'H' and 'T' packets handling to support the multiprocess extension. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-5-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 136 insertions(+), 18 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 02beb44d973..644377db9f5 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -688,6 +688,71 @@ out: #endif } +static GDBProcess *gdb_get_process(const GDBState *s, uint32_t pid) +{ + int i; + + if (!pid) { + /* 0 means any process, we take the first one */ + return &s->processes[0]; + } + + for (i = 0; i < s->process_num; i++) { + if (s->processes[i].pid == pid) { + return &s->processes[i]; + } + } + + return NULL; +} + +static GDBProcess *gdb_get_cpu_process(const GDBState *s, CPUState *cpu) +{ + return gdb_get_process(s, gdb_get_cpu_pid(s, cpu)); +} + +static CPUState *find_cpu(uint32_t thread_id) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + if (cpu_gdb_index(cpu) == thread_id) { + return cpu; + } + } + + return NULL; +} + +static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid) +{ + GDBProcess *process; + CPUState *cpu; + + if (!tid) { + /* 0 means any thread, we take the first one */ + tid = 1; + } + + cpu = find_cpu(tid); + + if (cpu == NULL) { + return NULL; + } + + process = gdb_get_cpu_process(s, cpu); + + if (process->pid != pid) { + return NULL; + } + + if (!process->attached) { + return NULL; + } + + return cpu; +} + static const char *get_feature_xml(const char *p, const char **newp, CPUClass *cc) { @@ -944,19 +1009,6 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) cpu_set_pc(cpu, pc); } -static CPUState *find_cpu(uint32_t thread_id) -{ - CPUState *cpu; - - CPU_FOREACH(cpu) { - if (cpu_gdb_index(cpu) == thread_id) { - return cpu; - } - } - - return NULL; -} - static char *gdb_fmt_thread_id(const GDBState *s, CPUState *cpu, char *buf, size_t buf_size) { @@ -970,6 +1022,60 @@ static char *gdb_fmt_thread_id(const GDBState *s, CPUState *cpu, return buf; } +typedef enum GDBThreadIdKind { + GDB_ONE_THREAD = 0, + GDB_ALL_THREADS, /* One process, all threads */ + GDB_ALL_PROCESSES, + GDB_READ_THREAD_ERR +} GDBThreadIdKind; + +static GDBThreadIdKind read_thread_id(const char *buf, const char **end_buf, + uint32_t *pid, uint32_t *tid) +{ + unsigned long p, t; + int ret; + + if (*buf == 'p') { + buf++; + ret = qemu_strtoul(buf, &buf, 16, &p); + + if (ret) { + return GDB_READ_THREAD_ERR; + } + + /* Skip '.' */ + buf++; + } else { + p = 1; + } + + ret = qemu_strtoul(buf, &buf, 16, &t); + + if (ret) { + return GDB_READ_THREAD_ERR; + } + + *end_buf = buf; + + if (p == -1) { + return GDB_ALL_PROCESSES; + } + + if (pid) { + *pid = p; + } + + if (t == -1) { + return GDB_ALL_THREADS; + } + + if (tid) { + *tid = t; + } + + return GDB_ONE_THREAD; +} + static int is_query_packet(const char *p, const char *query, char separator) { unsigned int query_len = strlen(query); @@ -1078,12 +1184,14 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) CPUClass *cc; const char *p; uint32_t thread; + uint32_t pid, tid; int ch, reg_size, type, res; uint8_t mem_buf[MAX_PACKET_LENGTH]; char buf[sizeof(mem_buf) + 1 /* trailing NUL */]; char thread_id[16]; uint8_t *registers; target_ulong addr, len; + GDBThreadIdKind thread_kind; trace_gdbstub_io_command(line_buf); @@ -1291,12 +1399,18 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) break; case 'H': type = *p++; - thread = strtoull(p, (char **)&p, 16); - if (thread == -1 || thread == 0) { + + thread_kind = read_thread_id(p, &p, &pid, &tid); + if (thread_kind == GDB_READ_THREAD_ERR) { + put_packet(s, "E22"); + break; + } + + if (thread_kind != GDB_ONE_THREAD) { put_packet(s, "OK"); break; } - cpu = find_cpu(thread); + cpu = gdb_get_cpu(s, pid, tid); if (cpu == NULL) { put_packet(s, "E22"); break; @@ -1316,8 +1430,12 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) } break; case 'T': - thread = strtoull(p, (char **)&p, 16); - cpu = find_cpu(thread); + thread_kind = read_thread_id(p, &p, &pid, &tid); + if (thread_kind == GDB_READ_THREAD_ERR) { + put_packet(s, "E22"); + break; + } + cpu = gdb_get_cpu(s, pid, tid); if (cpu != NULL) { put_packet(s, "OK"); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:47 +0000 Message-Id: <20190107163117.16269-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 07/37] gdbstub: add multiprocess support to vCont packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Add the gdb_first_attached_cpu() and gdb_next_attached_cpu() to iterate over all the CPUs in currently attached processes. Add the gdb_first_cpu_in_process() and gdb_next_cpu_in_process() to iterate over CPUs of a given process. Use them to add multiprocess extension support to vCont packets. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-6-luc.michel@greensocs.com [PMM: corrected checkpatch comment style nit] Signed-off-by: Peter Maydell --- gdbstub.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 100 insertions(+), 15 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 644377db9f5..09114ea7769 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -724,6 +724,36 @@ static CPUState *find_cpu(uint32_t thread_id) return NULL; } +static CPUState *get_first_cpu_in_process(const GDBState *s, + GDBProcess *process) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + if (gdb_get_cpu_pid(s, cpu) == process->pid) { + return cpu; + } + } + + return NULL; +} + +static CPUState *gdb_next_cpu_in_process(const GDBState *s, CPUState *cpu) +{ + uint32_t pid = gdb_get_cpu_pid(s, cpu); + cpu = CPU_NEXT(cpu); + + while (cpu) { + if (gdb_get_cpu_pid(s, cpu) == pid) { + break; + } + + cpu = CPU_NEXT(cpu); + } + + return cpu; +} + static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid) { GDBProcess *process; @@ -753,6 +783,35 @@ static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid) return cpu; } +/* Return the cpu following @cpu, while ignoring unattached processes. */ +static CPUState *gdb_next_attached_cpu(const GDBState *s, CPUState *cpu) +{ + cpu = CPU_NEXT(cpu); + + while (cpu) { + if (gdb_get_cpu_process(s, cpu)->attached) { + break; + } + + cpu = CPU_NEXT(cpu); + } + + return cpu; +} + +/* Return the first attached cpu */ +static CPUState *gdb_first_attached_cpu(const GDBState *s) +{ + CPUState *cpu = first_cpu; + GDBProcess *process = gdb_get_cpu_process(s, cpu); + + if (!process->attached) { + return gdb_next_attached_cpu(s, cpu); + } + + return cpu; +} + static const char *get_feature_xml(const char *p, const char **newp, CPUClass *cc) { @@ -1091,10 +1150,12 @@ static int is_query_packet(const char *p, const char *query, char separator) */ static int gdb_handle_vcont(GDBState *s, const char *p) { - int res, idx, signal = 0; + int res, signal = 0; char cur_action; char *newstates; unsigned long tmp; + uint32_t pid, tid; + GDBProcess *process; CPUState *cpu; #ifdef CONFIG_USER_ONLY int max_cpus = 1; /* global variable max_cpus exists only in system mode */ @@ -1137,25 +1198,48 @@ static int gdb_handle_vcont(GDBState *s, const char *p) res = -ENOTSUP; goto out; } - /* thread specification. special values: (none), -1 = all; 0 = any */ - if ((p[0] == ':' && p[1] == '-' && p[2] == '1') || (p[0] != ':')) { - if (*p == ':') { - p += 3; - } - for (idx = 0; idx < max_cpus; idx++) { - if (newstates[idx] == 1) { - newstates[idx] = cur_action; + + if (*p++ != ':') { + res = -ENOTSUP; + goto out; + } + + switch (read_thread_id(p, &p, &pid, &tid)) { + case GDB_READ_THREAD_ERR: + res = -EINVAL; + goto out; + + case GDB_ALL_PROCESSES: + cpu = gdb_first_attached_cpu(s); + while (cpu) { + if (newstates[cpu->cpu_index] == 1) { + newstates[cpu->cpu_index] = cur_action; } + + cpu = gdb_next_attached_cpu(s, cpu); } - } else if (*p == ':') { - p++; - res = qemu_strtoul(p, &p, 16, &tmp); - if (res) { + break; + + case GDB_ALL_THREADS: + process = gdb_get_process(s, pid); + + if (!process->attached) { + res = -EINVAL; goto out; } - /* 0 means any thread, so we pick the first valid CPU */ - cpu = tmp ? find_cpu(tmp) : first_cpu; + cpu = get_first_cpu_in_process(s, process); + while (cpu) { + if (newstates[cpu->cpu_index] == 1) { + newstates[cpu->cpu_index] = cur_action; + } + + cpu = gdb_next_cpu_in_process(s, cpu); + } + break; + + case GDB_ONE_THREAD: + cpu = gdb_get_cpu(s, pid, tid); /* invalid CPU/thread specified */ if (!cpu) { @@ -1167,6 +1251,7 @@ static int gdb_handle_vcont(GDBState *s, const char *p) if (newstates[cpu->cpu_index] == 1) { newstates[cpu->cpu_index] = cur_action; } + break; } } s->signal = signal; From patchwork Mon Jan 7 16:30:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154927 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3681656ljp; Mon, 7 Jan 2019 08:46:52 -0800 (PST) X-Google-Smtp-Source: ALg8bN7fIFKjrgbAFmRPTZWZOQ2Tfos3S/j3mZcWVg8QhgFglQjPo7L4YlBBWoLXiDC/GXkYCLvr X-Received: by 2002:a5d:694d:: with SMTP id r13mr50209888wrw.323.1546879612157; Mon, 07 Jan 2019 08:46:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879612; cv=none; d=google.com; s=arc-20160816; b=OSeKKs+/GC+Msn4AKINFhELrdrfCnaiD2e2LUqAYqcvPwywag4qHXafORnZtgHCLXc Wh/zTYpDa+Tig3lkN00PCfQVwRxeMZUbF5mGfIqz95yYhfgtD3+7lZOlBsQLLE9l21zv C0l6srpHrM35vjKxdoVHmCMBFjuoQ3iA8lHfS/dgqbRsL0aQ2fkzo3GVbFN7uw4KNmVO 9s2AHzdTkoubRP3lYuyvMvvTX8lK4eH7gsIU2AIaOyb+B5tQuI9/G9ZzdcfR/eXbxfED hIk/YhUJVHbGsIlP/gSf3ykw/TXP/uVekv+20pT//iZehAS3e6qwqnv+IYOcOPTH577J dWcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=YmllhqSrlPuqu/kNnOCys3nYm3gqrfzNAGZ2x7fkAlw=; b=hLT+r46KtrfgqQE2mIbZJ3M2rAIRFDQvy/8kUo3oNYJx7O6qJvMSeeYckP5ISmYkJz 86Ujn03H2aJ22EynDok+MZxxZ3oDmTTwJIhKzJYEEJ3+mixkkdPnVWFThD7xmj68zkGI iRp9yZZXVZEBG3NHjJSONRa/ZFzgWgbHrwgcOvW26dW/zz9Ebf1qcCGh8RXm0vyxQ93n yQe+/C+x1u8GVuR4kpEiA9KRXVGiTEnnDOdtm7LDwYvVAc7s7R8xBxiyEgHVLKMOiIz0 GnATNdFi2zvOr0RtNkf8VjvNtNBAAtSC6xzFpOQiRwaTpI49+3XUGfBebC2bWFPlF4Jn U9hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IB5vzVrm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:48 +0000 Message-Id: <20190107163117.16269-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 08/37] gdbstub: add multiprocess support to 'sC' packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Change the sC packet handling to support the multiprocess extension. Instead of returning the first thread, we return the first thread of the current process. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-7-luc.michel@greensocs.com [PMM: corrected checkpatch comment style nit] Signed-off-by: Peter Maydell --- gdbstub.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 09114ea7769..1ba7aa6a28a 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1554,9 +1554,15 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) put_packet(s, "OK"); break; } else if (strcmp(p,"C") == 0) { - /* "Current thread" remains vague in the spec, so always return - * the first CPU (gdb returns the first thread). */ - put_packet(s, "QC1"); + /* + * "Current thread" remains vague in the spec, so always return + * the first thread of the current process (gdb returns the + * first thread). + */ + cpu = get_first_cpu_in_process(s, gdb_get_cpu_process(s, s->g_cpu)); + snprintf(buf, sizeof(buf), "QC%s", + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id))); + put_packet(s, buf); break; } else if (strcmp(p,"fThreadInfo") == 0) { s->query_cpu = first_cpu; From patchwork Mon Jan 7 16:30:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154904 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3667929ljp; Mon, 7 Jan 2019 08:32:11 -0800 (PST) X-Google-Smtp-Source: ALg8bN59NbdXDmTeats/6MOjEuXdqZfB6u046sZik2M8AyTRUI66ri5MAd9Bk+c65GDh9t6CwoLl X-Received: by 2002:a1c:ce0e:: with SMTP id e14mr9849946wmg.53.1546878731730; Mon, 07 Jan 2019 08:32:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546878731; cv=none; d=google.com; s=arc-20160816; b=paRvi+TLk/XMQa+yKyvH8pi+87LywjH46/h/YaHjqIKu3WXNV5UVBF7TQjHdek55Y+ 8yG+iYR+Qkb5yS6/CBfI1u5n4E+nveXrUQxwph7fbqsmIMD4mmR+QqRhsJX5G3qINvK1 q1kI37X6p6FDeGraXzGKxxHhLhOpYhJZ5ymTaJ+4Q7uuLgBDIQ5FZGgpHtJUj1LKecwr bbIGpIfgKJpzF2EdvqvdgvtfvTNAloOlFqtTzbzh1WSkhDt97abN5OmlVAH7LCQsOGsH HmKpvsllyB+7Gs1tiVRjmzZMln6qQbyhUqphCtAuS7gVrXi/f5ZYFyXwKpuPzG+6c67x C5RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=qzU0ympb5SfpvFVwfmO3i1qJ2YHOQU/0Au0uTSOXsmk=; b=dwgz/X/HwV2lTyFGykyNF0Zmd2rHFJyQbOmg0d1xnNQYeanjNAdtu0h0UgXut2v57d 8HR/l8Omij3u9KrLHKEOFx3uHcENHahoYdkD4CpR91g+52RN5zHWDr7hzz48O0TphFgE ayicjAwMPxkGbFlWzqykO6jtSrlCgsNwgeBWcyUvKaN6t5Hc8OGK+BwhwDEwYuZSP0mU kX6xHw1g7RCgWjkYDCQdEHghXBk9I1pbctxCXRPehGdEr2JEAJWu2hDwxI9v1zFWt1XP ANG0K/aSAufrAJvq3G2mXr/ifycEcDkvBXD3y0QSxZLycjPlWSd4wymiL5NcpvmKKQD7 iyqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZxKIykM3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:49 +0000 Message-Id: <20190107163117.16269-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d Subject: [Qemu-devel] [PULL 09/37] gdbstub: add multiprocess support to (f|s)ThreadInfo and ThreadExtraInfo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Change the thread info related packets handling to support multiprocess extension. Add the CPUs class name in the extra info to help differentiate them in multiprocess mode. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20181207090135.7651-8-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 1ba7aa6a28a..f70b5a326fe 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1268,7 +1268,6 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) CPUState *cpu; CPUClass *cc; const char *p; - uint32_t thread; uint32_t pid, tid; int ch, reg_size, type, res; uint8_t mem_buf[MAX_PACKET_LENGTH]; @@ -1565,26 +1564,44 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) put_packet(s, buf); break; } else if (strcmp(p,"fThreadInfo") == 0) { - s->query_cpu = first_cpu; + s->query_cpu = gdb_first_attached_cpu(s); goto report_cpuinfo; } else if (strcmp(p,"sThreadInfo") == 0) { report_cpuinfo: if (s->query_cpu) { - snprintf(buf, sizeof(buf), "m%x", cpu_gdb_index(s->query_cpu)); + snprintf(buf, sizeof(buf), "m%s", + gdb_fmt_thread_id(s, s->query_cpu, + thread_id, sizeof(thread_id))); put_packet(s, buf); - s->query_cpu = CPU_NEXT(s->query_cpu); + s->query_cpu = gdb_next_attached_cpu(s, s->query_cpu); } else put_packet(s, "l"); break; } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) { - thread = strtoull(p+16, (char **)&p, 16); - cpu = find_cpu(thread); + if (read_thread_id(p + 16, &p, &pid, &tid) == GDB_READ_THREAD_ERR) { + put_packet(s, "E22"); + break; + } + cpu = gdb_get_cpu(s, pid, tid); if (cpu != NULL) { cpu_synchronize_state(cpu); - /* memtohex() doubles the required space */ - len = snprintf((char *)mem_buf, sizeof(buf) / 2, - "CPU#%d [%s]", cpu->cpu_index, - cpu->halted ? "halted " : "running"); + + if (s->multiprocess && (s->process_num > 1)) { + /* Print the CPU model and name in multiprocess mode */ + ObjectClass *oc = object_get_class(OBJECT(cpu)); + const char *cpu_model = object_class_get_name(oc); + char *cpu_name = + object_get_canonical_path_component(OBJECT(cpu)); + len = snprintf((char *)mem_buf, sizeof(buf) / 2, + "%s %s [%s]", cpu_model, cpu_name, + cpu->halted ? "halted " : "running"); + g_free(cpu_name); + } else { + /* memtohex() doubles the required space */ + len = snprintf((char *)mem_buf, sizeof(buf) / 2, + "CPU#%d [%s]", cpu->cpu_index, + cpu->halted ? "halted " : "running"); + } trace_gdbstub_op_extra_info((char *)mem_buf); memtohex(buf, mem_buf, len); put_packet(s, buf); From patchwork Mon Jan 7 16:30:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154918 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3675100ljp; Mon, 7 Jan 2019 08:39:37 -0800 (PST) X-Google-Smtp-Source: ALg8bN73fIbs7o47h7wv1+jIWzjH/xABF+N9E6EUH2z4MLw2StIVyTX+hYlNmWPCfsbhgNOQutJV X-Received: by 2002:a1c:3282:: with SMTP id y124mr2007739wmy.134.1546879177203; Mon, 07 Jan 2019 08:39:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879177; cv=none; d=google.com; s=arc-20160816; b=T7OTPOmLZx8whnJgIbghqpcxyNGOI98qGQCBAJUhGaMV4H+7Vw649/NVkF79Q5u9zr 0GyqgF4kU7ADMbOIfFc9isH0+SuvYTJqb2I8Q/uSaV8HLLTt1yeznTvjyBowcTv5AB/m UJUEdI133s+dvBHkI3e8uMRS4r/tGOLRn84HRTWVPSjurbJAa2iE4dOLuj3zuLrbqPXl ZMqieeZxSEBaaprO+0lIuaL4TcXKFVnSpmnGxaAIyof9G/Y4D/wzHAUuLcCNnXcJE0Bs BZN+NCEepA3HlYyc4veYDzxMepO8RGs2tJJ66+Kj1OxXX9GOtimUHcw2diZLDrSW2DUz eUKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BttWZQoZnqRZyHxMFdEOuZXRafzydfBLYBSIF6UEwhQ=; b=UvsDCUUCT/EuH+fnMkWrRppy7mCqX4qqtLoeMTW2/RY4RBv/xnLOW3QxsE+q+/DOIO Ai7IuJpKIN8/M6NX3OWkVgXpwQkTfoUVOqhiYIoEhaG/wkwyIXVWXtTAQnGPSWoLSsb4 l/nUpT2TVzIAHFWfz0cdEAU25lXFx6Ys4gy133oJ5kihJGQ7yjbJJxVuUNW8AJktjOGT IRGmR6TVovZw5K2G/9UQZ0OOADiW8ppwFsfjIYbXd+aWCGTqWWZVBPPOmz/u7qLW0KLw WK2EWY0Sgpv1vVx2OmsLXkCFoGD9KwM7LGykYUHSKiZAwyI0iO76H4IStdVBKrdz0+St HkEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gUxVjRAv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:50 +0000 Message-Id: <20190107163117.16269-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32b Subject: [Qemu-devel] [PULL 10/37] gdbstub: add multiprocess support to Xfer:features:read: X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Change the Xfer:features:read: packet handling to support the multiprocess extension. This packet is used to request the XML description of the CPU. In multiprocess mode, different descriptions can be sent for different processes. This function now takes the process to send the description for as a parameter, and use a buffer in the process structure to store the generated description. It takes the first CPU of the process to generate the description. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20181207090135.7651-9-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 52 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 22 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index f70b5a326fe..1f2b155490d 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -300,6 +300,8 @@ typedef struct GDBRegisterState { typedef struct GDBProcess { uint32_t pid; bool attached; + + char target_xml[1024]; } GDBProcess; enum RSState { @@ -812,13 +814,14 @@ static CPUState *gdb_first_attached_cpu(const GDBState *s) return cpu; } -static const char *get_feature_xml(const char *p, const char **newp, - CPUClass *cc) +static const char *get_feature_xml(const GDBState *s, const char *p, + const char **newp, GDBProcess *process) { size_t len; int i; const char *name; - static char target_xml[1024]; + CPUState *cpu = get_first_cpu_in_process(s, process); + CPUClass *cc = CPU_GET_CLASS(cpu); len = 0; while (p[len] && p[len] != ':') @@ -827,36 +830,37 @@ static const char *get_feature_xml(const char *p, const char **newp, name = NULL; if (strncmp(p, "target.xml", len) == 0) { - /* Generate the XML description for this CPU. */ - if (!target_xml[0]) { - GDBRegisterState *r; - CPUState *cpu = first_cpu; + char *buf = process->target_xml; + const size_t buf_sz = sizeof(process->target_xml); - pstrcat(target_xml, sizeof(target_xml), + /* Generate the XML description for this CPU. */ + if (!buf[0]) { + GDBRegisterState *r; + + pstrcat(buf, buf_sz, "" "" ""); if (cc->gdb_arch_name) { gchar *arch = cc->gdb_arch_name(cpu); - pstrcat(target_xml, sizeof(target_xml), ""); - pstrcat(target_xml, sizeof(target_xml), arch); - pstrcat(target_xml, sizeof(target_xml), ""); + pstrcat(buf, buf_sz, ""); + pstrcat(buf, buf_sz, arch); + pstrcat(buf, buf_sz, ""); g_free(arch); } - pstrcat(target_xml, sizeof(target_xml), "gdb_core_xml_file); - pstrcat(target_xml, sizeof(target_xml), "\"/>"); + pstrcat(buf, buf_sz, "gdb_core_xml_file); + pstrcat(buf, buf_sz, "\"/>"); for (r = cpu->gdb_regs; r; r = r->next) { - pstrcat(target_xml, sizeof(target_xml), "xml); - pstrcat(target_xml, sizeof(target_xml), "\"/>"); + pstrcat(buf, buf_sz, "xml); + pstrcat(buf, buf_sz, "\"/>"); } - pstrcat(target_xml, sizeof(target_xml), ""); + pstrcat(buf, buf_sz, ""); } - return target_xml; + return buf; } if (cc->gdb_get_dynamic_xml) { - CPUState *cpu = first_cpu; char *xmlname = g_strndup(p, len); const char *xml = cc->gdb_get_dynamic_xml(cpu, xmlname); @@ -1266,6 +1270,7 @@ out: static int gdb_handle_packet(GDBState *s, const char *line_buf) { CPUState *cpu; + GDBProcess *process; CPUClass *cc; const char *p; uint32_t pid, tid; @@ -1650,14 +1655,15 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) const char *xml; target_ulong total_len; - cc = CPU_GET_CLASS(first_cpu); + process = gdb_get_cpu_process(s, s->g_cpu); + cc = CPU_GET_CLASS(s->g_cpu); if (cc->gdb_core_xml_file == NULL) { goto unknown_command; } gdb_has_xml = true; p += 19; - xml = get_feature_xml(p, &p, cc); + xml = get_feature_xml(s, p, &p, process); if (!xml) { snprintf(buf, sizeof(buf), "E00"); put_packet(s, buf); @@ -2070,6 +2076,7 @@ static void create_default_process(GDBState *s) process->pid = max_pid + 1; process->attached = false; + process->target_xml[0] = '\0'; } #ifdef CONFIG_USER_ONLY @@ -2345,6 +2352,7 @@ static int find_cpu_clusters(Object *child, void *opaque) assert(cluster->cluster_id != UINT32_MAX); process->pid = cluster->cluster_id + 1; process->attached = false; + process->target_xml[0] = '\0'; return 0; } From patchwork Mon Jan 7 16:30:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154923 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3677801ljp; Mon, 7 Jan 2019 08:42:36 -0800 (PST) X-Google-Smtp-Source: ALg8bN64HvWW3tNYUoh5CjeqicrA8vQQXeUXcB4oFds0hUdZyiIgkTHRvjR0y3+5IraNB2UGme9T X-Received: by 2002:adf:9f10:: with SMTP id l16mr53377884wrf.206.1546879355968; Mon, 07 Jan 2019 08:42:35 -0800 (PST) ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:51 +0000 Message-Id: <20190107163117.16269-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 11/37] gdbstub: add multiprocess support to gdb_vm_state_change() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Add support for multiprocess extension in gdb_vm_state_change() function. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-10-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 1f2b155490d..edee38b6136 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1724,6 +1724,7 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) GDBState *s = gdbserver_state; CPUState *cpu = s->c_cpu; char buf[256]; + char thread_id[16]; const char *type; int ret; @@ -1735,6 +1736,14 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) put_packet(s, s->syscall_buf); return; } + + if (cpu == NULL) { + /* No process attached */ + return; + } + + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id)); + switch (state) { case RUN_STATE_DEBUG: if (cpu->watchpoint_hit) { @@ -1752,8 +1761,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) trace_gdbstub_hit_watchpoint(type, cpu_gdb_index(cpu), (target_ulong)cpu->watchpoint_hit->vaddr); snprintf(buf, sizeof(buf), - "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";", - GDB_SIGNAL_TRAP, cpu_gdb_index(cpu), type, + "T%02xthread:%s;%swatch:" TARGET_FMT_lx ";", + GDB_SIGNAL_TRAP, thread_id, type, (target_ulong)cpu->watchpoint_hit->vaddr); cpu->watchpoint_hit = NULL; goto send_packet; @@ -1795,7 +1804,7 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) break; } gdb_set_stop_cpu(cpu); - snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, cpu_gdb_index(cpu)); + snprintf(buf, sizeof(buf), "T%02xthread:%s;", ret, thread_id); send_packet: put_packet(s, buf); From patchwork Mon Jan 7 16:30:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154920 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3676478ljp; Mon, 7 Jan 2019 08:41:09 -0800 (PST) X-Google-Smtp-Source: ALg8bN7zrbOYzj8FVr3F9Eo2u6XrO9S7pgypaHAwixaQpcNrNLQzKyOwxKn9g0qeMeo3pvzinPVN X-Received: by 2002:adf:bc87:: with SMTP id g7mr50438299wrh.250.1546879269028; Mon, 07 Jan 2019 08:41:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879269; cv=none; d=google.com; s=arc-20160816; b=B3Rc+Ue/MnGPFy8l5AL3U5Tb28dxLz8QgmYLA9xEoCyo5BnI8R3moCOiptgV6tSKR3 ZPOPCYf2QQ9aJ4wLKCesI6wxwDHr0QdTJWgU0Ity0KDctC4aE3QGmgJYXOl0lkxzT1kS q3MVyebF+NwKMXXEsr6ozu3KrKObFZGalUxXMQS6aicNiwLh0Mrs2YwliWWRdj0HUttZ p5m82yrbxihoQ6UOrLEfeAY5sDXpDdQqPSznLBAkyEJddZHsocZC848C6i/As8vjBelJ io+FyR08uYSbTID7pzV7jqGxnDwd9LTd/dWTMzcVxZnfMHLvzPEB1Mw2uXR3g/EMbHJZ 3svQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=1s/FyqcakpdikFoKdyxVjsd1dTTqxskhDVsUDUlN9cs=; b=R7Au8kGfSUMuw+WDdElaBqxN/O2eR5AsHJ3Y4LizCvece54Mkw84xbsWG9WbW4jT/O tul8xnNrr2RFXkhyiaXTNZRel5GuiI881ChcEcgijBrAA85+sgbyxkQdJBphBcdaqiVY 6O+rTfWjLbAn8zsgUKy2vXaKlSDuR5P5EsXRDPZMYmGOO+PwqVlh2C2daWLSAGKgnDoB 40vFyAn4oVGAUfedf75O7h8fXNrcNCF5+hAoQ+QXms9XQsC6R3cOgqfOKHcqGhppdn/v 08Kh5gKHfocYnnDnQN+YRroegmqAsvBa/kUQSmW/AYS4LxjXpEhPTd9sfk13xLPjmlPO Iwbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XTFDdOfY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:52 +0000 Message-Id: <20190107163117.16269-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 12/37] gdbstub: add multiprocess support to 'D' packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel 'D' packets are used by GDB to detach from a process. In multiprocess mode, the PID to detach from is sent in the request. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-11-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 53 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index edee38b6136..2c7032f53ab 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1047,6 +1047,24 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) } } +static inline void gdb_cpu_breakpoint_remove_all(CPUState *cpu) +{ + cpu_breakpoint_remove_all(cpu, BP_GDB); +#ifndef CONFIG_USER_ONLY + cpu_watchpoint_remove_all(cpu, BP_GDB); +#endif +} + +static void gdb_process_breakpoint_remove_all(const GDBState *s, GDBProcess *p) +{ + CPUState *cpu = get_first_cpu_in_process(s, p); + + while (cpu) { + gdb_cpu_breakpoint_remove_all(cpu); + cpu = gdb_next_cpu_in_process(s, cpu); + } +} + static void gdb_breakpoint_remove_all(void) { CPUState *cpu; @@ -1057,10 +1075,7 @@ static void gdb_breakpoint_remove_all(void) } CPU_FOREACH(cpu) { - cpu_breakpoint_remove_all(cpu, BP_GDB); -#ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(cpu, BP_GDB); -#endif + gdb_cpu_breakpoint_remove_all(cpu); } } @@ -1339,9 +1354,40 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) exit(0); case 'D': /* Detach packet */ - gdb_breakpoint_remove_all(); - gdb_syscall_mode = GDB_SYS_DISABLED; - gdb_continue(s); + pid = 1; + + if (s->multiprocess) { + unsigned long lpid; + if (*p != ';') { + put_packet(s, "E22"); + break; + } + + if (qemu_strtoul(p + 1, &p, 16, &lpid)) { + put_packet(s, "E22"); + break; + } + + pid = lpid; + } + + process = gdb_get_process(s, pid); + gdb_process_breakpoint_remove_all(s, process); + process->attached = false; + + if (pid == gdb_get_cpu_pid(s, s->c_cpu)) { + s->c_cpu = gdb_first_attached_cpu(s); + } + + if (pid == gdb_get_cpu_pid(s, s->g_cpu)) { + s->g_cpu = gdb_first_attached_cpu(s); + } + + if (s->c_cpu == NULL) { + /* No more process attached */ + gdb_syscall_mode = GDB_SYS_DISABLED; + gdb_continue(s); + } put_packet(s, "OK"); break; case 's': From patchwork Mon Jan 7 16:30:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154934 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3686676ljp; Mon, 7 Jan 2019 08:52:46 -0800 (PST) X-Google-Smtp-Source: ALg8bN6xh7q/K3i1fEKQaNA93vXvnzRobeAXC06ntCJkDAxDWWpzVlWmnTYGSsqsaZ5GQKaYtz5L X-Received: by 2002:adf:90e5:: with SMTP id i92mr49554123wri.210.1546879965972; Mon, 07 Jan 2019 08:52:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879965; cv=none; d=google.com; s=arc-20160816; b=P6mCG4KUaMcdqEVr00693bIQCXqpRB2YHA+H2mYBBvCw6VMXUDbiX6lLAi9AkIUK5y OyHi6zSlRe0e42vxDyZMmMXxVm0YvvmomXffhZuCb3WpW1H24Tfkm+eBkwQ3totnNBZa NRcvcofMBCSP9p3tteyVPUr+WTj/Uugs3s5WjjZq/vXwvA/GY8g36kXzPEE7c6kI+bYi 7eHM/7Kj0lpEiPhLDpqEYW6ISZDCYcmpLk41bKEWWGNSD1ox0A5Vvk7RvbbbEKn6YkTH FHlr92PSwGAW49kzbQ1vOo/x+gTT6JMD9Dw8UMpe7SMS7zRtn5yakGJ5s+LCMjrSfPRn RZyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=KDpKGtvo/v3wqjD/NhUG0S90lilluzyMNggPM3w6PTs=; b=LhNBWKiTUu6e6ajEciSRdLS8JvB3klP8joGhaez8+xc3rVDlY5M8i21w+3zpqvEQOL wyqC5miOwC2l62jwYbbiOUojvMZu1PNQgIvIpqq6QMkBo61spDbrEcMb3B4bMzzVsRrr gZREF3k/9jJjG1LCVpnx8sBZTVVdVDTH1i8T81VzWwIjQN6nCANbR1aAvLd76FMdLLov leR08EVG2d1lZAya5cWP6uq18tSS7WakvMTwfG8ClLF2XGAphrq3vP21wooLGHhYsdJ5 3qmen9OPmyJSglk6SuRK87P2BvUueeb0MLSmGH8nFQusKg3ycpfi1USTOoMW8DG23oIu AvTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=O0yhLXCp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:53 +0000 Message-Id: <20190107163117.16269-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 13/37] gdbstub: add support for extended mode packet X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Add support for the '!' extended mode packet. This is required for the multiprocess extension. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-12-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 2c7032f53ab..9b6b4d20a02 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1302,6 +1302,9 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) p = line_buf; ch = *p++; switch(ch) { + case '!': + put_packet(s, "OK"); + break; case '?': /* TODO: Make this return the correct value for user-mode. */ snprintf(buf, sizeof(buf), "T%02xthread:%s;", GDB_SIGNAL_TRAP, From patchwork Mon Jan 7 16:30:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154928 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3682023ljp; Mon, 7 Jan 2019 08:47:16 -0800 (PST) X-Google-Smtp-Source: ALg8bN6n7yveuRAIGKa1RYnlwCVBRPQN2fc+c05soskQ5h2mnmqe3MMMYI0DqR9owlYImbfsuHW6 X-Received: by 2002:a5d:494a:: with SMTP id r10mr54206183wrs.272.1546879636646; Mon, 07 Jan 2019 08:47:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879636; cv=none; d=google.com; s=arc-20160816; b=g9+HDjpgnVxBlt8zKAlvFCgEOFL9TG26cPMVfwW3AxWhJlj3VTkePZZ/o7gBND8fSr lNrZbtDQLpicWk2w+/FQ+3zGXH2FxI3SNvnnIf4ElYzmoIlm4iESVAZ8Mzp8xvOmnqCo HjkDiZFdlxn8u4eEodjUVGJ1BHlmRLuTvsaplEqO7LaaBa8bv436JVPI7DBHk7cFGxU8 Pq4adr1C1Z+biUkKtimVfHTl5iniLQZIvHEvOYmYOdU5NxVYxEuRDYZ8VM/XS7f1C0HR uUF613Oma6ys9WcsZ6rjBhqIByPaJ0zUoJTT0W+ca3AiZ0Z/JXxW/EExVMSXw5ihysK1 UlCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=abbJ5FA/JUv7csyawQdvW1uyv+APDRlsWcI4Kd6+/U8=; b=xKTnhlcly3Ft/5vtnU8StUXaG8tnhjJKPQ6j1f2nqileJFDHxwIk8uUDAs7t4EywWA rdcqgaxdOGqoaGtWus9AAFyuUdFOY9/EOzAMnKdkFaNNEjqeXApRp3fc0Tqeq6ljhPQn 5DHGZXdXdrdIx7OniMABAXS20Or9BLbrkq2ZcxRMgtJafoXtocZk9gxMzLgKFu9RJhpc P4l3tK8MMFBJ7ukV7pdpvdlDu21Yo/e5giOcIRKjTgLpr9KdVrdl8Lr/jSTAtoXuNdWl 42Bb3+hbcWMvi6nTH2oFqdXRo9NJUg8dZmOFypIhHZa+bPRHdY9jM1W+3bXAKrRBYcle lfSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cBbURGE8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:54 +0000 Message-Id: <20190107163117.16269-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 14/37] gdbstub: add support for vAttach packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Add support for the vAttach packets. In multiprocess mode, GDB sends them to attach to additional processes. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181207090135.7651-13-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 9b6b4d20a02..d80af955cea 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1348,6 +1348,41 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) goto unknown_command; } break; + } else if (strncmp(p, "Attach;", 7) == 0) { + unsigned long pid; + + p += 7; + + if (qemu_strtoul(p, &p, 16, &pid)) { + put_packet(s, "E22"); + break; + } + + process = gdb_get_process(s, pid); + + if (process == NULL) { + put_packet(s, "E22"); + break; + } + + cpu = get_first_cpu_in_process(s, process); + + if (cpu == NULL) { + /* Refuse to attach an empty process */ + put_packet(s, "E22"); + break; + } + + process->attached = true; + + s->g_cpu = cpu; + s->c_cpu = cpu; + + snprintf(buf, sizeof(buf), "T%02xthread:%s;", GDB_SIGNAL_TRAP, + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id))); + + put_packet(s, buf); + break; } else { goto unknown_command; } From patchwork Mon Jan 7 16:30:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154907 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3671426ljp; Mon, 7 Jan 2019 08:35:35 -0800 (PST) X-Google-Smtp-Source: ALg8bN6DtECDSwCOmV/mPuaoDmEjI62a6leIRe1//z8s/7MB+R2DLB5Ky/1GX+ZM63GQGfEyZuBa X-Received: by 2002:a1c:d7d3:: with SMTP id o202mr10045164wmg.135.1546878935827; Mon, 07 Jan 2019 08:35:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546878935; cv=none; d=google.com; s=arc-20160816; b=TI/umZrvlnI1Bfl3i0Uu/8IEZk8XhywA0cKQqKtgrMepcD5c2Csyb2Uaepj+69zMAa Vv8B80fj3suu8o/b9tD6P/jvVBIup0gAWRg7BdiZAHJjhAa9WhVa4WcDwg384LCGKIUU OAif498dTNicL6brouBJmKf4H1gWK/P8r/0qcSMXHYO8DPpGKOpCkws7DeSMPbYQkQ30 IkIHf6toIcZ1iJ97dyneJb0FP1SgyNwBNzAnBbqpFEXoKHbG2HjOV4G+vP602F8Xbf/M vyRUFKopXtx/yzewNhV1sWVR066NDHVkL29vXKVHjTM8Ho11nb/gUg9ONW7d5PwQ6QgV y5Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=u312PotEuQpWHq94BwRphO7NoGBKFDJhyMDW9Wc9sAM=; b=rEvZNnT5KKXcIwLF7yazqNKrF4KXmMXGFbr1SlC+L2J4aUmMhgYvgW/8cxVigDunPq igQGoOrLrfESuUANbmHgnRZRXkfRm/UiknzrfGZPJ9L4grQ5uv4YBruzpTD4WAq+LzWS vKf2xour8k6P+tMFzi6ANvI8scGYl5tanLUNqRjLc49qeseuV1QSxHVq7//IXqKkXxF0 tXmTVoZJT+3/WY/C1SPbizEyMbIy7+CWiRq/p01nyG6Utja6ohZViWC0TQ/ZT/3ljnd1 InjkqvgHjWnGzYnHQHK3aPu3nipmqNKImga4GT6/95Q11K404QGzsfcdRwSP+O+WlZQW xMXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eGZVl4DT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:55 +0000 Message-Id: <20190107163117.16269-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::331 Subject: [Qemu-devel] [PULL 15/37] gdbstub: processes initialization on new peer connection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel When a new connection is established, we set the first process to be attached, and the others detached. The first CPU of the first process is selected as the current CPU. Signed-off-by: Luc Michel Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181207090135.7651-14-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index d80af955cea..432e7d2f7da 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -2267,9 +2267,10 @@ static bool gdb_accept(void) } s = g_malloc0(sizeof(GDBState)); - s->c_cpu = first_cpu; - s->g_cpu = first_cpu; create_default_process(s); + s->processes[0].attached = true; + s->c_cpu = gdb_first_attached_cpu(s); + s->g_cpu = s->c_cpu; s->fd = fd; gdb_has_xml = false; @@ -2355,8 +2356,19 @@ static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size) static void gdb_chr_event(void *opaque, int event) { + int i; + GDBState *s = (GDBState *) opaque; + switch (event) { case CHR_EVENT_OPENED: + /* Start with first process attached, others detached */ + for (i = 0; i < s->process_num; i++) { + s->processes[i].attached = !i; + } + + s->c_cpu = gdb_first_attached_cpu(s); + s->g_cpu = s->c_cpu; + vm_stop(RUN_STATE_PAUSED); gdb_has_xml = false; break; @@ -2546,15 +2558,13 @@ int gdbserver_start(const char *device) memset(s, 0, sizeof(GDBState)); s->mon_chr = mon_chr; } - s->c_cpu = first_cpu; - s->g_cpu = first_cpu; create_processes(s); if (chr) { qemu_chr_fe_init(&s->chr, chr, &error_abort); qemu_chr_fe_set_handlers(&s->chr, gdb_chr_can_receive, gdb_chr_receive, - gdb_chr_event, NULL, NULL, NULL, true); + gdb_chr_event, NULL, s, NULL, true); } s->state = chr ? RS_IDLE : RS_INACTIVE; s->mon_chr = mon_chr; From patchwork Mon Jan 7 16:30:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154922 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3676916ljp; Mon, 7 Jan 2019 08:41:38 -0800 (PST) X-Google-Smtp-Source: ALg8bN5UbADRXNqJaSMFoEaPRXLzTV3tErsSbYbQ6mbzd1Wk0e4OdHjkVfdA6q6v4LhqZrntpdD7 X-Received: by 2002:adf:9422:: with SMTP id 31mr55847562wrq.106.1546879298003; Mon, 07 Jan 2019 08:41:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879297; cv=none; d=google.com; s=arc-20160816; b=JFU5PFfUkQ4QG/P0hzenWUjLwq3kROKLgc3wEP16fP0z25iAnI+RzwvzvvAWrlxRHW oRGq+ySy+0tEnEluZwy2vDu0Zot8qFE8rjvVjTiBhc22zbgW/E8QNGFls+OaZ6tsOhEu jMlQh5F9Mm5CUPu3MyKW+cqhEbKSzbLe6lgYmvRvt9WT8gvxRHEB0TtlJjxLhJrazgRk 0ClkGdr2e9bxdGIe8dnUcEFFAS8yjF7IF7CsLvnqgN3cWYuh0IzjoU1bmR3Luu8owEw3 fisUo98M66yFzOWACzkH5dfrrIwbE3mpPPBgbwoe2XCj2E4agSaRBrdgeG6JkiadUaD7 l+nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=DggtY6HHQ9duEuWdFgn35E494xOLm+nkWBc8Po6gMWI=; b=ZJeju2x3yJxHnoJ65CcuKyV3hmlmGfGR97It9OZ+CsgK5tA4QGk2OxDWoxLBybRJlv GFQzRTPlsRrYqsNfjCOl9rldfjUSMhL9muualUiKMwO2DN5FaLs1wiLBk5yoGgAJ6Je9 A71dzSjsZNBGXIg1Q2q5dVHfZAmwFCqsLRORRIK9dQRTkrVbsifZgfPlSC7ZuG3dBt1s yE2e8gvQRloMFx2AOGfowVaOZe8T386Rf/CfmIsxrYzYx25pdWz2QulLkRqtB8RXWODo X1dvYKKru/117tZZhIWbnHBRWIRiZdhKZAaHqBcm64+ePN3Ss8srbhb47QAcopB9idut 2Nkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DcyYB1mk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.39 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:56 +0000 Message-Id: <20190107163117.16269-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 16/37] gdbstub: gdb_set_stop_cpu: ignore request when process is not attached X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel When gdb_set_stop_cpu() is called with a CPU associated to a process currently not attached by the GDB client, return without modifying the stop CPU. Otherwise, GDB gets confused if it receives packets with a thread-id it does not know about. Signed-off-by: Luc Michel Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-15-luc.michel@greensocs.com [PMM: fix checkpatch comment style nit] Signed-off-by: Peter Maydell --- gdbstub.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 432e7d2f7da..1517563abe1 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1798,6 +1798,16 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) void gdb_set_stop_cpu(CPUState *cpu) { + GDBProcess *p = gdb_get_cpu_process(gdbserver_state, cpu); + + if (!p->attached) { + /* + * Having a stop CPU corresponding to a process that is not attached + * confuses GDB. So we ignore the request. + */ + return; + } + gdbserver_state->c_cpu = cpu; gdbserver_state->g_cpu = cpu; } From patchwork Mon Jan 7 16:30:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154933 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3686359ljp; Mon, 7 Jan 2019 08:52:24 -0800 (PST) X-Google-Smtp-Source: ALg8bN4iTkz6N4iALB2pB6loOx5YDgfn5cIittUjBOrD885lC2U/XBoun4PvHhLaRQBsb/HYSVdC X-Received: by 2002:adf:d089:: with SMTP id y9mr53042659wrh.22.1546879944081; Mon, 07 Jan 2019 08:52:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879944; cv=none; d=google.com; s=arc-20160816; b=JWXqVX8t6x/oeGEkoLlAQA7VYh2sPQqLylQuFvq+RmBLrtR/TpodReHUcyIbmuAZe/ 469lv4Cu1FqBTIsptBWbZp317ZoQYQ4uY+JKH5LbVsD/HzVWmQZ5ThGFirWJKh8dXVj1 Ks1zWsOl1+JZd/FLsVdBJjOs2BRBbejgRmN947UR9AHs7VSjnph6q0qgD7gdXGTvKjEx Um/xvBOKZJxAdTHFaGupKpCcA32hUxvp3bh0Pgp8fwMo2MPs26J6MB3BQQYa28vPqTlo U0FgZ26773u9b6eXAo4Fly+ike6SEkfy2Djklux3waqXiQ7HACv3lQfcvlJhNRwIyY6v Q7lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=dV9FgMcSij0NL5Y8EajzqIS8bpID78HptYmcxeEKzgY=; b=o71apJfdUmStUAF0QGV9trWHF2ImmX1yF+Vx4S883ikNruikVXObvpLkD/xG8kEo4P K+cN6vx3+CmKgHqU1+XvPnwNVRTwMG+QdgZS8mVIYI+wyVuHXy3wyL5+iNWjrTImEtOe tl6+kdAEzasHmd2d+FHZGoTz2yf+rMP14uTvShP9FYBIFN7sTNT5howi41L+cwISjr3p 23MOI8n6Xrj6/w/fgiByhFRAY2qnOpcb7be0EXBUA3nneHLk+oEuQg3lFl6+RhX4KxCh 5SaDOUplzgmfZcCk9Nz3dP4eB2PIVGpOEDSiKeQ81NjgXkE2wACeXo/dGyVuxBGi3GQn oaCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Fc/9bGyA"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.40 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:57 +0000 Message-Id: <20190107163117.16269-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 17/37] gdbstub: add multiprocess extension support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Add multiprocess extension support by enabling multiprocess mode when the peer requests it, and by replying that we actually support it in the qSupported reply packet. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-16-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.19.2 diff --git a/gdbstub.c b/gdbstub.c index 1517563abe1..bfc7afb5096 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1732,6 +1732,12 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) if (cc->gdb_core_xml_file != NULL) { pstrcat(buf, sizeof(buf), ";qXfer:features:read+"); } + + if (strstr(p, "multiprocess+")) { + s->multiprocess = true; + } + pstrcat(buf, sizeof(buf), ";multiprocess+"); + put_packet(s, buf); break; } From patchwork Mon Jan 7 16:30:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154926 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3680424ljp; Mon, 7 Jan 2019 08:45:34 -0800 (PST) X-Google-Smtp-Source: ALg8bN7PglBQP4qrYePEMY2V7MUba1XDp1vyK7v3m941b7WnejGvxNW2rmWUuECwzaunTfYyhTko X-Received: by 2002:a1c:1f83:: with SMTP id f125mr8876790wmf.56.1546879534317; Mon, 07 Jan 2019 08:45:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879534; cv=none; d=google.com; s=arc-20160816; b=yo7QSRfUnqLFqfyR5AlT+kiXtZ8I6KpngPPjPkTEvY/eMUYyuLPIpJ0l3J5YxNwHYY 6Ll8GzIJURyGaV4TZ+SDtFJrPt6/fPKrrP7raKpA1bkiPxNh7NUSQYItudtCtVDznbIy 6OR3TPIdDNBWjiyWk3j7jBpj4+ETuAyHGQSeotreNeiSf6Z+vh9L2eftCpOnYef/gkeJ hJ0LWzStLpV8AVwqEpwNcu1r/howxjjoCkOStuFLw8Dovdv6XsteGeX6pZ1ljjgMsL4z DS62ulstOvzufUJSPO/pbz8BONRqlyfl4VmnjIHgmVdEsZxFvZne1oyAZjuetOucWW5o 3X7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=1Nj4Qd8AQBRrQsNtstFrCaiBGY7evGJTMBUrYASOjQY=; b=Jf1qUKqFG52WWVVQ0cnbvFsO4sCzTP3MlTqVs0KEeH+SyIzzxN14YrxfhEg+1nwzBx ORKruIjqEOPIkofAuHxtP1B02L532dhFhEfebWUVSghi+/3C473EslAIeiXdqB9NSvp2 gbIk/AzBOPlhIVZDyC/1cP5tPFKZT2XRVnfdGVTTMF6PawEA2BxiY+lcBn7EzAxH/dcO 7rX1BAoSB7v/Ic0QBSj+LsxmYmr6BrQTrq56TMtxIrXyjMEQdqh0hlXVx7laPNwE6me4 gW345LW2eZUwxvjrzf+DAL0d0LKQuwAP9i1gEOybK/9OMC4xEqq+EJGMIT7Ya0bO3gYT 5w3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ql5qOs4l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:58 +0000 Message-Id: <20190107163117.16269-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 18/37] arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel Create two separate CPU clusters for APUs and RPUs. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20181207090135.7651-17-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 3 +++ hw/arm/xlnx-zynqmp.c | 23 +++++++++++++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) -- 2.19.2 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 98f925ab84a..591515c7600 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -31,6 +31,7 @@ #include "hw/display/xlnx_dp.h" #include "hw/intc/xlnx-zynqmp-ipi.h" #include "hw/timer/xlnx-zynqmp-rtc.h" +#include "hw/cpu/cluster.h" #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ @@ -77,6 +78,8 @@ typedef struct XlnxZynqMPState { DeviceState parent_obj; /*< public >*/ + CPUClusterState apu_cluster; + CPUClusterState rpu_cluster; ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; GICState gic; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c1950403505..c67ac2e64ac 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -178,12 +178,19 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, int i; int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); + object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, + sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); + + qdev_init_nofail(DEVICE(&s->rpu_cluster)); + for (i = 0; i < num_rpus; i++) { char *name; object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), "cortex-r5f-" TYPE_ARM_CPU); - object_property_add_child(OBJECT(s), "rpu-cpu[*]", + object_property_add_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), &error_abort); name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); @@ -213,10 +220,16 @@ static void xlnx_zynqmp_init(Object *obj) int i; int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + object_initialize_child(obj, "apu-cluster", &s->apu_cluster, + sizeof(s->apu_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + for (i = 0; i < num_apus; i++) { - object_initialize_child(obj, "apu-cpu[*]", &s->apu_cpu[i], - sizeof(s->apu_cpu[i]), - "cortex-a53-" TYPE_ARM_CPU, &error_abort, NULL); + object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", + &s->apu_cpu[i], sizeof(s->apu_cpu[i]), + "cortex-a53-" TYPE_ARM_CPU, &error_abort, + NULL); } sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), @@ -333,6 +346,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", s->virt); + qdev_init_nofail(DEVICE(&s->apu_cluster)); + /* Realize APUs before realizing the GIC. KVM requires this. */ for (i = 0; i < num_apus; i++) { char *name; From patchwork Mon Jan 7 16:30:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154937 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3688576ljp; Mon, 7 Jan 2019 08:55:14 -0800 (PST) X-Google-Smtp-Source: ALg8bN4f+dANl0lvrkcE62DXO6Dbbmo8CIrbvofRzKQsZ8JyNM+qx7rB3+o3+KyGTHaLpB2kS01b X-Received: by 2002:adf:c711:: with SMTP id k17mr50166332wrg.197.1546880114928; Mon, 07 Jan 2019 08:55:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880114; cv=none; d=google.com; s=arc-20160816; b=JF3UULtuG5tEHsCdQjT8GQp0pHMtwIO9CRra14kp0BYG4MgZUaooAafF6CIaKfYfCc pUYkXmfqCMFQB6CQM1q9i/XwYjDYBhkhy+HCPY37/ZR4eM/oBlr9ae+Co9H7qXp8p/Ft JsUN7HRQAlTwTfovbZ3YDkrnLSF/BQlaq5Ed0/vZDsh38PjoSZGbMF0aXwXRNXqNRe8g hS5X6bYUHoK0R4zWsnuUbhc3MXRVyNiFS2Ft9sHaAVR6dd3Wkvh5Gj7h3ADr2BEi+K4t J19OHPTPCa4xuC939ajd/3D+X0svEL4bN8zLSXRiLcn+0l1UdnnGTUDcGNgZJD6uRyvE kNQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AAj13xPTkFQmjBETJwyujJHJPgr2Q5uzYWYEkzn2Pyc=; b=l+mJWr3Dd8ukpUCc9CPWomt9FBVZUPmLBSiBskn3ipPNNk8cIlO+jfruwz66wBoT8+ gFdo4Fzyq2i2BrQSQbq+p2wFYKiygODpMgOSh8A10SPJ/vh8gv+dzs4hObTB8iCEkWgW R15TXJK8Ill6SHrqmEb+CNsFpY1l8Sd5wMk3tfo50ugLCMkwVER8yRufkdYOeCgNKEJp qG+kObaW5gw3W7bS7HIE//d+a7yriX1pOiYF3XDu5xLuSfFthBkGwT85YqHCGWlenINc 1UkJduqzbFhqgmwTuEN661vM5drSXy/9w/d+QuHN6uatKKsDxPK5InKvgSay03Dsq8Hq 373A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jJXiIS8t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:59 +0000 Message-Id: <20190107163117.16269-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 Subject: [Qemu-devel] [PULL 19/37] Revert "armv7m: Guard against no -kernel argument" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Stefan Hajnoczi This reverts commit 01fd41ab3fb69971c24a69ed49cde96086d81278. The generic loader device (-device loader,file=kernel.bin) can be used to load a kernel instead of the -kernel option. Some boards have flash memory (pflash) that is set via the -pflash or -drive options. Allow starting QEMU without the -kernel option to accommodate these scenarios. Suggested-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103144124.18917-1-stefanha@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/armv7m.c | 5 ----- 1 file changed, 5 deletions(-) -- 2.19.2 diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 4bf9131b81e..f4446528307 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -285,11 +285,6 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) big_endian = 0; #endif - if (!kernel_filename && !qtest_enabled()) { - error_report("Guest image must be specified (using -kernel)"); - exit(1); - } - if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { asidx = ARMASIdx_S; } else { From patchwork Mon Jan 7 16:31:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154939 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3692315ljp; Mon, 7 Jan 2019 08:59:37 -0800 (PST) X-Google-Smtp-Source: ALg8bN7GWWhRYL2PZbgfbxKKbZxAx9HoXJkrwpjHTMvJZxST5KxogDLAKoteADtDcDMrhWvzQU2K X-Received: by 2002:a5d:628a:: with SMTP id k10mr13162628wru.254.1546880377719; Mon, 07 Jan 2019 08:59:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880377; cv=none; d=google.com; s=arc-20160816; b=WZMrlpqjdjp4dFiUUYdSecwFWB86rbDg7wmPW7tM7iPIhMgMD/tZcseaZcw1icfWle LZcREBVfJ/EqMQjgKhaqLgulRJ0ZgrUvvJsUjBPN5Mw3P+CB42atXM3aH6iABGN8HBbY z9OHl0Nu70QtbvQpT5/owsOvTDm+oUmznciPx6MzPRQE+bCVu3Kx2kaTkb9XvuIw61ED DFI280spErL+MlYOs92+4TsJEHklpEud//w2D62ecFemVbGd1arqPDQFmi6Yw6r3BTlD Wjctfem65IHaebSwSNszlrMf/P5pT3N4WwBqpyo0MXGDkL0L+vHC27B1eE6Vn5FHXELd wVIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=3EDWJiaFbSIgmkYxpZHI/vzgm7ATTJ6Z/riMYlEZu88=; b=Tdj/mRnAlCFnonHkZEm3ReVMnN4T609It/4WrF5H/ul93C0ceDf/7oyG+iHvU/is/a a9ss4Wu+6eVv3raGnN4BvW3jMRjc35HZQ7ZxsHih3wWNTw8BEr+57f1KlJf7uGN+vgDX Jm84LiNsYhy+S7DL67DBXW6SI+0CRp5B9uzkoraKr5NLIte35FzEIjme+aosZSVSo6Sj DwfXO3Jgbnga+j3KwX0Gy01PhAN1c9OdslkPr/Xqm57s7caaAiuqBNROyMFYYaHFrPWD ptV52WaWTWY8+dzcEJchm5LH527hOs4iPIbC/lje4vdt0UU9rggQF6JgShOOsuex23p9 p7sQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HlQnMkIW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:00 +0000 Message-Id: <20190107163117.16269-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 20/37] hw/arm: versal: Plug memory leaks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Plug a couple of "board creation time" memory leaks. Fixes: 6f16da53ffe4567 ("hw/arm: versal: Add a virtual Xilinx Versal board") Reported-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190104104749.5314-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal-virt.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.19.2 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index c6feeac532f..f95fde2309b 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -130,6 +130,7 @@ static void fdt_add_gic_nodes(VersalVirt *s) 2, MM_GIC_APU_REDIST_0_SIZE); qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); + g_free(nodename); } static void fdt_add_timer_nodes(VersalVirt *s) @@ -364,6 +365,7 @@ static void create_virtio_regions(VersalVirt *s) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion(&s->soc.mr_ps, base, mr); + g_free(name); } for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { From patchwork Mon Jan 7 16:31:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154941 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3696011ljp; Mon, 7 Jan 2019 09:02:57 -0800 (PST) X-Google-Smtp-Source: ALg8bN7YANQ60cMTA9rlNgEW4o+JoMExdjg4LFNTTORunWZhrGoUMeUegUcwcJgo7PSB0uFXch4V X-Received: by 2002:a1c:6e01:: with SMTP id j1mr9122023wmc.103.1546880577175; Mon, 07 Jan 2019 09:02:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880577; cv=none; d=google.com; s=arc-20160816; b=EgBzDgggn0Kw2pPjZBwL7JbxoxSw/Y7qP5TDG4KCV877c0LOun6D5QUJijt0F5tNH7 j4bRiAWnrfGh5BXMClNfN0ZGWOLpMKGQBgU22DXypuk7tGWAYk8WFNLxIPKYesE3rMqM 4O1kTeq3l914J4YnmTnK/gcihyX5jW7Tl39af6TkQZ+VWD/KJcqTNSwO4DWw1uR2yJRa QEZVxBXVDC/KOpS+9rTvjA6wi2H0sLRD1euXisaEf6HHi2beEiGzqwxuLuMPEsXoodt4 BPp/5+TvoHVr50op3bQKByKnerqL8cVN674PlyS9vJzWj7eXsyUQSVZ9O8sA6o5RqE+s k4Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=K6gRcPHJotk1qJugmg0T5V5Ijg7F2u3bPPHU1sURI7A=; b=HWty8i/y1ro8NiUpwbjp9YKy7iRRAea2ei+zzMBte97RCgRFsFHmFeY0nVbdThBo6F /wdSMrTise8vRaRHt6Vk/+kp/v4eS3tQqVPiYt2qDMCO7u5Zac1Xz3gNWZelcx3WLoYi ad7aEJJdWI4qnUtqyTSXPzCscbzeSocI3mQqI3Ml8XnZESMmGn7rzQ/GY41l+2HLEOEP +Us8ajGV0NchbW9tIw0Fp6jHvPHpGLe4pIOoECjWTs5EEGPkwXuHKQP4ZbjAJNLZnUto ryYLPJMgR/32s5/G2OIDMElpFOOaBWyxOjfbgLN6dHlXZeAnFut5Ce1r18HAPKh/yuvJ 8IqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="fk/BVTlD"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:01 +0000 Message-Id: <20190107163117.16269-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 21/37] MAINTAINERS: Add ARM-related files for hw/[misc|input|timer]/ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Thomas Huth Some of the files in hw/input/, hw/misc/ and hw/timer/ are only used by one of the ARM machines, so we can assign these files to the corresponding boards. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 1546433583-18397-1-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell --- MAINTAINERS | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 2.19.2 diff --git a/MAINTAINERS b/MAINTAINERS index 471161742de..0bfd95a4ef7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -515,6 +515,7 @@ F: hw/intc/arm* F: hw/intc/gic_internal.h F: hw/misc/a9scu.c F: hw/misc/arm11scu.c +F: hw/misc/arm_l2x0.c F: hw/timer/a9gtimer* F: hw/timer/arm* F: include/hw/arm/arm*.h @@ -587,6 +588,7 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/integratorcp.c F: hw/misc/arm_integrator_debug.c +F: include/hw/misc/arm_integrator_debug.h MCIMX6UL EVK / i.MX6ul M: Peter Maydell @@ -606,7 +608,9 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/mcimx7d-sabre.c F: hw/arm/fsl-imx7.c +F: hw/misc/imx7_*.c F: include/hw/arm/fsl-imx7.h +F: include/hw/misc/imx7_*.h F: hw/pci-host/designware.c F: include/hw/pci-host/designware.h @@ -640,6 +644,10 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/nseries.c +F: hw/input/lm832x.c +F: hw/input/tsc2005.c +F: hw/misc/cbus.c +F: hw/timer/twl92230.c Palm M: Andrzej Zaborowski @@ -647,6 +655,7 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/palm.c +F: hw/input/tsc210x.c Raspberry Pi M: Peter Maydell @@ -683,6 +692,7 @@ F: hw/display/tc6393xb.c F: hw/gpio/max7310.c F: hw/gpio/zaurus.c F: hw/misc/mst_fpga.c +F: hw/misc/max111x.c F: include/hw/arm/pxa.h F: include/hw/arm/sharpsl.h @@ -693,10 +703,10 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/sabrelite.c F: hw/arm/fsl-imx6.c -F: hw/misc/imx6_src.c +F: hw/misc/imx6_*.c F: hw/ssi/imx_spi.c F: include/hw/arm/fsl-imx6.h -F: include/hw/misc/imx6_src.h +F: include/hw/misc/imx6_*.h F: include/hw/ssi/imx_spi.h Sharp SL-5500 (Collie) PDA @@ -807,7 +817,9 @@ R: Joel Stanley L: qemu-arm@nongnu.org S: Maintained F: hw/*/*aspeed* +F: hw/misc/pca9552.c F: include/hw/*/*aspeed* +F: include/hw/misc/pca9552*.h F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h From patchwork Mon Jan 7 16:31:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154931 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3684983ljp; Mon, 7 Jan 2019 08:50:42 -0800 (PST) X-Google-Smtp-Source: ALg8bN44azSbzoD2kgCdj5Zu8U9GfjkRH7sq4ISLKgj+cYouSYAFk6eUB5sKaQRmt99JrjgEWaDt X-Received: by 2002:a5d:45d0:: with SMTP id b16mr49610442wrs.86.1546879842061; Mon, 07 Jan 2019 08:50:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879842; cv=none; d=google.com; s=arc-20160816; b=yYwytWrb6AhxNHEUibjpQW/rEOAMRStGF6zYcb5cTeFKgdoUvnBTZGgTjVUzJA8/AM qC+B92ugQLjBknWM1S5qUvpU7yqx+pT54hBPLNrcDxE7Ig32+VyfwPt+jnsa/aaqG+7i J3udARbVMFLhhSYGng9ARxvrV59QLWSa4UHwt8zHdwdxdHKny3A0zEbeEKNlevjxMdE1 p9p0HTxoWI3Pqc0JxuTax+Od08tU+nGE+s1KonH8XuybsxxTO3kKCa48iS6Q9a13sMIR Pe4jTVbOOUSnSMyTGFp3UKssoh0wAPdQMV9tyHL5rd6kvH1CVXxaub/6rVF3nNYvD2UD V9XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=TOtzORjw7YC4m6L0fj5Wo5LEgSmQNqLx7l1bWVlv6Zs=; b=AcR4j1voOo2NCN2UjfeZNCXfrhiNP9iToLmNBYY+KTE8siXl1kXiR41e81yTicEzfz 9GdWY7hKkVxveGWo+SYLT64SVBry5XA91YyCHAIOEbd+egw/3dXDswEzqJ2wDjny1vVq p2OiykYxyKQ3LnLmdLgFkYyuISG1Onc81OXkixgJbIckg1jISWbcBufg0AekW2LJKQum HcS2KGYrPBZ/iA0Lo4ZocbU5E3PyzC+sz37ymqsCypToha5f1ROXyKToJD224fn6Nms4 C0YzeuahHm3N6AoZwZJIs0VOp+f18O6buqvSocTUwTTUkY6NF/JW2iMFU0j64mA8KKt8 BzxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OBoSISdh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g5si5633717wma.148.2019.01.07.08.50.41 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:50:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OBoSISdh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:46919 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggY6r-0003Kr-49 for patch@linaro.org; Mon, 07 Jan 2019 11:50:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXod-00053K-25 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoa-0002Bg-Pl for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38747) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoa-00029M-Ep for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:48 -0500 Received: by mail-wr1-x42c.google.com with SMTP id v13so1074532wrw.5 for ; Mon, 07 Jan 2019 08:31:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TOtzORjw7YC4m6L0fj5Wo5LEgSmQNqLx7l1bWVlv6Zs=; b=OBoSISdh8OdMe08k6MDfolscA1raoDNnsZgRiIdvyfMczU2GSKjd6OaOZgu6LgVhmg uYU94Yv/o6gber87zgGPvhY2+c3Qdgd74RZ1yEDdza3kIyEar7zBbrcRsTdM4KirNgu7 NPgDd/saCOJ8UatmBJQNhZejH+WjzmcirMCLM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TOtzORjw7YC4m6L0fj5Wo5LEgSmQNqLx7l1bWVlv6Zs=; b=DJgL0qNOo4X3jvMg7z/JcCgw5UmmLY8sYSYor62IDRLuPA9B0vSrwMUTmijH1scWdw 9sFk/q5WH6oiKZRCE09RB+yMl+nEej1fg1A6BpCavnPUfD8J/hAnqbzAObPLB18X+U+J uT8yXWYWEwTKXv5AMNFr4i8lWehlYF+M2c7EuEP52LXeDUYK8aOU76TLaBDzoBiJhYlv Ra9ddLcUF/tAFjE4DtBx7hgcK7M5WnH+f4+U2EA0m8KKItGhKYBowQQQXCHT4YSBoqvn ymuNqXrQ159HUlaERvrJT1OLoA/MhqmKzi9qEAHS9CsmURdA5MLhbIGD45jPk9+5LJcW SXhw== X-Gm-Message-State: AJcUukfCWTcDXQK0DOd3LLyPyCBHxHyBWztcKj9c1l7vw5RAgWW5pXfX hTLPELS8z8zHpm8WgzvRjjc0wala0kKRuw== X-Received: by 2002:a5d:6450:: with SMTP id d16mr52215154wrw.64.1546878707068; Mon, 07 Jan 2019 08:31:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:02 +0000 Message-Id: <20190107163117.16269-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 22/37] cpus.c: Fix race condition in cpu_stop_current() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We use cpu_stop_current() to ensure the current CPU has stopped from places like qemu_system_reset_request(). Unfortunately its current implementation has a race. It calls qemu_cpu_stop(), which sets cpu->stopped to true even though the CPU hasn't actually stopped yet. The main thread will look at the flags set by qemu_system_reset_request() and call pause_all_vcpus(). pause_all_vcpus() waits for every cpu to have cpu->stopped true, so it can continue (and we will start the system reset operation) before the vcpu thread has got back to its top level loop. Instead, just set cpu->stop and call cpu_exit(). This will cause the vcpu to exit back to the top level loop, and there (as part of the wait_io_event code) it will call qemu_cpu_stop(). This fixes bugs where the reset request appeared to be ignored or the CPU misbehaved because the reset operation started to change vcpu state while the vcpu thread was still using it. Signed-off-by: Peter Maydell Reviewed-by: Emilio G. Cota Tested-by: Jaap Crezee Message-id: 20181207155911.12710-1-peter.maydell@linaro.org --- cpus.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.19.2 diff --git a/cpus.c b/cpus.c index 0ddeeefc14f..b09b7027126 100644 --- a/cpus.c +++ b/cpus.c @@ -2100,7 +2100,8 @@ void qemu_init_vcpu(CPUState *cpu) void cpu_stop_current(void) { if (current_cpu) { - qemu_cpu_stop(current_cpu, true); + current_cpu->stop = true; + cpu_exit(current_cpu); } } From patchwork Mon Jan 7 16:31:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154925 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3679513ljp; Mon, 7 Jan 2019 08:44:36 -0800 (PST) X-Google-Smtp-Source: ALg8bN4L+9cUlnrqTwzYpb4quyVHu4Bb1UAoMAFMpJqIvGYLNZWtXDNz35V5BmruLGPgxqsY8kO1 X-Received: by 2002:a1c:7409:: with SMTP id p9mr9721282wmc.136.1546879476644; Mon, 07 Jan 2019 08:44:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879476; cv=none; d=google.com; s=arc-20160816; b=wPaObB4eMsqWiJSyP7d83nIqjZVGmi7AaQh49oDHxJjXsmnnIiADJdB+QukgsnkpBz bKMWIUTc5FydPCRgaUDFieqNaChPBC+0psYWRgjmDjc6hwv9mJX/t1xHmTy+jJyXTf1I Nxl0HIv9GhG8s+d4MqI6d3DZkYHlx0PSa+UvVtHEYtfRf/5bG5JtpmsbSHiDrWyJu80T Zy65kPUuv+KyWXx2FEvgfAv2UuZAfd8jHpLCUXpSa4eyUjhVkgZTjQv42qGnoliqe1qn FTogU9jhWCguzNqkekQtK6zzyeR+pL+ANKIZuiojd2sQudB1OUrojf2B2rwX0NA11mFx kMvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=soNeqI2oAtZuvZ9bY0TG6Kpl0kFjvNdpLzIG+q3lAxk=; b=wA0/bb3E0MFBEEruDFEsb+uwBTi2WAy2EZGte3gsDdWS58O7lc7YfdAbLC9UUSolfF fh0S2MBmIhRYgw+X5/qKsG7Rz2kikS+ddAu/qLxiK8yDMRoijAcO0KNg5TX+gmjTKTcN 6LtG3r+x1GFPmSOt87Xww+Uo8Ywag7C1ROAWxVd8Hzj28WTfTJuN76nDM01GMCYXLqeQ wsmLNm0mycz+GHaFHwqNZGdUg8VqymMCIffpKYnFoqqp+j+0FItyoFVTjS69awCU/71b 1OKvfiKN3z+GUW0EQHjkhhdOjiQncd2LVTMlFbB4XXKSJRcakNaWkoDc+pGqG0TziguW wmfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G95b6NKc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.47 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:03 +0000 Message-Id: <20190107163117.16269-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 23/37] hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé >From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and: 7. System Control 7.1. Overview A10 embeds a high-speed SRAM which has been split into five segments. See detailed memory mapping in following table: Area Address Size (Bytes) A1 0x00000000-0x00003FFF 16K A2 0x00004000-0x00007FFF 16K A3 0x00008000-0x0000B3FF 13K A4 0x0000B400-0x0000BFFF 3K Since for emulation purpose we don't need the segmentations, we simply define the 'A' area as a single 48KB SRAM. We don't implement the following others areas: - 'B': 'Secure RAM' (64K), - 'C': Debug/ISP SRAM - 'D': USB SRAM (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000bfff (prio 0, ram): sram A 0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl 0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac 0000000001c18000-0000000001c18fff (prio 0, i/o): ahci 0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci 0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic 0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer 0000000001c28000-0000000001c2801f (prio 0, i/o): serial 0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram Reported-by: Charlie Smurthwaite Tested-by: Charlie Smurthwaite Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190104142921.878-1-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-a10.h | 1 + hw/arm/allwinner-a10.c | 6 ++++++ 2 files changed, 7 insertions(+) -- 2.19.2 diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index efb8fc81236..389e128d0fc 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -35,6 +35,7 @@ typedef struct AwA10State { AwA10PICState intc; AwEmacState emac; AllwinnerAHCIState sata; + MemoryRegion sram_a; } AwA10State; #define ALLWINNER_H_ diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 9fe875cdb5e..df0d079ad0a 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -22,6 +22,7 @@ #include "hw/sysbus.h" #include "hw/devices.h" #include "hw/arm/allwinner-a10.h" +#include "hw/misc/unimp.h" static void aw_a10_init(Object *obj) { @@ -85,6 +86,11 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(sysbusdev, 4, s->irq[67]); sysbus_connect_irq(sysbusdev, 5, s->irq[68]); + memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, + &error_fatal); + memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); + create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); + /* FIXME use qdev NIC properties instead of nd_table[] */ if (nd_table[0].used) { qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); From patchwork Mon Jan 7 16:31:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154942 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3699445ljp; Mon, 7 Jan 2019 09:05:54 -0800 (PST) X-Google-Smtp-Source: ALg8bN4NVVzkyhKdRm0nLoT7QYVYKdrA5DcUDfa3QtmB0h3WJzAJWSR6WpqJrp/gHQAptP6w6asK X-Received: by 2002:adf:e44c:: with SMTP id t12mr25354294wrm.89.1546880754620; Mon, 07 Jan 2019 09:05:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880754; cv=none; d=google.com; s=arc-20160816; b=qTfvCRvQMA+M7h7NLkZ7WmBcQfaJYZxGoC16cQDIH/M8pQlyfF6m9X2EZtTa1uhU30 MyuspHAiT0JDEbcbeSRjcocdDS8/6x7PDzcPrSvU7YCJDr9G9lXfV039RgdYfdVTwFWB 8y7cOFS9ONSjBCLOcROh3mfWJTJLTBbgC5JxqC04pngltyUQWmGkdUccD5eBd5Kih2oM 2SRM7U+Swt77NZ5kFq1DDCoFK14Qm+2zyssXCodHGIRibsmtX26ggKvNdQ1G7wkKlMpW Ovt8HFQu9io+H+VOnDU/4eBE9BTKk+I2I8r+aNOoiTzMPygtHGj2wOmKbCJJ/OZX8yBd tLgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ve0B8kcL9xi8WPnq11WzGB1BxRiHUSFLk/M8udS3Wzw=; b=aSEoisaMDKDGT/tsbOAcG4iNnfU2m7iJgi/Le5BVQpLyYGSYhqg7Z+sVFVJ0nnRzbu TCrRRWZjiNI2JQjsSDIR2e+4B26eT3qRQMzw6OVg/sHV4b2S4D2XlsUIgpQFS5THHT0u b4H3NpRMzt+hi5bS1HLu5sTMkBvajZkC1scurDGUciR1a2IVoxWO96wztLSrnG1Tnl5R 2PsvJRhaWyvPLOHwBAxG0oaTih3TJy1UAOVRDkrZNYEWMvv6LM+jTeEbt8UE5WU6lkyO zdBQYM+hwXZvxMOqrZ8T+MMTUl68o8eOtLOZ1Uh28GXyG1uBXq1eJOCYUPpLMA5ynLBV am4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cNGnadji; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.48 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:04 +0000 Message-Id: <20190107163117.16269-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 24/37] qtest: Add set_irq_in command to set IRQ/GPIO level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz Adds a new qtest command "set_irq_in" which allows to set qemu gpio lines to a given level. Based on https://lists.gnu.org/archive/html/qemu-devel/2012-12/msg02363.html which never got merged. Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Thomas Huth Reviewed-by: Laurent Vivier Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-2-stefanha@redhat.com Originally-by: Matthew Ogilvie Reviewed-by: Stefan Hajnoczi Reviewed-by: Thomas Huth Reviewed-by: Laurent Vivier Signed-off-by: Stefan Hajnoczi Signed-off-by: Peter Maydell --- tests/libqtest.h | 13 +++++++++++++ qtest.c | 43 +++++++++++++++++++++++++++++++++++++++++++ tests/libqtest.c | 10 ++++++++++ 3 files changed, 66 insertions(+) -- 2.19.2 diff --git a/tests/libqtest.h b/tests/libqtest.h index 9758c51be61..7ea94139b0c 100644 --- a/tests/libqtest.h +++ b/tests/libqtest.h @@ -230,6 +230,19 @@ void qtest_irq_intercept_in(QTestState *s, const char *string); */ void qtest_irq_intercept_out(QTestState *s, const char *string); +/** + * qtest_set_irq_in: + * @s: QTestState instance to operate on. + * @string: QOM path of a device + * @name: IRQ name + * @irq: IRQ number + * @level: IRQ level + * + * Force given device/irq GPIO-in pin to the given level. + */ +void qtest_set_irq_in(QTestState *s, const char *string, const char *name, + int irq, int level); + /** * qtest_outb: * @s: #QTestState instance to operate on. diff --git a/qtest.c b/qtest.c index 69b9e9962b5..451696b5dae 100644 --- a/qtest.c +++ b/qtest.c @@ -164,6 +164,17 @@ static bool qtest_opened; * where NUM is an IRQ number. For the PC, interrupts can be intercepted * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with * NUM=0 even though it is remapped to GSI 2). + * + * Setting interrupt level: + * + * > set_irq_in QOM-PATH NAME NUM LEVEL + * < OK + * + * where NAME is the name of the irq/gpio list, NUM is an IRQ number and + * LEVEL is an signed integer IRQ level. + * + * Forcibly set the given interrupt pin to the given level. + * */ static int hex2nib(char ch) @@ -326,7 +337,39 @@ static void qtest_process_command(CharBackend *chr, gchar **words) irq_intercept_dev = dev; qtest_send_prefix(chr); qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "set_irq_in") == 0) { + DeviceState *dev; + qemu_irq irq; + char *name; + int ret; + int num; + int level; + g_assert(words[1] && words[2] && words[3] && words[4]); + + dev = DEVICE(object_resolve_path(words[1], NULL)); + if (!dev) { + qtest_send_prefix(chr); + qtest_send(chr, "FAIL Unknown device\n"); + return; + } + + if (strcmp(words[2], "unnamed-gpio-in") == 0) { + name = NULL; + } else { + name = words[2]; + } + + ret = qemu_strtoi(words[3], NULL, 0, &num); + g_assert(!ret); + ret = qemu_strtoi(words[4], NULL, 0, &level); + g_assert(!ret); + + irq = qdev_get_gpio_in_named(dev, name, num); + + qemu_set_irq(irq, level); + qtest_send_prefix(chr); + qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "outb") == 0 || strcmp(words[0], "outw") == 0 || strcmp(words[0], "outl") == 0) { diff --git a/tests/libqtest.c b/tests/libqtest.c index 1d75d3c9363..55750dd68de 100644 --- a/tests/libqtest.c +++ b/tests/libqtest.c @@ -753,6 +753,16 @@ void qtest_irq_intercept_in(QTestState *s, const char *qom_path) qtest_rsp(s, 0); } +void qtest_set_irq_in(QTestState *s, const char *qom_path, const char *name, + int num, int level) +{ + if (!name) { + name = "unnamed-gpio-in"; + } + qtest_sendf(s, "set_irq_in %s %s %d %d\n", qom_path, name, num, level); + qtest_rsp(s, 0); +} + static void qtest_out(QTestState *s, const char *cmd, uint16_t addr, uint32_t value) { qtest_sendf(s, "%s 0x%x 0x%x\n", cmd, addr, value); From patchwork Mon Jan 7 16:31:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154936 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3687418ljp; Mon, 7 Jan 2019 08:53:41 -0800 (PST) X-Google-Smtp-Source: ALg8bN6yAU+fgJd2BR69zNdxK0C7JQC46JzYxwZxltQdSZF1l/UTRS252Lk2cym6n5ksQggDjvkX X-Received: by 2002:a1c:864f:: with SMTP id i76mr9160969wmd.83.1546880021837; Mon, 07 Jan 2019 08:53:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880021; cv=none; d=google.com; s=arc-20160816; b=RMyifCtQkhaldmH0mTDH51/+SuR7+oi9ojsmoJqoGibaeqgxrCGjSpF5pFuf+oWWHM 6vryo2GZcRw1K1yghcUGig2WiHu7NlMkxuD5mDqs31H3uZRQdGIQh+J/BzjopNv4iIbX YUG5Q5T5MtAq1+iqZk0LsKcxdLJbMTESzvhL68kmdg4udWdad+WDSkasi2xkFN9+ybd6 fCkvAjNXmBnaU0PWdXObvclKDuMLNk1JA1U0E2EdgsmwI69qxy5jGh+Gkap08B9CxFuI SMvyrIKs0T29I5iutczNF2MS6iwivP2SowyG3pb95il3Bemk2C+/vcmgNX6Qo7Xqpm25 6IHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aoJhloQbPryNA5qvMLJTb544BXc+pdlFTsnDtd737a0=; b=fctg6g5HULxTliLV2g8rdxC2Ai038ISG9WJQJErN2W14pIQs9m0Lc4bd50I/6X2Ie0 XqvnLV6u/1R3xgJ0pkrwVWTBQ7uTLITe9rN/MulTfRDSGsggySPzJBpRkYoqGiBw7Mio dSPZAeYbF4fWxrGIrBlOVZps8N1RLElDa7mEp8vXy7tVZSiW5ZiABEFj+FCw3m0+8lMR 5go/JIw3vsuMcQFYSSiPMkzpm66keuFFrVh+ybHxZywbN4AATw1kNKUkk1wTq98bkx4/ 1xPbmfiUigSM4oxvivp1H+nO6OICk1IojfIn/wTIS2ZrtiMC6V1msCcIHg2Vr9nSZXJn Gi1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jk4fe1hA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:05 +0000 Message-Id: <20190107163117.16269-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 25/37] arm: Add header to host common definition for nRF51 SOC peripherals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz Adds a header that provides definitions that are used across nRF51 peripherals Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-3-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51.h | 45 ++++++++++++++++++++++++++++++++++++ include/hw/char/nrf51_uart.h | 1 - hw/arm/nrf51_soc.c | 33 ++++++++++---------------- 3 files changed, 57 insertions(+), 22 deletions(-) create mode 100644 include/hw/arm/nrf51.h -- 2.19.2 diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h new file mode 100644 index 00000000000..175bb6c301e --- /dev/null +++ b/include/hw/arm/nrf51.h @@ -0,0 +1,45 @@ +/* + * Nordic Semiconductor nRF51 Series SOC Common Defines + * + * This file hosts generic defines used in various nRF51 peripheral devices. + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen Görtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef NRF51_H +#define NRF51_H + +#define NRF51_FLASH_BASE 0x00000000 +#define NRF51_FICR_BASE 0x10000000 +#define NRF51_FICR_SIZE 0x00000100 +#define NRF51_UICR_BASE 0x10001000 +#define NRF51_SRAM_BASE 0x20000000 + +#define NRF51_IOMEM_BASE 0x40000000 +#define NRF51_IOMEM_SIZE 0x20000000 + +#define NRF51_UART_BASE 0x40002000 +#define NRF51_TIMER_BASE 0x40008000 +#define NRF51_TIMER_SIZE 0x00001000 +#define NRF51_RNG_BASE 0x4000D000 +#define NRF51_NVMC_BASE 0x4001E000 +#define NRF51_GPIO_BASE 0x50000000 + +#define NRF51_PRIVATE_BASE 0xF0000000 +#define NRF51_PRIVATE_SIZE 0x10000000 + +#define NRF51_PAGE_SIZE 1024 + +/* Trigger */ +#define NRF51_TRIGGER_TASK 0x01 + +/* Events */ +#define NRF51_EVENT_CLEAR 0x00 + +#endif diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h index e3ecb7c81c2..eb1c15b490b 100644 --- a/include/hw/char/nrf51_uart.h +++ b/include/hw/char/nrf51_uart.h @@ -16,7 +16,6 @@ #include "hw/registerfields.h" #define UART_FIFO_LENGTH 6 -#define UART_BASE 0x40002000 #define UART_SIZE 0x1000 #define TYPE_NRF51_UART "nrf51_soc.uart" diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index b89c1bdea08..55f8eaafcb0 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -21,27 +21,16 @@ #include "qemu/log.h" #include "cpu.h" +#include "hw/arm/nrf51.h" #include "hw/arm/nrf51_soc.h" -#define IOMEM_BASE 0x40000000 -#define IOMEM_SIZE 0x20000000 - -#define FICR_BASE 0x10000000 -#define FICR_SIZE 0x000000fc - -#define FLASH_BASE 0x00000000 -#define SRAM_BASE 0x20000000 - -#define PRIVATE_BASE 0xF0000000 -#define PRIVATE_SIZE 0x10000000 - /* * The size and base is for the NRF51822 part. If other parts * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * 1024) -#define NRF51822_SRAM_SIZE (16 * 1024) +#define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) +#define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) @@ -76,14 +65,14 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash); memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); if (err) { error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); /* UART */ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); @@ -92,15 +81,17 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) return; } mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); - memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0); + memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, qdev_get_gpio_in(DEVICE(&s->cpu), - BASE_TO_IRQ(UART_BASE))); + BASE_TO_IRQ(NRF51_UART_BASE))); - create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); - create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, + NRF51_IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, + NRF51_FICR_SIZE); create_unimplemented_device("nrf51_soc.private", - PRIVATE_BASE, PRIVATE_SIZE); + NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); } static void nrf51_soc_init(Object *obj) From patchwork Mon Jan 7 16:31:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154943 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3702526ljp; Mon, 7 Jan 2019 09:08:47 -0800 (PST) X-Google-Smtp-Source: ALg8bN7/j12wk+TNbZBTEE2cAONgX5Lnnwwwo4+XAFOfREoT+3XHTvWxNRieb05pc8dwnHGQhC8F X-Received: by 2002:a1c:9cce:: with SMTP id f197mr9345189wme.135.1546880927043; Mon, 07 Jan 2019 09:08:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880927; cv=none; d=google.com; s=arc-20160816; b=fROTUQAJ1+AoMFzhkgQtWdrOx+IYs42JxFI4X6mFnyp1p7NVSZcnjeXhVVPvJU2xbI fpVlrV2OvXknseP4tWYi5I5J369wioQCfC9iO7E4ukYuejp50AW28Y4iGtheDX3Z4sc5 z5B7YD2b+/j9LuG6PltKIQWf/0cajs3ATKNI6VuFVebDMspmx1m6JMb2taikmvGpB0VQ 13d1+fYnthi2gS4QJMtQnWYCcNCHdfPFnTKoRbTHyVbrOuwArU3Bb1J1hVjKin/aBo8H chxrD2A7DnBiiVwE7xQvVLrk7xFPxpk2j03uAr4NQQP+0w5Pkoet09Arx/VQQdFLwqyk KJcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ZG1ERp+/USLfyfNp6gYdXOw0W5fRiZ5jT4xT5OEh+C4=; b=OlT5vib7PZCX2J8qCiyBwkB/zS55n9En1hv1gr+aOLUMkkjazt+zQeMBXi2mHaIHdm X/VP4T8h0OjsRIrQiMcCpb0e1tdqtZJjVa393vsbJNT/IYqSuuUSmXjvLoRf7xxOXVHc poQwzv3Uhqyt2hYDIIDB+fT2CTk/EHGdHhvlZim8tdGQl5tkwR4kVDoq2LfrifKFzn/B BPlhYBeEKYBZiMikRvMLTAWT97Y8arKexMAyQRovDdDAO5HIFYCtvmNJd5Als6anOev3 gKU1AnmwWmLNOrnI45hOV8DgGJasE+wpZQVf6/yR+AnIoSiyzpFGkHeySpOa+hiWAtx+ qwog== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HrwZiG10; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:06 +0000 Message-Id: <20190107163117.16269-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 26/37] hw/misc/nrf51_rng: Add NRF51 random number generator peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz Add a model of the NRF51 random number generator peripheral. This is a simple random generator that continuously generates new random values after startup. Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-4-stefanha@redhat.com Signed-off-by: Peter Maydell --- hw/misc/Makefile.objs | 1 + include/hw/misc/nrf51_rng.h | 83 ++++++++++++ hw/misc/nrf51_rng.c | 262 ++++++++++++++++++++++++++++++++++++ 3 files changed, 346 insertions(+) create mode 100644 include/hw/misc/nrf51_rng.h create mode 100644 hw/misc/nrf51_rng.c -- 2.19.2 diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 680350b3c3b..04f3bfa516e 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -74,3 +74,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o obj-$(CONFIG_AUX) += auxbus.o obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o obj-$(CONFIG_MSF2) += msf2-sysreg.o +obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o diff --git a/include/hw/misc/nrf51_rng.h b/include/hw/misc/nrf51_rng.h new file mode 100644 index 00000000000..3d6bf799977 --- /dev/null +++ b/include/hw/misc/nrf51_rng.h @@ -0,0 +1,83 @@ +/* + * nRF51 Random Number Generator + * + * QEMU interface: + * + Property "period_unfiltered_us": Time between two biased values in + * microseconds. + * + Property "period_filtered_us": Time between two unbiased values in + * microseconds. + * + sysbus MMIO regions 0: Memory Region with tasks, events and registers + * to be mapped to the peripherals instance address by the SOC. + * + Named GPIO output "irq": Interrupt line of the peripheral. Must be + * connected to the associated peripheral interrupt line of the NVIC. + * + Named GPIO output "eep_valrdy": Event set when new random value is ready + * to be read. + * + Named GPIO input "tep_start": Task that triggers start of continuous + * generation of random values. + * + Named GPIO input "tep_stop": Task that ends continuous generation of + * random values. + * + * Accuracy of the peripheral model: + * + Stochastic properties of different configurations of the random source + * are not modeled. + * + Generation of unfiltered and filtered random values take at least the + * average generation time stated in the production specification; + * non-deterministic generation times are not modeled. + * + * Copyright 2018 Steffen Görtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_RNG_H +#define NRF51_RNG_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#define TYPE_NRF51_RNG "nrf51_soc.rng" +#define NRF51_RNG(obj) OBJECT_CHECK(NRF51RNGState, (obj), TYPE_NRF51_RNG) + +#define NRF51_RNG_SIZE 0x1000 + +#define NRF51_RNG_TASK_START 0x000 +#define NRF51_RNG_TASK_STOP 0x004 +#define NRF51_RNG_EVENT_VALRDY 0x100 +#define NRF51_RNG_REG_SHORTS 0x200 +#define NRF51_RNG_REG_SHORTS_VALRDY_STOP 0 +#define NRF51_RNG_REG_INTEN 0x300 +#define NRF51_RNG_REG_INTEN_VALRDY 0 +#define NRF51_RNG_REG_INTENSET 0x304 +#define NRF51_RNG_REG_INTENCLR 0x308 +#define NRF51_RNG_REG_CONFIG 0x504 +#define NRF51_RNG_REG_CONFIG_DECEN 0 +#define NRF51_RNG_REG_VALUE 0x508 + +typedef struct { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + /* Event End Points */ + qemu_irq eep_valrdy; + + QEMUTimer timer; + + /* Time between generation of successive unfiltered values in us */ + uint16_t period_unfiltered_us; + /* Time between generation of successive filtered values in us */ + uint16_t period_filtered_us; + + uint8_t value; + + uint32_t active; + uint32_t event_valrdy; + uint32_t shortcut_stop_on_valrdy; + uint32_t interrupt_enabled; + uint32_t filter_enabled; + +} NRF51RNGState; + + +#endif /* NRF51_RNG_H_ */ diff --git a/hw/misc/nrf51_rng.c b/hw/misc/nrf51_rng.c new file mode 100644 index 00000000000..d188f044f4c --- /dev/null +++ b/hw/misc/nrf51_rng.c @@ -0,0 +1,262 @@ +/* + * nRF51 Random Number Generator + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * + * Copyright 2018 Steffen Görtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/arm/nrf51.h" +#include "hw/misc/nrf51_rng.h" +#include "crypto/random.h" + +static void update_irq(NRF51RNGState *s) +{ + bool irq = s->interrupt_enabled && s->event_valrdy; + qemu_set_irq(s->irq, irq); +} + +static uint64_t rng_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + uint64_t r = 0; + + switch (offset) { + case NRF51_RNG_EVENT_VALRDY: + r = s->event_valrdy; + break; + case NRF51_RNG_REG_SHORTS: + r = s->shortcut_stop_on_valrdy; + break; + case NRF51_RNG_REG_INTEN: + case NRF51_RNG_REG_INTENSET: + case NRF51_RNG_REG_INTENCLR: + r = s->interrupt_enabled; + break; + case NRF51_RNG_REG_CONFIG: + r = s->filter_enabled; + break; + case NRF51_RNG_REG_VALUE: + r = s->value; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + return r; +} + +static int64_t calc_next_timeout(NRF51RNGState *s) +{ + int64_t timeout = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL); + if (s->filter_enabled) { + timeout += s->period_filtered_us; + } else { + timeout += s->period_unfiltered_us; + } + + return timeout; +} + + +static void rng_update_timer(NRF51RNGState *s) +{ + if (s->active) { + timer_mod(&s->timer, calc_next_timeout(s)); + } else { + timer_del(&s->timer); + } +} + + +static void rng_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + + switch (offset) { + case NRF51_RNG_TASK_START: + if (value == NRF51_TRIGGER_TASK) { + s->active = 1; + rng_update_timer(s); + } + break; + case NRF51_RNG_TASK_STOP: + if (value == NRF51_TRIGGER_TASK) { + s->active = 0; + rng_update_timer(s); + } + break; + case NRF51_RNG_EVENT_VALRDY: + if (value == NRF51_EVENT_CLEAR) { + s->event_valrdy = 0; + } + break; + case NRF51_RNG_REG_SHORTS: + s->shortcut_stop_on_valrdy = + (value & BIT_MASK(NRF51_RNG_REG_SHORTS_VALRDY_STOP)) ? 1 : 0; + break; + case NRF51_RNG_REG_INTEN: + s->interrupt_enabled = + (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) ? 1 : 0; + break; + case NRF51_RNG_REG_INTENSET: + if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) { + s->interrupt_enabled = 1; + } + break; + case NRF51_RNG_REG_INTENCLR: + if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) { + s->interrupt_enabled = 0; + } + break; + case NRF51_RNG_REG_CONFIG: + s->filter_enabled = + (value & BIT_MASK(NRF51_RNG_REG_CONFIG_DECEN)) ? 1 : 0; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_irq(s); +} + +static const MemoryRegionOps rng_ops = { + .read = rng_read, + .write = rng_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4 +}; + +static void nrf51_rng_timer_expire(void *opaque) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + + qcrypto_random_bytes(&s->value, 1, &error_abort); + + s->event_valrdy = 1; + qemu_set_irq(s->eep_valrdy, 1); + + if (s->shortcut_stop_on_valrdy) { + s->active = 0; + } + + rng_update_timer(s); + update_irq(s); +} + +static void nrf51_rng_tep_start(void *opaque, int n, int level) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + + if (level) { + s->active = 1; + rng_update_timer(s); + } +} + +static void nrf51_rng_tep_stop(void *opaque, int n, int level) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + + if (level) { + s->active = 0; + rng_update_timer(s); + } +} + + +static void nrf51_rng_init(Object *obj) +{ + NRF51RNGState *s = NRF51_RNG(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mmio, obj, &rng_ops, s, + TYPE_NRF51_RNG, NRF51_RNG_SIZE); + sysbus_init_mmio(sbd, &s->mmio); + + timer_init_us(&s->timer, QEMU_CLOCK_VIRTUAL, nrf51_rng_timer_expire, s); + + sysbus_init_irq(sbd, &s->irq); + + /* Tasks */ + qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_start, "tep_start", 1); + qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_stop, "tep_stop", 1); + + /* Events */ + qdev_init_gpio_out_named(DEVICE(s), &s->eep_valrdy, "eep_valrdy", 1); +} + +static void nrf51_rng_reset(DeviceState *dev) +{ + NRF51RNGState *s = NRF51_RNG(dev); + + s->value = 0; + s->active = 0; + s->event_valrdy = 0; + s->shortcut_stop_on_valrdy = 0; + s->interrupt_enabled = 0; + s->filter_enabled = 0; + + rng_update_timer(s); +} + + +static Property nrf51_rng_properties[] = { + DEFINE_PROP_UINT16("period_unfiltered_us", NRF51RNGState, + period_unfiltered_us, 167), + DEFINE_PROP_UINT16("period_filtered_us", NRF51RNGState, + period_filtered_us, 660), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_rng = { + .name = "nrf51_soc.rng", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(active, NRF51RNGState), + VMSTATE_UINT32(event_valrdy, NRF51RNGState), + VMSTATE_UINT32(shortcut_stop_on_valrdy, NRF51RNGState), + VMSTATE_UINT32(interrupt_enabled, NRF51RNGState), + VMSTATE_UINT32(filter_enabled, NRF51RNGState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_rng_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = nrf51_rng_properties; + dc->vmsd = &vmstate_rng; + dc->reset = nrf51_rng_reset; +} + +static const TypeInfo nrf51_rng_info = { + .name = TYPE_NRF51_RNG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51RNGState), + .instance_init = nrf51_rng_init, + .class_init = nrf51_rng_class_init +}; + +static void nrf51_rng_register_types(void) +{ + type_register_static(&nrf51_rng_info); +} + +type_init(nrf51_rng_register_types) From patchwork Mon Jan 7 16:31:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154932 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3685414ljp; Mon, 7 Jan 2019 08:51:11 -0800 (PST) X-Google-Smtp-Source: ALg8bN6KEKl5e2y4WMp8GlN5OApLxVg1EbYcCDI6pz9Gwo3K128FnAAlLMnjLrtf6Gx3IT1oANft X-Received: by 2002:a1c:8d12:: with SMTP id p18mr10156577wmd.31.1546879871642; Mon, 07 Jan 2019 08:51:11 -0800 (PST) ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:07 +0000 Message-Id: <20190107163117.16269-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c Subject: [Qemu-devel] [PULL 27/37] arm: Instantiate NRF51 random number generator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz Use RNG in SOC. Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-5-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 2 ++ hw/arm/nrf51_soc.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) -- 2.19.2 diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 73fc92e9a8d..9e3ba916bd0 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -13,6 +13,7 @@ #include "hw/sysbus.h" #include "hw/arm/armv7m.h" #include "hw/char/nrf51_uart.h" +#include "hw/misc/nrf51_rng.h" #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ @@ -26,6 +27,7 @@ typedef struct NRF51State { ARMv7MState cpu; NRF51UARTState uart; + NRF51RNGState rng; MemoryRegion iomem; MemoryRegion sram; diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 55f8eaafcb0..d2a19b8eadd 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -86,6 +86,19 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_UART_BASE))); + /* RNG */ + object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(NRF51_RNG_BASE))); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -110,6 +123,9 @@ static void nrf51_soc_init(Object *obj) TYPE_NRF51_UART); object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", &error_abort); + + sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), + TYPE_NRF51_RNG); } static Property nrf51_soc_properties[] = { From patchwork Mon Jan 7 16:31:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154938 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3689361ljp; Mon, 7 Jan 2019 08:56:12 -0800 (PST) X-Google-Smtp-Source: ALg8bN7b7fujJJBi2uGLgRPp7yboR/6D8Zy22utRUg6ujx7krqCbnEFwer/YbW/cP8/QV6YFncnJ X-Received: by 2002:a1c:4108:: with SMTP id o8mr9011358wma.91.1546880172172; Mon, 07 Jan 2019 08:56:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880172; cv=none; d=google.com; s=arc-20160816; b=ovho9hukfxwhvdJDArTufFbV2bxG8E9/Ra2l08jGJpfNbsehpUxOj3B5Dy/J8FzmIA 1V5Gf51egzYBNNaYABfRHTT37heyYkw+b/WDfAYpP1dt4tO71jCexmjUlFLXZuoO+meE RL8O4rHWNUzwVXNSVbpjwsiDFdox3Ld4Sg7ymOudbGpOcemYKg5vwPaAKIno2w7kdzZ6 w6gzwgXqq9h9ddJqDTgHHde1OYQtXaY3iCD9LU/TJ2Bs4x3GkGcX93g514DItSl8zIzE Xu6iw+IYbSm2phcZPS+zLa71lEHVBe+FqeoD+UYOdVMJZ8/2IsZMQBzKOhBU1W4op1YF TQLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=K4G4en5CZrdXfv5pe8Z+g+gS1rF1AOdP0MUzboLucIE=; b=MowKUNwPRsUQj31OmQMOiDPt/koCv/1tEA3ZEbadCMNqT51xih1Fvu6lsTxOoQ96tc LAFCh5SaMsPGgGkGVtxRThcszZfF+RJMaj35jcqaZPwsMS9oIUUuIkooWwEqcKad+VWV A4dlU9madOMjoGLypHA0qV944gHvQZkvpcXzLkscQeVUD3GaHuGE7BMghqKLqq3HiO0v BTeGMu+z0TOw8IMRly6VS2WvIaTc3wA9fJXnfQr/HiykNl+OMtNC4pUdQ6lrvOO8osc/ eGPD2HZJo042EvVbJgmqpIcpqiKGD1e5UetrVXj3q1b7vC7Eqv9lqcUz59XOcQbOv6pX Z3eg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=T0IzQMaL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.53 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:08 +0000 Message-Id: <20190107163117.16269-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 28/37] hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz This adds a model of the nRF51 GPIO peripheral. Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf The nRF51 series microcontrollers support up to 32 GPIO pins in various configurations. The pins can be used as input pins with pull-ups or pull-down. Furthermore, three different output driver modes per level are available (disconnected, standard, high-current). The GPIO-Peripheral has a mechanism for detecting level changes which is not featured in this model. Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-6-stefanha@redhat.com Signed-off-by: Peter Maydell --- Makefile.objs | 1 + hw/gpio/Makefile.objs | 1 + include/hw/gpio/nrf51_gpio.h | 69 ++++++++ hw/gpio/nrf51_gpio.c | 300 +++++++++++++++++++++++++++++++++++ hw/gpio/trace-events | 7 + 5 files changed, 378 insertions(+) create mode 100644 include/hw/gpio/nrf51_gpio.h create mode 100644 hw/gpio/nrf51_gpio.c create mode 100644 hw/gpio/trace-events -- 2.19.2 diff --git a/Makefile.objs b/Makefile.objs index bc5b8a8442f..456115992a4 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -184,6 +184,7 @@ trace-events-subdirs += hw/vfio trace-events-subdirs += hw/virtio trace-events-subdirs += hw/watchdog trace-events-subdirs += hw/xen +trace-events-subdirs += hw/gpio trace-events-subdirs += io trace-events-subdirs += linux-user trace-events-subdirs += migration diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs index fa0a72e6d0c..e5da0cb54fe 100644 --- a/hw/gpio/Makefile.objs +++ b/hw/gpio/Makefile.objs @@ -8,3 +8,4 @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o obj-$(CONFIG_OMAP) += omap_gpio.o obj-$(CONFIG_IMX) += imx_gpio.o obj-$(CONFIG_RASPI) += bcm2835_gpio.o +obj-$(CONFIG_NRF51_SOC) += nrf51_gpio.o diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h new file mode 100644 index 00000000000..337ee534bbc --- /dev/null +++ b/include/hw/gpio/nrf51_gpio.h @@ -0,0 +1,69 @@ +/* + * nRF51 System-on-Chip general purpose input/output register definition + * + * QEMU interface: + * + sysbus MMIO regions 0: GPIO registers + * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin. + * Level -1: Externally Disconnected/Floating; Pull-up/down will be regarded + * Level 0: Input externally driven LOW + * Level 1: Input externally driven HIGH + * + Unnamed GPIO outputs 0-31: + * Level -1: Disconnected/Floating + * Level 0: Driven LOW + * Level 1: Driven HIGH + * + * Accuracy of the peripheral model: + * + The nRF51 GPIO output driver supports two modes, standard and high-current + * mode. These different drive modes are not modeled and handled the same. + * + Pin SENSEing is not modeled/implemented. + * + * Copyright 2018 Steffen Görtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_GPIO_H +#define NRF51_GPIO_H + +#include "hw/sysbus.h" +#define TYPE_NRF51_GPIO "nrf51_soc.gpio" +#define NRF51_GPIO(obj) OBJECT_CHECK(NRF51GPIOState, (obj), TYPE_NRF51_GPIO) + +#define NRF51_GPIO_PINS 32 + +#define NRF51_GPIO_SIZE 0x1000 + +#define NRF51_GPIO_REG_OUT 0x504 +#define NRF51_GPIO_REG_OUTSET 0x508 +#define NRF51_GPIO_REG_OUTCLR 0x50C +#define NRF51_GPIO_REG_IN 0x510 +#define NRF51_GPIO_REG_DIR 0x514 +#define NRF51_GPIO_REG_DIRSET 0x518 +#define NRF51_GPIO_REG_DIRCLR 0x51C +#define NRF51_GPIO_REG_CNF_START 0x700 +#define NRF51_GPIO_REG_CNF_END 0x77F + +#define NRF51_GPIO_PULLDOWN 1 +#define NRF51_GPIO_PULLUP 3 + +typedef struct NRF51GPIOState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + uint32_t out; + uint32_t in; + uint32_t in_mask; + uint32_t dir; + uint32_t cnf[NRF51_GPIO_PINS]; + + uint32_t old_out; + uint32_t old_out_connected; + + qemu_irq output[NRF51_GPIO_PINS]; +} NRF51GPIOState; + + +#endif diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c new file mode 100644 index 00000000000..86e047d649f --- /dev/null +++ b/hw/gpio/nrf51_gpio.c @@ -0,0 +1,300 @@ +/* + * nRF51 System-on-Chip general purpose input/output register definition + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen Görtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/gpio/nrf51_gpio.h" +#include "trace.h" + +/* + * Check if the output driver is connected to the direction switch + * given the current configuration and logic level. + * It is not differentiated between standard and "high"(-power) drive modes. + */ +static bool is_connected(uint32_t config, uint32_t level) +{ + bool state; + uint32_t drive_config = extract32(config, 8, 3); + + switch (drive_config) { + case 0 ... 3: + state = true; + break; + case 4 ... 5: + state = level != 0; + break; + case 6 ... 7: + state = level == 0; + break; + default: + g_assert_not_reached(); + break; + } + + return state; +} + +static void update_output_irq(NRF51GPIOState *s, size_t i, + bool connected, bool level) +{ + int64_t irq_level = connected ? level : -1; + bool old_connected = extract32(s->old_out_connected, i, 1); + bool old_level = extract32(s->old_out, i, 1); + + if ((old_connected != connected) || (old_level != level)) { + qemu_set_irq(s->output[i], irq_level); + trace_nrf51_gpio_update_output_irq(i, irq_level); + } + + s->old_out = deposit32(s->old_out, i, 1, level); + s->old_out_connected = deposit32(s->old_out_connected, i, 1, connected); +} + +static void update_state(NRF51GPIOState *s) +{ + uint32_t pull; + size_t i; + bool connected_out, dir, connected_in, out, input; + + for (i = 0; i < NRF51_GPIO_PINS; i++) { + pull = extract32(s->cnf[i], 2, 2); + dir = extract32(s->cnf[i], 0, 1); + connected_in = extract32(s->in_mask, i, 1); + out = extract32(s->out, i, 1); + input = !extract32(s->cnf[i], 1, 1); + connected_out = is_connected(s->cnf[i], out) && dir; + + update_output_irq(s, i, connected_out, out); + + /* Pin both driven externally and internally */ + if (connected_out && connected_in) { + qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i); + } + + /* + * Input buffer disconnected from internal/external drives, so + * pull-up/pull-down becomes relevant + */ + if (!input || (input && !connected_in && !connected_out)) { + if (pull == NRF51_GPIO_PULLDOWN) { + s->in = deposit32(s->in, i, 1, 0); + } else if (pull == NRF51_GPIO_PULLUP) { + s->in = deposit32(s->in, i, 1, 1); + } + } + + /* Self stimulation through internal output driver */ + if (connected_out && !connected_in && input) { + s->in = deposit32(s->in, i, 1, out); + } + } + +} + +/* + * Direction is exposed in both the DIR register and the DIR bit + * of each PINs CNF configuration register. Reflect bits for pins in DIR + * to individual pin configuration registers. + */ +static void reflect_dir_bit_in_cnf(NRF51GPIOState *s) +{ + size_t i; + + uint32_t value = s->dir; + + for (i = 0; i < NRF51_GPIO_PINS; i++) { + s->cnf[i] = (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01); + } +} + +static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51GPIOState *s = NRF51_GPIO(opaque); + uint64_t r = 0; + size_t idx; + + switch (offset) { + case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR: + r = s->out; + break; + + case NRF51_GPIO_REG_IN: + r = s->in; + break; + + case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR: + r = s->dir; + break; + + case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: + idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; + r = s->cnf[idx]; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + trace_nrf51_gpio_read(offset, r); + + return r; +} + +static void nrf51_gpio_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51GPIOState *s = NRF51_GPIO(opaque); + size_t idx; + + trace_nrf51_gpio_write(offset, value); + + switch (offset) { + case NRF51_GPIO_REG_OUT: + s->out = value; + break; + + case NRF51_GPIO_REG_OUTSET: + s->out |= value; + break; + + case NRF51_GPIO_REG_OUTCLR: + s->out &= ~value; + break; + + case NRF51_GPIO_REG_DIR: + s->dir = value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_DIRSET: + s->dir |= value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_DIRCLR: + s->dir &= ~value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: + idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; + s->cnf[idx] = value; + /* + * direction is exposed in both the DIR register and the DIR bit + * of each PINs CNF configuration register. + */ + s->dir = (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_state(s); +} + +static const MemoryRegionOps gpio_ops = { + .read = nrf51_gpio_read, + .write = nrf51_gpio_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, +}; + +static void nrf51_gpio_set(void *opaque, int line, int value) +{ + NRF51GPIOState *s = NRF51_GPIO(opaque); + + trace_nrf51_gpio_set(line, value); + + assert(line >= 0 && line < NRF51_GPIO_PINS); + + s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); + if (value >= 0) { + s->in = deposit32(s->in, line, 1, value != 0); + } + + update_state(s); +} + +static void nrf51_gpio_reset(DeviceState *dev) +{ + NRF51GPIOState *s = NRF51_GPIO(dev); + size_t i; + + s->out = 0; + s->old_out = 0; + s->old_out_connected = 0; + s->in = 0; + s->in_mask = 0; + s->dir = 0; + + for (i = 0; i < NRF51_GPIO_PINS; i++) { + s->cnf[i] = 0x00000002; + } +} + +static const VMStateDescription vmstate_nrf51_gpio = { + .name = TYPE_NRF51_GPIO, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(out, NRF51GPIOState), + VMSTATE_UINT32(in, NRF51GPIOState), + VMSTATE_UINT32(in_mask, NRF51GPIOState), + VMSTATE_UINT32(dir, NRF51GPIOState), + VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS), + VMSTATE_UINT32(old_out, NRF51GPIOState), + VMSTATE_UINT32(old_out_connected, NRF51GPIOState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_gpio_init(Object *obj) +{ + NRF51GPIOState *s = NRF51_GPIO(obj); + + memory_region_init_io(&s->mmio, obj, &gpio_ops, s, + TYPE_NRF51_GPIO, NRF51_GPIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS); + qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS); +} + +static void nrf51_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_nrf51_gpio; + dc->reset = nrf51_gpio_reset; + dc->desc = "nRF51 GPIO"; +} + +static const TypeInfo nrf51_gpio_info = { + .name = TYPE_NRF51_GPIO, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51GPIOState), + .instance_init = nrf51_gpio_init, + .class_init = nrf51_gpio_class_init +}; + +static void nrf51_gpio_register_types(void) +{ + type_register_static(&nrf51_gpio_info); +} + +type_init(nrf51_gpio_register_types) diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events new file mode 100644 index 00000000000..cb41a897569 --- /dev/null +++ b/hw/gpio/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/gpio/nrf51_gpio.c +nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 +nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 +nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 +nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 \ No newline at end of file From patchwork Mon Jan 7 16:31:09 2019 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.54 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:09 +0000 Message-Id: <20190107163117.16269-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 29/37] arm: Instantiate NRF51 general purpose I/O X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz Instantiates GPIO peripheral model Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-7-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 2 ++ hw/arm/nrf51_soc.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) -- 2.19.2 diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 9e3ba916bd0..84e0278881b 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -14,6 +14,7 @@ #include "hw/arm/armv7m.h" #include "hw/char/nrf51_uart.h" #include "hw/misc/nrf51_rng.h" +#include "hw/gpio/nrf51_gpio.h" #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ @@ -28,6 +29,7 @@ typedef struct NRF51State { NRF51UARTState uart; NRF51RNGState rng; + NRF51GPIOState gpio; MemoryRegion iomem; MemoryRegion sram; diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index d2a19b8eadd..db817fe5064 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -99,6 +99,19 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_RNG_BASE))); + /* GPIO */ + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); + + /* Pass all GPIOs to the SOC layer so they are available to the board */ + qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -126,6 +139,9 @@ static void nrf51_soc_init(Object *obj) sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), TYPE_NRF51_RNG); + + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), + TYPE_NRF51_GPIO); } static Property nrf51_soc_properties[] = { From patchwork Mon Jan 7 16:31:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154919 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3675114ljp; Mon, 7 Jan 2019 08:39:37 -0800 (PST) X-Google-Smtp-Source: ALg8bN7nwV3n7MywDg/GvKBka+7CDnLhIxNa+7ZpKH0hotogugsMgfbqPpBnjnbMyVNeR9cBdSPL X-Received: by 2002:a1c:a9d4:: with SMTP id s203mr9059693wme.132.1546879177737; Mon, 07 Jan 2019 08:39:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879177; cv=none; d=google.com; s=arc-20160816; b=Vu1z6xrNws6MUwwgimA9S8wmuRSB6AvnnL91eAZJfs6WRSYUxQ+PFK3zL32dmmVIMA k+VZIMfBdch7sSjniMgwi5svtu87RoXPPveM8Ot5mQnS8jjk8Nc/5qyK0y1uJb9tKQPA OevxxRxMEVqzYqN3/wSyK59SiCQ4f2/dQeE5HNsfJB8bwBLrPKzwZr7baiPGew9QtWSs 7Din7cHFIH7dTPsl5tV7irqZx+3VZ+9wOgyQB460q6Q301FYhnRwFF2P+Q13yOKyKX9J sGAZGVZCCiKtxQfNksrElH6X/O3GbTFAZ5qihIqUqnZGy92scKGyOPU83s0PneUL407i c5UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=pFFnt0PGN+JXnIxcfblwupVgdtnANwbtO3wSuWa/d4k=; b=dFk/9xwgfaA1zyRx/elQbzZ+Z0TusojE7pYYrHSapYzibt4vc6k1O8EePCRMgXJLdG uR8zr9k02GR6a0i4VnXbml7BUqWUCUktmQtewoqGgbwNLHiNfwq9WblKXgVbvLH4Ikrl v02TTOZKhrmfQDg2NZ/PQhKhYDO2MryzVILcf2oIZ9XGl1yfbTC3kIpgUzQtufJ14nRb HRamoYjd/ys2keYJVOiAW+E/apiqrJCA03PVAFbABb+Y75QYTaI5cw9MZLv+oFCWE3jF GTkBygETAw2g3ZIcdKNNIh13TORzi8fuARC/bfUGtF8rqv6KKwwp8UqKgNJnId0Qz0b8 Zfkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GdeLa6j1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:10 +0000 Message-Id: <20190107163117.16269-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 30/37] tests/microbit-test: Add Tests for nRF51 GPIO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz The test suite for the nRF51 GPIO peripheral for now only tests initial state. Additionally a set of tests testing an implementation detail of the model are included. Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-8-stefanha@redhat.com [PMM: fixed stray space at start of file] Signed-off-by: Peter Maydell --- tests/Makefile.include | 2 + tests/microbit-test.c | 160 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 162 insertions(+) create mode 100644 tests/microbit-test.c -- 2.19.2 diff --git a/tests/Makefile.include b/tests/Makefile.include index 3f5a1d0c308..9c84bbd8296 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -277,6 +277,7 @@ check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF) check-qtest-arm-y += tests/tmp105-test$(EXESUF) check-qtest-arm-y += tests/pca9552-test$(EXESUF) check-qtest-arm-y += tests/ds1338-test$(EXESUF) +check-qtest-arm-y += tests/microbit-test$(EXESUF) check-qtest-arm-y += tests/m25p80-test$(EXESUF) check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF) @@ -708,6 +709,7 @@ tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y) tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/microbit-test$(EXESUF): tests/microbit-test.o tests/m25p80-test$(EXESUF): tests/m25p80-test.o tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) diff --git a/tests/microbit-test.c b/tests/microbit-test.c new file mode 100644 index 00000000000..f0a180cbc6f --- /dev/null +++ b/tests/microbit-test.c @@ -0,0 +1,160 @@ +/* + * QTest testcase for Microbit board using the Nordic Semiconductor nRF51 SoC. + * + * nRF51: + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Microbit Board: http://microbit.org/ + * + * Copyright 2018 Steffen Görtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + + +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "libqtest.h" + +#include "hw/arm/nrf51.h" +#include "hw/gpio/nrf51_gpio.h" + +static void test_nrf51_gpio(void) +{ + size_t i; + uint32_t actual, expected; + + struct { + hwaddr addr; + uint32_t expected; + } const reset_state[] = { + {NRF51_GPIO_REG_OUT, 0x00000000}, {NRF51_GPIO_REG_OUTSET, 0x00000000}, + {NRF51_GPIO_REG_OUTCLR, 0x00000000}, {NRF51_GPIO_REG_IN, 0x00000000}, + {NRF51_GPIO_REG_DIR, 0x00000000}, {NRF51_GPIO_REG_DIRSET, 0x00000000}, + {NRF51_GPIO_REG_DIRCLR, 0x00000000} + }; + + /* Check reset state */ + for (i = 0; i < ARRAY_SIZE(reset_state); i++) { + expected = reset_state[i].expected; + actual = readl(NRF51_GPIO_BASE + reset_state[i].addr); + g_assert_cmpuint(actual, ==, expected); + } + + for (i = 0; i < NRF51_GPIO_PINS; i++) { + expected = 0x00000002; + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START + i * 4); + g_assert_cmpuint(actual, ==, expected); + } + + /* Check dir bit consistency between dir and cnf */ + /* Check set via DIRSET */ + expected = 0x80000001; + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRSET, expected); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, ==, expected); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + + /* Check clear via DIRCLR */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRCLR, 0x80000001); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, ==, 0x00000000); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + + /* Check set via DIR */ + expected = 0x80000001; + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, expected); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, ==, expected); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + + /* Reset DIR */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, 0x00000000); + + /* Check Input propagates */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x00); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 0); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 1); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, -1); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + + /* Check pull-up working */ + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 0); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b1110); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + + /* Check pull-down working */ + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 1); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0110); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, -1); + + /* Check Output propagates */ + irq_intercept_out("/machine/nrf51"); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0011); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + g_assert_true(get_irq(0)); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + g_assert_false(get_irq(0)); + + /* Check self-stimulation */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + + /* + * Check short-circuit - generates an guest_error which must be checked + * manually as long as qtest can not scan qemu_log messages + */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 0); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + global_qtest = qtest_initf("-machine microbit"); + + qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); + + ret = g_test_run(); + + qtest_quit(global_qtest); + return ret; +} From patchwork Mon Jan 7 16:31:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154944 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3703120ljp; Mon, 7 Jan 2019 09:09:20 -0800 (PST) X-Google-Smtp-Source: ALg8bN7IQ3TpXDvcEr9BgOVpUpw0t3LvPUlL7nMqj9Ci32JFkKZkGyreNtIDoi/RX0lyfZaNegG6 X-Received: by 2002:adf:ec83:: with SMTP id z3mr53336578wrn.264.1546880960558; Mon, 07 Jan 2019 09:09:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880960; cv=none; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:11 +0000 Message-Id: <20190107163117.16269-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 Subject: [Qemu-devel] [PULL 31/37] hw/timer/nrf51_timer: Add nRF51 Timer peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz This patch adds the model for the nRF51 timer peripheral. Currently, only the TIMER mode is implemented. Signed-off-by: Steffen Görtz Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-9-stefanha@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/Makefile.objs | 1 + include/hw/timer/nrf51_timer.h | 80 +++++++ hw/timer/nrf51_timer.c | 393 +++++++++++++++++++++++++++++++++ hw/timer/trace-events | 5 + 4 files changed, 479 insertions(+) create mode 100644 include/hw/timer/nrf51_timer.h create mode 100644 hw/timer/nrf51_timer.c -- 2.19.2 diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index b32194d153d..0e9a4530f84 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -23,6 +23,7 @@ common-obj-$(CONFIG_IMX) += imx_gpt.o common-obj-$(CONFIG_LM32) += lm32_timer.o common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o +common-obj-$(CONFIG_NRF51_SOC) += nrf51_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h new file mode 100644 index 00000000000..85cad2300df --- /dev/null +++ b/include/hw/timer/nrf51_timer.h @@ -0,0 +1,80 @@ +/* + * nRF51 System-on-Chip Timer peripheral + * + * QEMU interface: + * + sysbus MMIO regions 0: GPIO registers + * + sysbus irq + * + * Copyright 2018 Steffen Görtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ +#ifndef NRF51_TIMER_H +#define NRF51_TIMER_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#define TYPE_NRF51_TIMER "nrf51_soc.timer" +#define NRF51_TIMER(obj) OBJECT_CHECK(NRF51TimerState, (obj), TYPE_NRF51_TIMER) + +#define NRF51_TIMER_REG_COUNT 4 + +#define NRF51_TIMER_TASK_START 0x000 +#define NRF51_TIMER_TASK_STOP 0x004 +#define NRF51_TIMER_TASK_COUNT 0x008 +#define NRF51_TIMER_TASK_CLEAR 0x00C +#define NRF51_TIMER_TASK_SHUTDOWN 0x010 +#define NRF51_TIMER_TASK_CAPTURE_0 0x040 +#define NRF51_TIMER_TASK_CAPTURE_3 0x04C + +#define NRF51_TIMER_EVENT_COMPARE_0 0x140 +#define NRF51_TIMER_EVENT_COMPARE_1 0x144 +#define NRF51_TIMER_EVENT_COMPARE_2 0x148 +#define NRF51_TIMER_EVENT_COMPARE_3 0x14C + +#define NRF51_TIMER_REG_SHORTS 0x200 +#define NRF51_TIMER_REG_SHORTS_MASK 0xf0f +#define NRF51_TIMER_REG_INTENSET 0x304 +#define NRF51_TIMER_REG_INTENCLR 0x308 +#define NRF51_TIMER_REG_INTEN_MASK 0xf0000 +#define NRF51_TIMER_REG_MODE 0x504 +#define NRF51_TIMER_REG_MODE_MASK 0x01 +#define NRF51_TIMER_TIMER 0 +#define NRF51_TIMER_COUNTER 1 +#define NRF51_TIMER_REG_BITMODE 0x508 +#define NRF51_TIMER_REG_BITMODE_MASK 0x03 +#define NRF51_TIMER_WIDTH_16 0 +#define NRF51_TIMER_WIDTH_8 1 +#define NRF51_TIMER_WIDTH_24 2 +#define NRF51_TIMER_WIDTH_32 3 +#define NRF51_TIMER_REG_PRESCALER 0x510 +#define NRF51_TIMER_REG_PRESCALER_MASK 0x0F +#define NRF51_TIMER_REG_CC0 0x540 +#define NRF51_TIMER_REG_CC3 0x54C + +typedef struct NRF51TimerState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + + QEMUTimer timer; + int64_t timer_start_ns; + int64_t update_counter_ns; + uint32_t counter; + + bool running; + + uint8_t events_compare[NRF51_TIMER_REG_COUNT]; + uint32_t cc[NRF51_TIMER_REG_COUNT]; + uint32_t shorts; + uint32_t inten; + uint32_t mode; + uint32_t bitmode; + uint32_t prescaler; + +} NRF51TimerState; + + +#endif diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c new file mode 100644 index 00000000000..0c90662896e --- /dev/null +++ b/hw/timer/nrf51_timer.c @@ -0,0 +1,393 @@ +/* + * nRF51 System-on-Chip Timer peripheral + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen Görtz + * Copyright (c) 2019 Red Hat, Inc. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/arm/nrf51.h" +#include "hw/timer/nrf51_timer.h" +#include "trace.h" + +#define TIMER_CLK_FREQ 16000000UL + +static uint32_t const bitwidths[] = {16, 8, 24, 32}; + +static uint32_t ns_to_ticks(NRF51TimerState *s, int64_t ns) +{ + uint32_t freq = TIMER_CLK_FREQ >> s->prescaler; + + return muldiv64(ns, freq, NANOSECONDS_PER_SECOND); +} + +static int64_t ticks_to_ns(NRF51TimerState *s, uint32_t ticks) +{ + uint32_t freq = TIMER_CLK_FREQ >> s->prescaler; + + return muldiv64(ticks, NANOSECONDS_PER_SECOND, freq); +} + +/* Returns number of ticks since last call */ +static uint32_t update_counter(NRF51TimerState *s, int64_t now) +{ + uint32_t ticks = ns_to_ticks(s, now - s->update_counter_ns); + + s->counter = (s->counter + ticks) % BIT(bitwidths[s->bitmode]); + s->update_counter_ns = now; + return ticks; +} + +/* Assumes s->counter is up-to-date */ +static void rearm_timer(NRF51TimerState *s, int64_t now) +{ + int64_t min_ns = INT64_MAX; + size_t i; + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + int64_t delta_ns; + + if (s->events_compare[i]) { + continue; /* already expired, ignore it for now */ + } + + if (s->cc[i] <= s->counter) { + delta_ns = ticks_to_ns(s, BIT(bitwidths[s->bitmode]) - + s->counter + s->cc[i]); + } else { + delta_ns = ticks_to_ns(s, s->cc[i] - s->counter); + } + + if (delta_ns < min_ns) { + min_ns = delta_ns; + } + } + + if (min_ns != INT64_MAX) { + timer_mod_ns(&s->timer, now + min_ns); + } +} + +static void update_irq(NRF51TimerState *s) +{ + bool flag = false; + size_t i; + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + flag |= s->events_compare[i] && extract32(s->inten, 16 + i, 1); + } + qemu_set_irq(s->irq, flag); +} + +static void timer_expire(void *opaque) +{ + NRF51TimerState *s = NRF51_TIMER(opaque); + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint32_t cc_remaining[NRF51_TIMER_REG_COUNT]; + bool should_stop = false; + uint32_t ticks; + size_t i; + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (s->cc[i] > s->counter) { + cc_remaining[i] = s->cc[i] - s->counter; + } else { + cc_remaining[i] = BIT(bitwidths[s->bitmode]) - + s->counter + s->cc[i]; + } + } + + ticks = update_counter(s, now); + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (cc_remaining[i] <= ticks) { + s->events_compare[i] = 1; + + if (s->shorts & BIT(i)) { + s->timer_start_ns = now; + s->update_counter_ns = s->timer_start_ns; + s->counter = 0; + } + + should_stop |= s->shorts & BIT(i + 8); + } + } + + update_irq(s); + + if (should_stop) { + s->running = false; + timer_del(&s->timer); + } else { + rearm_timer(s, now); + } +} + +static void counter_compare(NRF51TimerState *s) +{ + uint32_t counter = s->counter; + size_t i; + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (counter == s->cc[i]) { + s->events_compare[i] = 1; + + if (s->shorts & BIT(i)) { + s->counter = 0; + } + } + } +} + +static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51TimerState *s = NRF51_TIMER(opaque); + uint64_t r = 0; + + switch (offset) { + case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3: + r = s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4]; + break; + case NRF51_TIMER_REG_SHORTS: + r = s->shorts; + break; + case NRF51_TIMER_REG_INTENSET: + r = s->inten; + break; + case NRF51_TIMER_REG_INTENCLR: + r = s->inten; + break; + case NRF51_TIMER_REG_MODE: + r = s->mode; + break; + case NRF51_TIMER_REG_BITMODE: + r = s->bitmode; + break; + case NRF51_TIMER_REG_PRESCALER: + r = s->prescaler; + break; + case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3: + r = s->cc[(offset - NRF51_TIMER_REG_CC0) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + trace_nrf51_timer_read(offset, r, size); + + return r; +} + +static void nrf51_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51TimerState *s = NRF51_TIMER(opaque); + uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + size_t idx; + + trace_nrf51_timer_write(offset, value, size); + + switch (offset) { + case NRF51_TIMER_TASK_START: + if (value == NRF51_TRIGGER_TASK && s->mode == NRF51_TIMER_TIMER) { + s->running = true; + s->timer_start_ns = now - ticks_to_ns(s, s->counter); + s->update_counter_ns = s->timer_start_ns; + rearm_timer(s, now); + } + break; + case NRF51_TIMER_TASK_STOP: + case NRF51_TIMER_TASK_SHUTDOWN: + if (value == NRF51_TRIGGER_TASK) { + s->running = false; + timer_del(&s->timer); + } + break; + case NRF51_TIMER_TASK_COUNT: + if (value == NRF51_TRIGGER_TASK && s->mode == NRF51_TIMER_COUNTER) { + s->counter = (s->counter + 1) % BIT(bitwidths[s->bitmode]); + counter_compare(s); + } + break; + case NRF51_TIMER_TASK_CLEAR: + if (value == NRF51_TRIGGER_TASK) { + s->timer_start_ns = now; + s->update_counter_ns = s->timer_start_ns; + s->counter = 0; + if (s->running) { + rearm_timer(s, now); + } + } + break; + case NRF51_TIMER_TASK_CAPTURE_0 ... NRF51_TIMER_TASK_CAPTURE_3: + if (value == NRF51_TRIGGER_TASK) { + if (s->running) { + timer_expire(s); /* update counter and all state */ + } + + idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4; + s->cc[idx] = s->counter; + } + break; + case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3: + if (value == NRF51_EVENT_CLEAR) { + s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4] = 0; + + if (s->running) { + timer_expire(s); /* update counter and all state */ + } + } + break; + case NRF51_TIMER_REG_SHORTS: + s->shorts = value & NRF51_TIMER_REG_SHORTS_MASK; + break; + case NRF51_TIMER_REG_INTENSET: + s->inten |= value & NRF51_TIMER_REG_INTEN_MASK; + break; + case NRF51_TIMER_REG_INTENCLR: + s->inten &= ~(value & NRF51_TIMER_REG_INTEN_MASK); + break; + case NRF51_TIMER_REG_MODE: + s->mode = value; + break; + case NRF51_TIMER_REG_BITMODE: + if (s->mode == NRF51_TIMER_TIMER && s->running) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: erroneous change of BITMODE while timer is running\n", + __func__); + } + s->bitmode = value & NRF51_TIMER_REG_BITMODE_MASK; + break; + case NRF51_TIMER_REG_PRESCALER: + if (s->mode == NRF51_TIMER_TIMER && s->running) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: erroneous change of PRESCALER while timer is running\n", + __func__); + } + s->prescaler = value & NRF51_TIMER_REG_PRESCALER_MASK; + break; + case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3: + if (s->running) { + timer_expire(s); /* update counter */ + } + + idx = (offset - NRF51_TIMER_REG_CC0) / 4; + s->cc[idx] = value % BIT(bitwidths[s->bitmode]); + + if (s->running) { + rearm_timer(s, now); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_irq(s); +} + +static const MemoryRegionOps rng_ops = { + .read = nrf51_timer_read, + .write = nrf51_timer_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, +}; + +static void nrf51_timer_init(Object *obj) +{ + NRF51TimerState *s = NRF51_TIMER(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &rng_ops, s, + TYPE_NRF51_TIMER, NRF51_TIMER_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + + timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, timer_expire, s); +} + +static void nrf51_timer_reset(DeviceState *dev) +{ + NRF51TimerState *s = NRF51_TIMER(dev); + + timer_del(&s->timer); + s->timer_start_ns = 0x00; + s->update_counter_ns = 0x00; + s->counter = 0x00; + s->running = false; + + memset(s->events_compare, 0x00, sizeof(s->events_compare)); + memset(s->cc, 0x00, sizeof(s->cc)); + + s->shorts = 0x00; + s->inten = 0x00; + s->mode = 0x00; + s->bitmode = 0x00; + s->prescaler = 0x00; +} + +static int nrf51_timer_post_load(void *opaque, int version_id) +{ + NRF51TimerState *s = NRF51_TIMER(opaque); + + if (s->running && s->mode == NRF51_TIMER_TIMER) { + timer_expire(s); + } + return 0; +} + +static const VMStateDescription vmstate_nrf51_timer = { + .name = TYPE_NRF51_TIMER, + .version_id = 1, + .post_load = nrf51_timer_post_load, + .fields = (VMStateField[]) { + VMSTATE_TIMER(timer, NRF51TimerState), + VMSTATE_INT64(timer_start_ns, NRF51TimerState), + VMSTATE_INT64(update_counter_ns, NRF51TimerState), + VMSTATE_UINT32(counter, NRF51TimerState), + VMSTATE_BOOL(running, NRF51TimerState), + VMSTATE_UINT8_ARRAY(events_compare, NRF51TimerState, + NRF51_TIMER_REG_COUNT), + VMSTATE_UINT32_ARRAY(cc, NRF51TimerState, NRF51_TIMER_REG_COUNT), + VMSTATE_UINT32(shorts, NRF51TimerState), + VMSTATE_UINT32(inten, NRF51TimerState), + VMSTATE_UINT32(mode, NRF51TimerState), + VMSTATE_UINT32(bitmode, NRF51TimerState), + VMSTATE_UINT32(prescaler, NRF51TimerState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = nrf51_timer_reset; + dc->vmsd = &vmstate_nrf51_timer; +} + +static const TypeInfo nrf51_timer_info = { + .name = TYPE_NRF51_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51TimerState), + .instance_init = nrf51_timer_init, + .class_init = nrf51_timer_class_init +}; + +static void nrf51_timer_register_types(void) +{ + type_register_static(&nrf51_timer_info); +} + +type_init(nrf51_timer_register_types) diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 75bd3b1042a..0144a68951c 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -72,3 +72,8 @@ sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value # hw/timer/xlnx-zynqmp-rtc.c xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" + +# hw/timer/nrf51_timer.c +nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" + From patchwork Mon Jan 7 16:31:12 2019 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:12 +0000 Message-Id: <20190107163117.16269-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 32/37] arm: Instantiate NRF51 Timers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz Instantiates TIMER0 - TIMER2 Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-10-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 4 ++++ hw/arm/nrf51_soc.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) -- 2.19.2 diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 84e0278881b..39e613e1c97 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -15,11 +15,14 @@ #include "hw/char/nrf51_uart.h" #include "hw/misc/nrf51_rng.h" #include "hw/gpio/nrf51_gpio.h" +#include "hw/timer/nrf51_timer.h" #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) +#define NRF51_NUM_TIMERS 3 + typedef struct NRF51State { /*< private >*/ SysBusDevice parent_obj; @@ -30,6 +33,7 @@ typedef struct NRF51State { NRF51UARTState uart; NRF51RNGState rng; NRF51GPIOState gpio; + NRF51TimerState timer[NRF51_NUM_TIMERS]; MemoryRegion iomem; MemoryRegion sram; diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index db817fe5064..ef70bd62fa4 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -39,6 +39,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) NRF51State *s = NRF51_SOC(dev_soc); MemoryRegion *mr; Error *err = NULL; + uint8_t i = 0; + hwaddr base_addr = 0; if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -112,6 +114,22 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) /* Pass all GPIOs to the SOC layer so they are available to the board */ qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); + /* TIMER */ + for (i = 0; i < NRF51_NUM_TIMERS; i++) { + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(base_addr))); + } + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -122,6 +140,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) static void nrf51_soc_init(Object *obj) { + uint8_t i = 0; + NRF51State *s = NRF51_SOC(obj); memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); @@ -142,6 +162,12 @@ static void nrf51_soc_init(Object *obj) sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), TYPE_NRF51_GPIO); + + for (i = 0; i < NRF51_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_NRF51_TIMER); + + } } static Property nrf51_soc_properties[] = { From patchwork Mon Jan 7 16:31:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154930 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3684646ljp; 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X-Received-From: 2a00:1450:4864:20::433 Subject: [Qemu-devel] [PULL 33/37] tests/microbit-test: Add Tests for nRF51 Timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz Basic tests for nRF51 Timer Peripheral. Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-11-stefanha@redhat.com Signed-off-by: Peter Maydell --- tests/microbit-test.c | 95 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) -- 2.19.2 diff --git a/tests/microbit-test.c b/tests/microbit-test.c index f0a180cbc6f..0c125535f64 100644 --- a/tests/microbit-test.c +++ b/tests/microbit-test.c @@ -20,6 +20,7 @@ #include "hw/arm/nrf51.h" #include "hw/gpio/nrf51_gpio.h" +#include "hw/timer/nrf51_timer.h" static void test_nrf51_gpio(void) { @@ -143,6 +144,99 @@ static void test_nrf51_gpio(void) qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 0); } +static void timer_task(hwaddr task) +{ + writel(NRF51_TIMER_BASE + task, NRF51_TRIGGER_TASK); +} + +static void timer_clear_event(hwaddr event) +{ + writel(NRF51_TIMER_BASE + event, NRF51_EVENT_CLEAR); +} + +static void timer_set_bitmode(uint8_t mode) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_BITMODE, mode); +} + +static void timer_set_prescaler(uint8_t prescaler) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_PRESCALER, prescaler); +} + +static void timer_set_cc(size_t idx, uint32_t value) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_CC0 + idx * 4, value); +} + +static void timer_assert_events(uint32_t ev0, uint32_t ev1, uint32_t ev2, + uint32_t ev3) +{ + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_0) == ev0); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_1) == ev1); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_2) == ev2); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_3) == ev3); +} + +static void test_nrf51_timer(void) +{ + uint32_t steps_to_overflow = 408; + + /* Compare Match */ + timer_task(NRF51_TIMER_TASK_STOP); + timer_task(NRF51_TIMER_TASK_CLEAR); + + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_0); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_1); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_2); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_3); + + timer_set_bitmode(NRF51_TIMER_WIDTH_16); /* 16 MHz Timer */ + timer_set_prescaler(0); + /* Swept over in first step */ + timer_set_cc(0, 2); + /* Barely miss on first step */ + timer_set_cc(1, 162); + /* Spot on on third step */ + timer_set_cc(2, 480); + + timer_assert_events(0, 0, 0, 0); + + timer_task(NRF51_TIMER_TASK_START); + clock_step(10000); + timer_assert_events(1, 0, 0, 0); + + /* Swept over on first overflow */ + timer_set_cc(3, 114); + + clock_step(10000); + timer_assert_events(1, 1, 0, 0); + + clock_step(10000); + timer_assert_events(1, 1, 1, 0); + + /* Wrap time until internal counter overflows */ + while (steps_to_overflow--) { + timer_assert_events(1, 1, 1, 0); + clock_step(10000); + } + + timer_assert_events(1, 1, 1, 1); + + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_0); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_1); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_2); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_3); + timer_assert_events(0, 0, 0, 0); + + timer_task(NRF51_TIMER_TASK_STOP); + + /* Test Proposal: Stop/Shutdown */ + /* Test Proposal: Shortcut Compare -> Clear */ + /* Test Proposal: Shortcut Compare -> Stop */ + /* Test Proposal: Counter Mode */ +} + int main(int argc, char **argv) { int ret; @@ -152,6 +246,7 @@ int main(int argc, char **argv) global_qtest = qtest_initf("-machine microbit"); qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); + qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); ret = g_test_run(); From patchwork Mon Jan 7 16:31:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154935 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3686815ljp; Mon, 7 Jan 2019 08:52:55 -0800 (PST) X-Google-Smtp-Source: ALg8bN5/5HztEbZq+zfZNwM+mIQQoBGmIRy6YdwcwUNV2wXDp6+421mX3M7Wo5EhXfl6Bq/NkotP X-Received: by 2002:adf:82f1:: with SMTP id 104mr55073181wrc.131.1546879975397; Mon, 07 Jan 2019 08:52:55 -0800 (PST) ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:14 +0000 Message-Id: <20190107163117.16269-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 34/37] arm: Add Clock peripheral stub to NRF51 SOC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Steffen Görtz This stubs enables the microbit-micropython firmware to run on the microbit machine. Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-12-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 1 + hw/arm/nrf51_soc.c | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+) -- 2.19.2 diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 39e613e1c97..e06f0304b48 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -38,6 +38,7 @@ typedef struct NRF51State { MemoryRegion iomem; MemoryRegion sram; MemoryRegion flash; + MemoryRegion clock; uint32_t sram_size; uint32_t flash_size; diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index ef70bd62fa4..1630c275940 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -34,6 +34,26 @@ #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) +static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", + __func__, addr, size); + return 1; +} + +static void clock_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", + __func__, addr, data, size); +} + +static const MemoryRegionOps clock_ops = { + .read = clock_read, + .write = clock_write +}; + + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s = NRF51_SOC(dev_soc); @@ -130,6 +150,12 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) BASE_TO_IRQ(base_addr))); } + /* STUB Peripherals */ + memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, + "nrf51_soc.clock", 0x1000); + memory_region_add_subregion_overlap(&s->container, + NRF51_IOMEM_BASE, &s->clock, -1); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, From patchwork Mon Jan 7 16:31:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154924 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3677806ljp; Mon, 7 Jan 2019 08:42:36 -0800 (PST) X-Google-Smtp-Source: ALg8bN4Ae6ah51SFFJampPOqFw/nNOswF/tgsvBicS6vH80uda1ILfMpCht9zzQ3oLAEEuc8d2q8 X-Received: by 2002:adf:ea81:: with SMTP id s1mr50529500wrm.309.1546879356564; Mon, 07 Jan 2019 08:42:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546879356; cv=none; d=google.com; s=arc-20160816; b=pe9S2PaoEG7IbRTiN75Ps5Mt00K/gyUhnKoemUxg3nAtnXsuh+pzGlaQ8P75xZ5r9u x2E2zwjo/IFQ6SDlt1XbEAHGqioJ/nKFGGrPQD/TRmec0gwqU1kACKuOHWg8xJm+0a39 3hYNXgSFe9NDCecLja3/b6xltH0ZpWWabLC8d8H0/CQ3V+h/qSnGInJ+oD9g2/os9Tuy 0Ejz1rS0GmUuOK0wRmJn5L8E8mMCMXnTapXXYx4RwEbG0+3HWNklhUD0NcUoE+q9YzgH NX7wW5/YagGulyWFb5t/IzWUfX/cw+jOA2LvVqHASlTmGY9J/C5wsqU2cya7MuzHale7 icRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4t2j3JlI3wCS/gpNiHag2Gqqa/xd788Q4yu+HY0+oFg=; b=PX00dUhV6q0ve7fABUWdxirj49QAM/WYiyUqUYcR+va+nfjMMXYvy2D7nRPEnNW7Y4 vX8yJFEnG6gVoNTLeCS6xl1dPSm1tyE7UeVa7XFmtBEd3s389wJ7wPym5I5ZYM5NXUyg Csm6f3wDi2Lz5WrC1T+KGvYA2xa5Ycz5TqxdJIH7Mlzw3jeymHv1PgjCOW745ma+ETJI I9XH70wJDROYx3vQ77vp/WMRrDBVRDGVtII+p0lDgnms0uoJIgP9jtM6IvVG2HkSTpvH XqGFPlCrJG/lj5Vkj4KyJQ+51OX8h5dx5Z8ASop0uppw6E2epE4rlajpsctLRiPa02lW C0/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=S2dKX0rG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:15 +0000 Message-Id: <20190107163117.16269-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 35/37] target/arm: Emit barriers for A32/T32 load-acquire/store-release insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that MTTCG is here, the comment in the 32-bit Arm decoder that "Since the emulation does not have barriers, the acquire/release semantics need no special handling" is no longer true. Emit the correct barriers for the load-acquire/store-release insns, as we already do in the A64 decoder. Signed-off-by: Peter Maydell Tested-by: Alex Bennée Reviewed-by: Alex Bennée --- target/arm/translate.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/target/arm/translate.c b/target/arm/translate.c index ed3db0c3946..66cf28c8cbe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9733,6 +9733,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) rd = (insn >> 12) & 0xf; if (insn & (1 << 23)) { /* load/store exclusive */ + bool is_ld = extract32(insn, 20, 1); + bool is_lasr = !extract32(insn, 8, 1); int op2 = (insn >> 8) & 3; op1 = (insn >> 21) & 0x3; @@ -9760,11 +9762,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) addr = tcg_temp_local_new_i32(); load_reg_var(s, addr, rn); - /* Since the emulation does not have barriers, - the acquire/release semantics need no special - handling */ + if (is_lasr && !is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + if (op2 == 0) { - if (insn & (1 << 20)) { + if (is_ld) { tmp = tcg_temp_new_i32(); switch (op1) { case 0: /* lda */ @@ -9810,7 +9813,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } tcg_temp_free_i32(tmp); } - } else if (insn & (1 << 20)) { + } else if (is_ld) { switch (op1) { case 0: /* ldrex */ gen_load_exclusive(s, rd, 15, addr, 2); @@ -9847,6 +9850,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } tcg_temp_free_i32(addr); + + if (is_lasr && is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } } else if ((insn & 0x00300f00) == 0) { /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx * - SWP, SWPB @@ -10862,6 +10869,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_gen_addi_i32(tmp, tmp, s->pc); store_reg(s, 15, tmp); } else { + bool is_lasr = false; + bool is_ld = extract32(insn, 20, 1); int op2 = (insn >> 6) & 0x3; op = (insn >> 4) & 0x3; switch (op2) { @@ -10883,12 +10892,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 3: /* Load-acquire/store-release exclusive */ ARCH(8); + is_lasr = true; break; } + + if (is_lasr && !is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + addr = tcg_temp_local_new_i32(); load_reg_var(s, addr, rn); if (!(op2 & 1)) { - if (insn & (1 << 20)) { + if (is_ld) { tmp = tcg_temp_new_i32(); switch (op) { case 0: /* ldab */ @@ -10927,12 +10942,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } tcg_temp_free_i32(tmp); } - } else if (insn & (1 << 20)) { + } else if (is_ld) { gen_load_exclusive(s, rs, rd, addr, op); } else { gen_store_exclusive(s, rm, rs, rd, addr, op); } tcg_temp_free_i32(addr); + + if (is_lasr && is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } } } else { /* Load/store multiple, RFE, SRS. */ From patchwork Mon Jan 7 16:31:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154940 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3693401ljp; Mon, 7 Jan 2019 09:00:43 -0800 (PST) X-Google-Smtp-Source: ALg8bN5iTQHJTMhg87swXUrP4UFLm/OH45IMTT7fg4oCcQGRiEvFsek52B2eL36wYKmpyVHsT8mM X-Received: by 2002:a1c:1b8d:: with SMTP id b135mr9372749wmb.115.1546880443290; Mon, 07 Jan 2019 09:00:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546880443; cv=none; d=google.com; s=arc-20160816; b=nREFOrrlqb07aDAEfC5LKdQxz7JtQvdAH2wOa0CdybiZA6mAzujgBSXEMttu4XU8WJ 87SW2p6QSp5ENrXiKcq0fXBS+XCcS1Pq20VPw4ql5KQfquRR6nfBkMljh049o7jWWLlH 9Q72be+bxCLdc446lF90q/PzWjkM9nVjYWGMn9OxhrgQa4GICzn0i1Sdok3qtiF8smEm obO7N8NoSeemmTh5W7lmWZNpyKxwnN9JHv0mtQj/b61sR+jcegB77/IzqlPsy4udbHrB b8gzu0ER4eV45Cy8pnEIKBufXAkXp6YTYyVpsdFI1HWNX6dxMwSd6xiC+/VPpYm4vt2o 6wGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=sV9hC86VR1BwwXtur8ugDHh5zaLnT6kGUvr9DsHA44A=; b=HgbT+o9xg2WmXMeIt/jjI37HBv7xAKOsft8yjlt5hPbO67py6tlGwvGRofo1l1eSS1 tlVDbCLEit+u7AgZFa5TQn71DDBsIyRg0fpodpgbQSFllAwZaUelNUTedARLC4CMm5jx vyLs5mmAVw8Tx216fLS5eNGe6O+BcnkJZ826rqG4Gl5b0oHika2Kll5K8qR0gBxQumTC xKSK673AUKJFr+0lpB75JDmuxjVXYfw7lx8pVxQGAAtvE7UuU0C6wqb8WLw0k+6r690V zokCZI75j+570vkRsJCO1C3bzUjMVLrTLDnB5vq+VrYnG3GP0ama/zWU+L1wBz3XVu+L 9Dlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="MRmnZ7//"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:16 +0000 Message-Id: <20190107163117.16269-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 36/37] hw/misc/tz-mpc: Fix value of BLK_MAX register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the TZ Memory Protection Controller, the BLK_MAX register is supposed to return the maximum permitted value of the BLK_IDX register. Our implementation incorrectly returned max+1 (ie the total number of valid index values, since BLK_IDX is zero-based). Correct this off-by-one error. Since we consistently initialize and use s->blk_max throughout the implementation as the 'size' of the LUT, just adjust the value we return when the guest reads the BLK_MAX register, rather than trying to change the semantics of the s->blk_max internal struct field. Fixes: https://bugs.launchpad.net/qemu/+bug/1806824 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181213183249.3468-1-peter.maydell@linaro.org --- hw/misc/tz-mpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.19.2 diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index fb48a1540b9..9a84be75ed6 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -150,7 +150,7 @@ static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr, r = s->ctrl; break; case A_BLK_MAX: - r = s->blk_max; + r = s->blk_max - 1; break; case A_BLK_CFG: /* We are never in "init in progress state", so this just indicates From patchwork Mon Jan 7 16:31:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154945 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3706232ljp; Mon, 7 Jan 2019 09:12:09 -0800 (PST) X-Google-Smtp-Source: ALg8bN75ezaEG1jZ3piCUvABZFGx37WNb9weM481mP0s2M0Gp76hBbajk+RrsWjCAd2j62zo6oR8 X-Received: by 2002:a1c:448a:: with SMTP id r132mr8864473wma.47.1546881129896; Mon, 07 Jan 2019 09:12:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546881129; cv=none; d=google.com; s=arc-20160816; b=IQrjiT/0jg6zvo95aTrPfS3yChBGvYUd2eEM6+k8XIAYm9fZpcU8+gh5rmV04G1eoh pK4k4llYlVbnZbTZtwJg65gASaerGSe8P43a7J/9g1o6eThhJA6+m9j5BfTdOzmcxwN9 G53ociHkBQ/s/diS92duRdr89QvXOKFdx/Kic/OEKlh/yE/AyYi6SRtxYtqlQAtI7HDi 94PKXu+8g+/aodeoAM1/yrd+kc2ORgMCrVWp/hu+NCmy/ebwuf1xJI5nSmprR9qdoAQJ HO39oojtWgCp/jWnX75GXG9VNmvcmI9lEMx5sFjrnLDWa3QLTTfjY8wrZmp0zHoV/shK vzfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=cDFB1Ur65EARuRk/dPzzE6tv5eNAyb1OwUrHB1LwiDY=; b=akAw8Kji530pkuGcgN2TEEtQFBWI3oA0mvwx6NMTxU47oCcjKrCz8GkbpE46kbUPMy ZbQp2VzpQTCFOEJ+D8Rvu2X/+D2soqcjIxvoZmYbqNDkb840AuCe76Teh4yCTga7GIFN mi3hIF8hatMIvQLRSvz4KwqFLZUrf419hgtPyHb51+c1Gf35iARPFF0HRvW4IWDVsHdO H5fViiRZpBcPrGaH91K+YjuXOppGYx5QBH31YRS5jORDVcglx28u3/IkwdCV9y2cMC1i xQgE0pK6VBMpCtrmwO3g+nqgyNGVgG9ugbEuCO/mYvJ/KiOkGkrej1NAi3gih/IRCoAc D7sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DbdHnwn2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:17 +0000 Message-Id: <20190107163117.16269-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 37/37] Support u-boot noload images for arm as used by, NetBSD/evbarm GENERIC kernel. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Nick Hudson noload kernels are loaded with the u-boot image header and as a result the header size needs adding to the entry point. Fake up a hdr so the kernel image is loaded at the right address and the entry point is adjusted appropriately. The default location for the uboot file is 32MiB above bottom of DRAM. This matches the recommendation in Documentation/arm/Booting. Clarify the load_uimage API to state the passing of a load address when an image doesn't specify one, or when loading a ramdisk is expected. Adjust callers of load_uimage, etc. Signed-off-by: Nick Hudson Message-id: 11488a08-1fe0-a278-2210-deb64731107f@gmx.co.uk Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/core/uboot_image.h | 1 + include/hw/loader.h | 7 ++++++- hw/arm/boot.c | 8 +++++--- hw/core/loader.c | 19 ++++++++++++++++--- hw/microblaze/boot.c | 2 +- hw/nios2/boot.c | 2 +- hw/ppc/e500.c | 1 + hw/ppc/ppc440_bamboo.c | 2 +- hw/ppc/sam460ex.c | 2 +- 9 files changed, 33 insertions(+), 11 deletions(-) -- 2.19.2 diff --git a/hw/core/uboot_image.h b/hw/core/uboot_image.h index 34c11a70a67..608022de6ec 100644 --- a/hw/core/uboot_image.h +++ b/hw/core/uboot_image.h @@ -124,6 +124,7 @@ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ +#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image (noload) */ /* * Compression Types diff --git a/include/hw/loader.h b/include/hw/loader.h index 0a0ad808ea3..de8a29603b0 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -175,10 +175,15 @@ void load_elf_hdr(const char *filename, void *hdr, bool *is64, Error **errp); int load_aout(const char *filename, hwaddr addr, int max_sz, int bswap_needed, hwaddr target_page_size); +#define LOAD_UIMAGE_LOADADDR_INVALID (-1) + /** load_uimage_as: * @filename: Path of uimage file * @ep: Populated with program entry point. Ignored if NULL. - * @loadaddr: Populated with the load address. Ignored if NULL. + * @loadaddr: load address if none specified in the image or when loading a + * ramdisk. Populated with the load address. Ignored if NULL or + * LOAD_UIMAGE_LOADADDR_INVALID (images which do not specify a load + * address will not be loadable). * @is_linux: Is set to true if the image loaded is Linux. Ignored if NULL. * @translate_fn: optional function to translate load addresses * @translate_opaque: opaque data passed to @translate_fn diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 94fce128028..c7a67af7a97 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -30,8 +30,9 @@ * Documentation/arm/Booting and Documentation/arm64/booting.txt * They have different preferred image load offsets from system RAM base. */ -#define KERNEL_ARGS_ADDR 0x100 -#define KERNEL_LOAD_ADDR 0x00010000 +#define KERNEL_ARGS_ADDR 0x100 +#define KERNEL_NOLOAD_ADDR 0x02000000 +#define KERNEL_LOAD_ADDR 0x00010000 #define KERNEL64_LOAD_ADDR 0x00080000 #define ARM64_TEXT_OFFSET_OFFSET 8 @@ -1082,7 +1083,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) } entry = elf_entry; if (kernel_size < 0) { - kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, + uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; + kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, &is_linux, NULL, NULL, as); } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { diff --git a/hw/core/loader.c b/hw/core/loader.c index fa41842280a..c7182dfa64b 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -613,13 +613,26 @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr, goto out; if (hdr->ih_type != image_type) { - fprintf(stderr, "Wrong image type %d, expected %d\n", hdr->ih_type, - image_type); - goto out; + if (!(image_type == IH_TYPE_KERNEL && + hdr->ih_type == IH_TYPE_KERNEL_NOLOAD)) { + fprintf(stderr, "Wrong image type %d, expected %d\n", hdr->ih_type, + image_type); + goto out; + } } /* TODO: Implement other image types. */ switch (hdr->ih_type) { + case IH_TYPE_KERNEL_NOLOAD: + if (!loadaddr || *loadaddr == LOAD_UIMAGE_LOADADDR_INVALID) { + fprintf(stderr, "this image format (kernel_noload) cannot be " + "loaded on this machine type"); + goto out; + } + + hdr->ih_load = *loadaddr + sizeof(*hdr); + hdr->ih_ep += hdr->ih_load; + /* fall through */ case IH_TYPE_KERNEL: address = hdr->ih_load; if (translate_fn) { diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c index 35bfeda7aa7..489ab839b7c 100644 --- a/hw/microblaze/boot.c +++ b/hw/microblaze/boot.c @@ -156,7 +156,7 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base, /* If it wasn't an ELF image, try an u-boot image. */ if (kernel_size < 0) { - hwaddr uentry, loadaddr; + hwaddr uentry, loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0, NULL, NULL); diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c index 4bb5b601d3a..ed5cb28e942 100644 --- a/hw/nios2/boot.c +++ b/hw/nios2/boot.c @@ -161,7 +161,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base, /* If it wasn't an ELF image, try an u-boot image. */ if (kernel_size < 0) { - hwaddr uentry, loadaddr; + hwaddr uentry, loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0, NULL, NULL); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b20fea0dfce..0581e9e3d4c 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -995,6 +995,7 @@ void ppce500_init(MachineState *machine) * Hrm. No ELF image? Try a uImage, maybe someone is giving us an * ePAPR compliant kernel */ + loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, NULL, NULL); if (payload_size < 0) { diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index b8aa55d5266..fc061915887 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -179,7 +179,7 @@ static void bamboo_init(MachineState *machine) CPUPPCState *env; uint64_t elf_entry; uint64_t elf_lowaddr; - hwaddr loadaddr = 0; + hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; target_long initrd_size = 0; DeviceState *dev; int success; diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 4b051c0950a..84ea592749c 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -402,7 +402,7 @@ static void sam460ex_init(MachineState *machine) CPUPPCState *env; PPC4xxI2CState *i2c[2]; hwaddr entry = UBOOT_ENTRY; - hwaddr loadaddr = 0; + hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; target_long initrd_size = 0; DeviceState *dev; SysBusDevice *sbdev;