From patchwork Mon May 23 18:18:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 575521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF88AC433EF for ; Mon, 23 May 2022 18:39:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242188AbiEWSjK (ORCPT ); Mon, 23 May 2022 14:39:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243356AbiEWSi6 (ORCPT ); Mon, 23 May 2022 14:38:58 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E44B1756AB for ; Mon, 23 May 2022 11:18:50 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id bu29so27065232lfb.0 for ; Mon, 23 May 2022 11:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Db68uHKl1+UUBIZ5yalfu7z/18tYxDiBSXR8pSKlIHc=; b=IFtJOdo6qh45Vv6VL8WNpxgCaAjOHurkfzmO7bRTI2BolPV6OjXikSBAwYgrIzhO48 bziFK4bYLZGPgNCnKZPuuPB4wHITaJayqrKShwNPsqLL8go3uUN2swUhp6wR/VWnJXMD wj1HDSHr3Cy5wgFiWYZ/7E0dQcF9kumzlXCHn3wQPKrfKmEJkyMRpqok/q0W31y6xY4l Vrdoj9kYkFv92zMONCTqGOq8sUI0+mfdIySZ5BAPQvfMsKCzYJZecNN/xetuqouRW0Gf X6ZhjANeZY0IJFvSyitzbXfkG5Bl7S80BytlOW8crNkEsnUqrJd6BD5C+fhF+gipglSK pWVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Db68uHKl1+UUBIZ5yalfu7z/18tYxDiBSXR8pSKlIHc=; b=Gc2iUmFESkqxFd9udPElsoq0kQ/uN8uVRbq/sNjV8+S926oWb8JsXrgJKNILBX2A6b Xi0wbH1tHDiAul0CG30sFQf7/6sAx0PumXxs6zaQ1gjsOygso93xMiy/e5JU99lejbCN 6SuDeaDudSqp3OuA3PtjcsStIe3PJUqpY8AlJz4Ss+QhAke++IYLrw5bMOKXOi3BtNfZ u9iosub8DB25+/hTf1EddkvqthqONYlDiNyoNKznyNftSPZYVFIPeoJndniPUgThp7g/ WYt9oGJ8jkvWWete3lhbIsi4xcBk0lQFgodt8AOo4o9lKRK0F7ODCzeYRZBcUtGKZuFX /CXQ== X-Gm-Message-State: AOAM533Wyhi/lv02aQX83GTTMWbeNWJSnHF7Y75VEysH2Qes0uq1V9Cu hiqkU5JRFFPI01ZDYI0RTE2sSg== X-Google-Smtp-Source: ABdhPJxSrlHpZn4gDnhb4ltJQQlDuUuZgI4TVCCxbECdjFlVfTtoG/i+jEMAnpCOpbw7VgE/ODDekg== X-Received: by 2002:ac2:5e32:0:b0:477:c733:9d91 with SMTP id o18-20020ac25e32000000b00477c7339d91mr15968093lfg.485.1653329920237; Mon, 23 May 2022 11:18:40 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id j20-20020a2e6e14000000b0024f3d1daedesm1904127ljc.102.2022.05.23.11.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 11:18:39 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v12 2/8] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Date: Mon, 23 May 2022 21:18:30 +0300 Message-Id: <20220523181836.2019180-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> References: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The subdrivers pass -ESOMETHING if they do not want the core to touch MSI IRQ. dw_pcie_host_init() also checks if (msi_irq > 0) rather than just if (msi_irq). So let's make dw_pcie_free_msi() also check that msi_irq is greater than zero. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov Reviewed-by: Johan Hovold --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9979302532b7..af91fe69f542 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,7 +257,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) static void dw_pcie_free_msi(struct pcie_port *pp) { - if (pp->msi_irq) + if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); irq_domain_remove(pp->msi_domain); From patchwork Mon May 23 18:18:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 575520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F23EEC43217 for ; Mon, 23 May 2022 18:39:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242293AbiEWSjU (ORCPT ); Mon, 23 May 2022 14:39:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243612AbiEWSjC (ORCPT ); Mon, 23 May 2022 14:39:02 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B14C1756B2 for ; Mon, 23 May 2022 11:19:02 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id p4so25579590lfg.4 for ; Mon, 23 May 2022 11:19:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gFEMes1AfWhaaqevgaALAaWMRL+uUFPmUrTzyb1BceA=; b=Ye5lPtGeyOzNCuzZFFomPvE5FKt+GRDqJq0mc4zeg/DbmEt9ZYCLxQQCde5moI7BaJ YwHtKZhzNNr8JqcFUaWS1sogdAA5WHT3/3MUfOgbQGnMbSyDb/MzV+3nF/WfgoW3aB8L h5Ps56AHTkFmrxm2HWfGP9/yASHjkk7kaSsPQmLnbmgmMdL6H+ZEIkxvDxLOOqheIHqk Jzk+VVAa0zXiQAtbbKP+FCRrV1uSd/AqFdjLAEtWw9+kCO8Mv1O4xuPqqBRhnxYP3EAz S4u7eWx6BOWIHCUYqp/EwAELGppTIWZdwDctAWwRc/fBiZ0UrCtFq9PKo20n1bYt+ya9 r3AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gFEMes1AfWhaaqevgaALAaWMRL+uUFPmUrTzyb1BceA=; b=68UWzk38MHf1sYpCNWfLqWpik/xkzGRh5kJk0jKnzFscc5TYyjUFnlQY8tETdJyXT6 79BVyINzAr8NcU9q0BDAWJbev3nJFJ08VtY6UDMI61a0Z3oog/ARWRhlP1MaZ2PTG/xh lqhEdLephTYffYwaaAp+7EteuEMAkJZBiglPupaiATAu9YqD8qCjH8qetdOXpyv4ZI5A u6Jqbbiwjb4LiPdBVzA7C50mO6SfDDTyfBmrw+tO/pVv6xLD74e5sP2BOxmuRQ/OgTK7 UQmdshVXgywUMUQMqf4lkCOzIePazLgf+h0BwHKT5fYypBTJ0BG6qMjEnAMF9sCzVTn+ jzFQ== X-Gm-Message-State: AOAM531/tx83A/81OkD6X2Bb2PXdEE2QetNWboJP11xcmR7v+j9kYiJR TLpEDZ/eGeyfyqapd6E1scY/kQ== X-Google-Smtp-Source: ABdhPJw0OrY5vI46+HdRHCkX9LIpWv0vaK8pOwWPxJFWpovoYdq7GG8JaHwURmSTXWhiavzUP7vxMQ== X-Received: by 2002:a05:6512:3e26:b0:478:5972:54b7 with SMTP id i38-20020a0565123e2600b00478597254b7mr11195988lfv.646.1653329923368; Mon, 23 May 2022 11:18:43 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id j20-20020a2e6e14000000b0024f3d1daedesm1904127ljc.102.2022.05.23.11.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 11:18:42 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v12 5/8] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Date: Mon, 23 May 2022 21:18:33 +0300 Message-Id: <20220523181836.2019180-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> References: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On some of Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Implement support for such configurations by parsing "msi0" ... "msiN" interrupts and attaching them to the chained handler. Note, that if DT doesn't list an array of MSI interrupts and uses single "msi" IRQ, the driver will limit the amount of supported MSI vectors accordingly (to 32). Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 61 +++++++++++++++++-- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index a076abe6611c..98a57249ecaf 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -288,6 +288,47 @@ static void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +static const char * const split_msi_names[] = { + "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", +}; + +static int dw_pcie_parse_split_msi_irq(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct platform_device *pdev = to_platform_device(dev); + int irq; + u32 ctrl, max_vectors; + + /* Parse as many IRQs as described in the devicetree. */ + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { + irq = platform_get_irq_byname_optional(pdev, split_msi_names[ctrl]); + if (irq == -ENXIO) + break; + if (irq < 0) + return dev_err_probe(dev, irq, + "Failed to parse MSI IRQ '%s'\n", + split_msi_names[ctrl]); + + pp->msi_irq[ctrl] = irq; + } + + /* If there were no "msiN" IRQs at all, fallback to the standard "msi" IRQ. */ + if (ctrl == 0) + return -ENXIO; + + max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL; + if (pp->num_vectors > max_vectors) { + dev_warn(dev, "Exceeding number of MSI vectors, limiting to %d\n", max_vectors); + pp->num_vectors = max_vectors; + } + if (!pp->num_vectors) + pp->num_vectors = max_vectors; + + return 0; +} + static int dw_pcie_msi_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -296,21 +337,32 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp) int ret; u32 ctrl, num_ctrls; - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (ctrl = 0; ctrl < num_ctrls; ctrl++) + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) pp->irq_mask[ctrl] = ~0; + if (!pp->msi_irq[0]) { + ret = dw_pcie_parse_split_msi_irq(pp); + if (ret < 0 && ret != -ENXIO) + return ret; + } + + if (!pp->num_vectors) + pp->num_vectors = MSI_DEF_NUM_VECTORS; + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + if (!pp->msi_irq[0]) { int irq = platform_get_irq_byname_optional(pdev, "msi"); if (irq < 0) { irq = platform_get_irq(pdev, 0); if (irq < 0) - return irq; + return dev_err_probe(dev, irq, "Failed to parse MSI irq\n"); } pp->msi_irq[0] = irq; } + dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors); + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; ret = dw_pcie_allocate_domains(pp); @@ -407,7 +459,8 @@ int dw_pcie_host_init(struct pcie_port *pp) of_property_read_bool(np, "msi-parent") || of_property_read_bool(np, "msi-map")); - if (!pp->num_vectors) { + /* for the has_msi_ctrl the default assignment is handled inside dw_pcie_msi_host_init() */ + if (!pp->has_msi_ctrl && !pp->num_vectors) { pp->num_vectors = MSI_DEF_NUM_VECTORS; } else if (pp->num_vectors > MAX_MSI_IRQS) { dev_err(dev, "Invalid number of vectors\n"); From patchwork Mon May 23 18:18:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 575518 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9049CC433FE for ; Mon, 23 May 2022 18:42:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237875AbiEWSmY (ORCPT ); Mon, 23 May 2022 14:42:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243597AbiEWSjC (ORCPT ); Mon, 23 May 2022 14:39:02 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02FE2177061 for ; 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Mon, 23 May 2022 11:18:44 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id j20-20020a2e6e14000000b0024f3d1daedesm1904127ljc.102.2022.05.23.11.18.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 11:18:43 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v12 6/8] PCI: dwc: Implement special ISR handler for split MSI IRQ setup Date: Mon, 23 May 2022 21:18:34 +0300 Message-Id: <20220523181836.2019180-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> References: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If the PCIe DWC controller uses split MSI IRQs for reporting MSI vectors, it is possible to detect, which group triggered the interrupt. Provide an optimized version of MSI ISR handler that will handle just a single MSI group instead of handling all of them. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 86 ++++++++++++++----- 1 file changed, 65 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 98a57249ecaf..2b2de517301a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -52,34 +52,42 @@ static struct msi_domain_info dw_pcie_msi_domain_info = { .chip = &dw_pcie_msi_irq_chip, }; +static inline irqreturn_t dw_handle_single_msi_group(struct pcie_port *pp, int i) +{ + int pos; + unsigned long val; + u32 status; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + + (i * MSI_REG_CTRL_BLOCK_SIZE)); + if (!status) + return IRQ_NONE; + + val = status; + pos = 0; + while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, + pos)) != MAX_MSI_IRQS_PER_CTRL) { + generic_handle_domain_irq(pp->irq_domain, + (i * MAX_MSI_IRQS_PER_CTRL) + + pos); + pos++; + } + + return IRQ_HANDLED; +} + /* MSI int handler */ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { - int i, pos; - unsigned long val; - u32 status, num_ctrls; + int i; + u32 num_ctrls; irqreturn_t ret = IRQ_NONE; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (i = 0; i < num_ctrls; i++) { - status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + - (i * MSI_REG_CTRL_BLOCK_SIZE)); - if (!status) - continue; - - ret = IRQ_HANDLED; - val = status; - pos = 0; - while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, - pos)) != MAX_MSI_IRQS_PER_CTRL) { - generic_handle_domain_irq(pp->irq_domain, - (i * MAX_MSI_IRQS_PER_CTRL) + - pos); - pos++; - } - } + for (i = 0; i < num_ctrls; i++) + ret |= dw_handle_single_msi_group(pp, i); return ret; } @@ -98,6 +106,38 @@ static void dw_chained_msi_isr(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static void dw_split_msi_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + int irq = irq_desc_get_irq(desc); + struct pcie_port *pp; + int i; + u32 num_ctrls; + struct dw_pcie *pci; + + chained_irq_enter(chip, desc); + + pp = irq_desc_get_handler_data(desc); + pci = to_dw_pcie_from_pp(pp); + + /* + * Unlike generic dw_handle_msi_irq(), we can determine which group of + * MSIs triggered the IRQ, so process just that group. + */ + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + for (i = 0; i < num_ctrls; i++) { + if (pp->msi_irq[i] == irq) { + dw_handle_single_msi_group(pp, i); + break; + } + } + + WARN_ON_ONCE(i == num_ctrls); + + chained_irq_exit(chip, desc); +} + static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); @@ -336,6 +376,7 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp) struct platform_device *pdev = to_platform_device(dev); int ret; u32 ctrl, num_ctrls; + bool has_split_msi_irq = false; for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) pp->irq_mask[ctrl] = ~0; @@ -344,6 +385,8 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp) ret = dw_pcie_parse_split_msi_irq(pp); if (ret < 0 && ret != -ENXIO) return ret; + else if (!ret) + has_split_msi_irq = true; } if (!pp->num_vectors) @@ -372,6 +415,7 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp) for (ctrl = 0; ctrl < num_ctrls; ctrl++) if (pp->msi_irq[ctrl] > 0) irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + has_split_msi_irq ? dw_split_msi_isr : dw_chained_msi_isr, pp); From patchwork Mon May 23 18:18:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 575519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF62EC433EF for ; Mon, 23 May 2022 18:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243612AbiEWSjV (ORCPT ); Mon, 23 May 2022 14:39:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235787AbiEWSjC (ORCPT ); Mon, 23 May 2022 14:39:02 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D00A7177891 for ; Mon, 23 May 2022 11:19:04 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id 27so13253592ljw.0 for ; Mon, 23 May 2022 11:19:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HYUuQ4fR4SBZdSuM6IAnUnoggotKrAQZZIhO70s2q7Y=; b=QYYWiNQNm/oL2rplHN7Uw+iWwXFrRQe1iC//feAzu915Y1wyqCc8WmJdUnWIVcSqhh JMHtqXXBevW9e3pAJQrzhLoE135R2wRo6jqCIeGhT7z2v2J9nqL0cO3ojRgJXNc25DDn K1AMMnczOGAdGeZYElB7lCYf+eMNvGWSLj1GgThKm5rz4nW8WGc+EZVQMHiYsjBw9HDn DJ97MQBp1xbl8ONATS4C/0/GUFR4GIqgk7XNxbhWWqUE9wvvLd8T1HEUymVp5sk7pz8y h/aR75FyE6eH1XaMUN8vgAajV52nsEWoqG7oNdCuNKrsZ/robtm69oUaz3M3tTnInG4k 7QKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HYUuQ4fR4SBZdSuM6IAnUnoggotKrAQZZIhO70s2q7Y=; b=ka43YTcWqKwuoZuLHodtgcKqcQwmb89/mHfH99Hu5dZK3TMtY9+6XDXTcJGmSmVe5k fiiN87CRr8/ri7Ms2InVVR7wwkA4IoNp/SZXbpuHeSDD4oF+5SUzJxdEJopYBF71SZCv BX2p/K4y0nAMCGbryjrFVjSHpVSL+lEXuxJ/jwnFKn+2Cb6Vyon5bzJzlDusT8tqm9BX w8GqYzvfLtOTHNktX6QEgO6S/3fSvlibHC/URgyrZ63tfiTJcDhdVK9oQ2pfmTqGsn5S 554BlV7UYwf/jGZmnJumPPlbg/xbXdvz7pUlIWAXVV1u6WR7jxOvDLRQAeKEpHM569Pm DWaw== X-Gm-Message-State: AOAM5338UTtZbe4CL7Rt0Ip+6oSzlaeeQ5NRVigzDpt9OlIpd1pdAd80 f8NWRJPRPybsLCLDoQaoKi7ufg== X-Google-Smtp-Source: ABdhPJyVKnlZ6ujYgGbG9H8omcqdxH5nnoRtCc1cglAPXhlprZD9wdrYIV7uDvnGCHE9LwmLh18bhQ== X-Received: by 2002:a2e:920a:0:b0:253:e695:606a with SMTP id k10-20020a2e920a000000b00253e695606amr5585674ljg.17.1653329924984; Mon, 23 May 2022 11:18:44 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id j20-20020a2e6e14000000b0024f3d1daedesm1904127ljc.102.2022.05.23.11.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 11:18:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v12 7/8] dt-bindings: PCI: qcom: Support additional MSI interrupts Date: Mon, 23 May 2022 21:18:35 +0300 Message-Id: <20220523181836.2019180-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> References: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie.yaml | 53 +++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12b849e..fe8f9a62a665 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,12 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: - items: - - const: msi + minItems: 1 + maxItems: 8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +624,52 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + items: + - const: msi + - properties: + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + unevaluatedProperties: false examples: