From patchwork Wed May 25 14:43:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 576077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B56A4C433FE for ; Wed, 25 May 2022 14:44:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232038AbiEYOom (ORCPT ); Wed, 25 May 2022 10:44:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244853AbiEYOoj (ORCPT ); Wed, 25 May 2022 10:44:39 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27C92ABF46 for ; Wed, 25 May 2022 07:44:36 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id y13so41422578eje.2 for ; Wed, 25 May 2022 07:44:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KhlEBIuQ03eusWOfEIpb3AWYeF5p0BIH1Ax8ZKxHaIU=; b=HYwjZB3aWboUwzWq0BJxI7E1IepJCdru5AAGgubDmK5VK4WSXa5SYhu3K75AJZ+sXK OCLsgqoa4mrbqc0XJcnHoF/I/8Aodo/8R/xogaVAP/ISmEFbbnY62t2vvJ3Du/oSxo/6 SMJUmkSM3CsyJS0xlBFiU5h+5oPuFLapnbpPBECTxOyXOR1oUEeNSE9PGzvLysz7NpF0 fRkMFCeuBaqV3obwXXtq4UzmU7Dh8d7Npq5r5bA8IrQDXzfL57W7BDQsEdpFxnVHRLjB zLbFgASHZhQbx+Ss/y7PbfQugFD/A7KHcbjb/CaCaaJxeNfNgWbVbJhDiSiyEkNj1t48 YRqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KhlEBIuQ03eusWOfEIpb3AWYeF5p0BIH1Ax8ZKxHaIU=; b=nfbT1uDw/ZqEducLY7VOhJik43nb5mXQjmi6/NEXI1FDhjc6KDe/7I/O3ATUlREsl3 Li2fy/Q7dj5PoADbP+N5MSZ4j6/H4aVKv8nE0NQHGtxKost8F7+ggDMxIHu//R+2cH25 DkQLc37bJvTZaWa17+PEe5UjYg10J1cV58WddF+opaTxIswtBeo84Ji4vt8e+jTRWmVV HlBL7BRg4tJ49ESeu0nuVWjWsP5NShr1sVqxlepGtiSgTRZw1mD9Hh21eNzYrP44w5rD kxmU/gW8HNCSq1QZ83LJFh1RysitYUsuWk/mLtFRc8tKSQC2V4FhRnAgI0Hlkgbt1SOA pViQ== X-Gm-Message-State: AOAM530xa6dib6wZ0ECLzUuOX5VL3KLh+/CdNGiGm+2MxvRjRE6JjvDM Uo/4zN48khAWf+r8Ofb6xFOXkQ== X-Google-Smtp-Source: ABdhPJzPsltsdGsrAfLJ/TR+I0VNaXB93M/IcJcIEkH/OFtUEvKEHUFNs+QtI4kfrbkgqzuJjUw7Fg== X-Received: by 2002:a17:907:6d10:b0:6fe:c744:43be with SMTP id sa16-20020a1709076d1000b006fec74443bemr17045582ejc.470.1653489874615; Wed, 25 May 2022 07:44:34 -0700 (PDT) Received: from otso.. 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id r2-20020a170906550200b006f3ef214de1sm8159596ejp.71.2022.05.25.07.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 07:44:34 -0700 (PDT) From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Odelu Kukatla , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/5] dt-bindings: interconnect: qcom: Split out rpmh-common bindings Date: Wed, 25 May 2022 16:43:58 +0200 Message-Id: <20220525144404.200390-3-luca.weiss@fairphone.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220525144404.200390-1-luca.weiss@fairphone.com> References: <20220525144404.200390-1-luca.weiss@fairphone.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation for the platforms, split out common definitions used in rpmh-based interconnects. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski --- Changes since v2: * Reorganize patches so order is more logical * Replace bouncing maintainer email with Bjorn * maxItems: 2 for qcom,bcm-voters and qcom,bcm-voter-names * Remove | from some descriptions .../interconnect/qcom,rpmh-common.yaml | 43 +++++++++++++++++++ .../bindings/interconnect/qcom,rpmh.yaml | 22 +++------- 2 files changed, 48 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml new file mode 100644 index 000000000000..e962e8dc9a61 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect + +maintainers: + - Georgi Djakov + - Bjorn Andersson + +description: + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + '#interconnect-cells': + enum: [ 1, 2 ] + + qcom,bcm-voters: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + maxItems: 2 + description: + List of phandles to qcom,bcm-voter nodes that are required by + this interconnect to send RPMh commands. + + qcom,bcm-voter-names: + description: + Names for each of the qcom,bcm-voters specified. + maxItems: 2 + +required: + - '#interconnect-cells' + - qcom,bcm-voters + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index fae3363fed02..e822dc099339 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -18,6 +18,9 @@ description: | least one RPMh device child node pertaining to their RSC and each provider can map to multiple RPMh resources. +allOf: + - $ref: qcom,rpmh-common.yaml# + properties: reg: maxItems: 1 @@ -131,28 +134,13 @@ properties: - qcom,sm8450-pcie-anoc - qcom,sm8450-system-noc - '#interconnect-cells': - enum: [ 1, 2 ] - - qcom,bcm-voters: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - maxItems: 1 - description: | - List of phandles to qcom,bcm-voter nodes that are required by - this interconnect to send RPMh commands. - - qcom,bcm-voter-names: - description: | - Names for each of the qcom,bcm-voters specified. + '#interconnect-cells': true required: - compatible - reg - - '#interconnect-cells' - - qcom,bcm-voters -additionalProperties: false +unevaluatedProperties: false examples: - | From patchwork Wed May 25 14:44:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 576076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A865AC433FE for ; Wed, 25 May 2022 14:44:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240770AbiEYOop (ORCPT ); Wed, 25 May 2022 10:44:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244894AbiEYOoo (ORCPT ); Wed, 25 May 2022 10:44:44 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF951AE244 for ; Wed, 25 May 2022 07:44:41 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id f21so28476803ejh.11 for ; Wed, 25 May 2022 07:44:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ofMD+z2oV9+oiTcB8ClGG1nsZ8Ej5W9o4q3U+Ksa5Uw=; b=moCAWImdMLqDufc3TXmt5sapIcISEyjUSAghKNBvb4vzVLlS7SwsWQDzYB5QUx7G8Y P7OD3P8faIwsSTTeOa+T+Owj+UCZcdfkgWab1i/PEvYp3RFHdVwGeSbTmyhKGQ+zCF2/ q04NK6k+4JVtCWnBc5tcanVUnukRJdkV8eEBu4XYYAFpKJOKO67GC6ehqTrHUXFT+kjx 1VDlC5Pg5ZiGbuQqhMBYelc6cFIqbodAHrGMbEEmQdRooZ5vyYFSxF7d2kp2KRir55lW QJmAapvk4RRGjOd5tN7kP3hI3vxBXGYlW6GK8cf8JG6MVlk8MGfFxteLhqD2iqOdKSAW yReA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ofMD+z2oV9+oiTcB8ClGG1nsZ8Ej5W9o4q3U+Ksa5Uw=; b=RvsCcANp+WirTMtvD1GEyNcVykvGGMmnvOI+ICMNI2xYQtCT6MK2LQkZRxxZixLwtC CLD31IirZ+QgCfik8bWsT9OaJ8755pp0qn8yXmUhYMO/ad7wCWoXUPsTIyquaQQQ71Po ko2HsAiY60E95dqObk+BOqBuyfbbsZTn+Tdw1YY+a54Y0ZDcqRbjbUee3GErJVYyB3e3 d/f1z/zhxjzAQDp8/cAzbzG/yG/JMXAQQRA88MIypmxv7PXtzOcmOhJEm1we0lWdPWab pOppXyZ18PQX/CTWOd70qynFTs/ogG7NuYhyIRwsD1oOoNsQoWKZrxRSPEBJu3yAIEO+ a1uA== X-Gm-Message-State: AOAM530juy+dNzicpquCw79jECQTNxy5Eax8gSq/NSTrrar4ejYImwx7 KYRH5mYbjrW/u20a4zsufpm/5w== X-Google-Smtp-Source: ABdhPJy3PWgO5E6DAJkr5aFegnBB8BHm80d8zEbsc269ulJNaqXw0TFRhzJl3d02E0ccvfCfQ2wCDg== X-Received: by 2002:a17:907:9715:b0:6fe:d943:3116 with SMTP id jg21-20020a170907971500b006fed9433116mr14989002ejc.257.1653489880355; Wed, 25 May 2022 07:44:40 -0700 (PDT) Received: from otso.. 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id r2-20020a170906550200b006f3ef214de1sm8159596ejp.71.2022.05.25.07.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 07:44:39 -0700 (PDT) From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support Date: Wed, 25 May 2022 16:44:01 +0200 Message-Id: <20220525144404.200390-6-luca.weiss@fairphone.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220525144404.200390-1-luca.weiss@fairphone.com> References: <20220525144404.200390-1-luca.weiss@fairphone.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add all the different NoC providers that are found in SM6350 and populate different nodes that use the interconnect properties. Signed-off-by: Luca Weiss --- Changes since v2: * none arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 +++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index fb1a0f662575..119073f19285 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1,11 +1,13 @@ // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, Konrad Dybcio + * Copyright (c) 2022, Luca Weiss */ #include #include #include +#include #include #include #include @@ -539,6 +541,10 @@ i2c0: i2c@880000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -552,6 +558,10 @@ i2c2: i2c@888000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; }; @@ -578,6 +588,10 @@ i2c6: i2c@980000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -591,6 +605,10 @@ i2c7: i2c@984000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -604,6 +622,10 @@ i2c8: i2c@988000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -615,6 +637,9 @@ uart9: serial@98c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_default>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -628,11 +653,62 @@ i2c10: i2c@990000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sm6350-config-noc"; + reg = <0 0x01500000 0 0x28000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm6350-system-noc"; + reg = <0 0x01620000 0 0x17080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sm6350-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm6350-aggre1-noc"; + reg = <0 0x016e0000 0 0x15080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm6350-aggre2-noc"; + reg = <0 0x01700000 0 0x1f880>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + + compute_noc: interconnect-compute-noc { + compatible = "qcom,sm6350-compute-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sm6350-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufs@1d84000 { compatible = "qcom,sm6350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -933,6 +1009,10 @@ sdhc_2: sdhci@8804000 { <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd 0>; @@ -947,11 +1027,15 @@ sdhc2_opp_table: sdhc2-opp-table { opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <790000 131000>; + opp-avg-kBps = <50000 50000>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3190000 294000>; + opp-avg-kBps = <261438 300000>; }; }; }; @@ -1017,12 +1101,33 @@ dp_phy: dp-phy@88ea200 { }; }; + dc_noc: interconnect@9160000 { + compatible = "qcom,sm6350-dc-noc"; + reg = <0 0x09160000 0 0x3200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; }; + gem_noc: interconnect@9680000 { + compatible = "qcom,sm6350-gem-noc"; + reg = <0 0x09680000 0 0x3e200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + npu_noc: interconnect@9990000 { + compatible = "qcom,sm6350-npu-noc"; + reg = <0 0x09990000 0 0x1600>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; @@ -1051,6 +1156,10 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>;