From patchwork Wed May 25 00:32:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 576110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15A90C433FE for ; Wed, 25 May 2022 00:33:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241065AbiEYAdP (ORCPT ); Tue, 24 May 2022 20:33:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241106AbiEYAdN (ORCPT ); Tue, 24 May 2022 20:33:13 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 185405C76C for ; Tue, 24 May 2022 17:33:10 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id z25so5143457pfr.1 for ; Tue, 24 May 2022 17:33:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C4C/D4T+CUJxvXvtCc8LzXnNYagqhSTrzLZVSiGb5zY=; b=g//OhIA0UTsxXJFmtA6Yjqv1mp+jHeAcfxuLELOuTrgbC8jTtOHm8ixIMhylQiJUUe KF04EdncRzRvqP1+3hoZU3iOad5Hxet3k76doOGDcm+U8bx9PtfxqWLhX3E+2FMDJYfn 8Y16xi2U3UIvzxWvQmooV/w22AeNKH+q7ewEM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C4C/D4T+CUJxvXvtCc8LzXnNYagqhSTrzLZVSiGb5zY=; b=V3T3ivYJedeszxqQELwtkmf5ZC440uqnr1rkNU4Z3Yqz4Zp5pkwspP+fJvVr50sA7i /v9MHWkkp253fwD9a2vU0L2nk8vLxRYChG5WHCzjCSFg8GSrkK0AD2R1Ddd6sxUqGVR4 BTMTEyrFl2dJLpddcVh0Ix9k4QC2VXhLR81i9phZOFhL0hfj7NKgkAI6ajt9zM7bunBi YV522leu3mmmjpLdIAXSeYZbytJfB/cj7qPguYkj/zDEXEZE0IAJtAVRY66ctCV7SWPJ 7mY2sMW/O0usVQ8shdM0+8VSbePZmnhCiB+ekSTTBgVZrIzaFiskSSngY8T1MwUu5ACL 96OA== X-Gm-Message-State: AOAM530/vKo6v5Lvo5kzy/oJ+8C5S0tKkPsmTZqA2/YsDkEJ0OlTb+9H BEKMmCxRr5nxR9MAG9O78pGsPQ== X-Google-Smtp-Source: ABdhPJyKWWyRzUNEQSFUPvMrVx5fySO0oToibLjAeOhNPvvGU3SjjZj9ykLkFlOZ8RmmVxp82uO9bA== X-Received: by 2002:a05:6a00:2408:b0:4f7:a8cb:9b63 with SMTP id z8-20020a056a00240800b004f7a8cb9b63mr31211627pfh.33.1653438789403; Tue, 24 May 2022 17:33:09 -0700 (PDT) Received: from T3500-3.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id t71-20020a63784a000000b003db610ebdd0sm7087438pgc.65.2022.05.24.17.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 17:33:07 -0700 (PDT) From: William Zhang To: Linux ARM List Cc: samyon.furman@broadcom.com, philippe.reynes@softathome.com, kursad.oney@broadcom.com, florian.fainelli@broadcom.com, joel.peshkin@broadcom.com, anand.gore@broadcom.com, dan.beygelman@broadcom.com, tomer.yacoby@broadcom.com, William Zhang , Arnd Bergmann , Broadcom internal kernel review list , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH 2/3] ARM: dts: add dts files for bcmbca SoC bcm6846 Date: Tue, 24 May 2022 17:32:35 -0700 Message-Id: <20220525003236.2699-3-william.zhang@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525003236.2699-1-william.zhang@broadcom.com> References: <20220525003236.2699-1-william.zhang@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dts for ARMv7 based broadband SoC BCM6846. bcm6846.dtsi is the SoC description dts header and bcm96846.dts is a simple dts file for Broadcom BCM96846 Reference board that only enable the UART port. Signed-off-by: William Zhang --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/bcm6846.dtsi | 103 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm96846.dts | 30 ++++++++++ 3 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm6846.dtsi create mode 100644 arch/arm/boot/dts/bcm96846.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index edfbedaa6168..b4143031860b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -182,7 +182,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb dtb-$(CONFIG_ARCH_BCMBCA) += \ - bcm947622.dtb + bcm947622.dtb \ + bcm96846.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi new file mode 100644 index 000000000000..e610c102498f --- /dev/null +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6846", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x1b>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts new file mode 100644 index 000000000000..c70ebccabc19 --- /dev/null +++ b/arch/arm/boot/dts/bcm96846.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6846.dtsi" + +/ { + model = "Broadcom BCM96846 Reference Board"; + compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};