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The result can be unexpectly long SPL boot time. This change adds support for wait_dat0() mmc operation. Signed-off-by: Loic Poulain Reviewed-by: Jaehoon Chung --- drivers/mmc/mmc.c | 3 +++ include/mmc.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f6ccd83..109f340 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -34,6 +34,9 @@ static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us) { + if (mmc->cfg->ops->wait_dat0) + return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us); + return -ENOSYS; } diff --git a/include/mmc.h b/include/mmc.h index 6bdcce8..b7e94e8 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -561,6 +561,7 @@ struct mmc_ops { int (*getwp)(struct mmc *mmc); int (*host_power_cycle)(struct mmc *mmc); int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt); + int (*wait_dat0)(struct mmc *mmc, int state, int timeout_us); }; static inline int mmc_hs400_prepare_ddr(struct mmc *mmc) From patchwork Thu May 26 14:37:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 576241 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp633977mab; Thu, 26 May 2022 07:37:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy/qY12tFZpwWOXUWHSMixmKW9CbkDxpCJMIjGeC0KUVun4v4+KLNM2O/ZiPfQLQDB5CFJ9 X-Received: by 2002:a05:6602:1551:b0:665:6755:d179 with SMTP id h17-20020a056602155100b006656755d179mr7877172iow.3.1653575860087; Thu, 26 May 2022 07:37:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653575860; cv=none; d=google.com; s=arc-20160816; b=Cs3l8kz/7LBJ6+ZxA+rpsk20gNgbjwm1PC/lA8SAbbLfL6n6RqCUW+yndmX8+73sJy FmywFMFaWmX0ufzB3YiQWYKBSiIo3Bt6g9ESr/+7UTDtFLziL88Oxb40cRqeDjgPaJmQ OJD04xMQ5rdm8JXMXapQuqrsatXuq6j/F3KgwcTTROVz6vSuJQGPQSOHMg82j5u1DC6J HEctjTXArLOTzxaUCc9WiIhFGR60bZ5igjk1IShr0i27Lg3x0AcLcHx7YbrobYWrWTY0 uGukuWPbRBU+iZoo/M1JsdG3XxuKVzr/sKZnK78EVCMtJs1Spfq9iK0Lq45qrliyEOlQ SxgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=sNohbryY1wfMHuL20UMahkVckbunJ3cFL4BruuWMThc=; b=IYR88cqa8AZky71xx7XD3uifK23BhTEb4mbTx5oX0/5plO0gwJGxL3VZS/2+3xJVf0 IdvAQdU80odEg+xSRiqc8IBdcYo2s5I42ZVkLhWKaD6o1JMug/5RTUxmkUgvhU5gXzmx WKQtF8MeqOULNuTOuVEz/NJqDu4++pfyA6fNzUXowI4Ds7JT9feoxSZYB4BCaTIFV5rf IMCFp6io7OypOUyP6Qz0DtjxCO2jsEiQWDvQG4ZGk9eiSHJxI3EqyzqZYqSRKIKKNFKM 7wwlysiMFxNsbtIYL53FMU+1rBAs78sAhIEtpyQRAtjuajgziQoDE+gk/YBBhlzUPZz7 h4tA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZnO2vOUG; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Before (using grabserial): [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.028257 0.028257] DDRINFO: start DRAM init [0.028500 0.000243] DDRINFO: DRAM rate 3000MTS [0.304627 0.276127] DDRINFO:ddrphy calibration done [0.305647 0.001020] DDRINFO: ddrmix config done [0.352584 0.046937] SEC0: RNG instantiated [0.374299 0.021715] Normal Boot [0.374675 0.000376] Trying to boot from MMC2 [1.250580 0.875905] NOTICE: BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9 [1.251985 0.001405] NOTICE: BL31: Built : 08:02:40, Apr 12 2022 [1.522560 0.270575] [1.522734 0.000174] [1.522788 0.000054] U-Boot 2021.04-xxxx After: [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.001614 0.001614] DDRINFO: start DRAM init [0.002377 0.000763] DDRINFO: DRAM rate 3000MTS [0.278494 0.276117] DDRINFO:ddrphy calibration done [0.279266 0.000772] DDRINFO: ddrmix config done [0.338432 0.059166] SEC0: RNG instantiated [0.339051 0.000619] Normal Boot [0.339431 0.000380] Trying to boot from MMC2 [0.412587 0.073156] NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b [0.414191 0.001604] NOTICE: BL31: Built : 10:35:26, Apr 6 2022 [0.700685 0.286494] [0.700793 0.000108] [0.700845 0.000052] U-Boot 2021.04-xxxx Signed-off-by: Loic Poulain Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc_imx.c | 50 ++++++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 02208a5..ec52f93 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1060,6 +1060,30 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) return timeout > 0; } +static int esdhc_wait_dat0_common(struct fsl_esdhc_priv *priv, int state, + int timeout_us) +{ + struct fsl_esdhc *regs = priv->esdhc_regs; + int ret, err; + u32 tmp; + + /* make sure the card clock keep on */ + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, + !!(tmp & PRSSTAT_DAT0) == !!state, + timeout_us); + + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + + err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (err) + pr_warn("card clock not gate off as expect.\n"); + + return ret; +} + static int esdhc_reset(struct fsl_esdhc *regs) { ulong start; @@ -1109,11 +1133,19 @@ static int esdhc_set_ios(struct mmc *mmc) return esdhc_set_ios_common(priv, mmc); } +static int esdhc_wait_dat0(struct mmc *mmc, int state, int timeout_us) +{ + struct fsl_esdhc_priv *priv = mmc->priv; + + return esdhc_wait_dat0_common(priv, state, timeout_us); +} + static const struct mmc_ops esdhc_ops = { .getcd = esdhc_getcd, .init = esdhc_init, .send_cmd = esdhc_send_cmd, .set_ios = esdhc_set_ios, + .wait_dat0 = esdhc_wait_dat0, }; #endif @@ -1576,25 +1608,9 @@ static int __maybe_unused fsl_esdhc_set_enhanced_strobe(struct udevice *dev) static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, int timeout_us) { - int ret, err; - u32 tmp; struct fsl_esdhc_priv *priv = dev_get_priv(dev); - struct fsl_esdhc *regs = priv->esdhc_regs; - /* make sure the card clock keep on */ - esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - - ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, - !!(tmp & PRSSTAT_DAT0) == !!state, - timeout_us); - - /* change to default setting, let host control the card clock */ - esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); - if (err) - dev_warn(dev, "card clock not gate off as expect.\n"); - - return ret; + return esdhc_wait_dat0_common(priv, state, timeout_us); } static const struct dm_mmc_ops fsl_esdhc_ops = {