From patchwork Mon May 30 15:05:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marco Felsch X-Patchwork-Id: 577339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F8E5C433F5 for ; Mon, 30 May 2022 15:49:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239330AbiE3PtM (ORCPT ); Mon, 30 May 2022 11:49:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240451AbiE3Psu (ORCPT ); Mon, 30 May 2022 11:48:50 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D8AECE5D9 for ; Mon, 30 May 2022 08:06:12 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nvgy4-0005Kw-Bj; Mon, 30 May 2022 17:06:04 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nvgy4-005TIB-Q7; Mon, 30 May 2022 17:06:03 +0200 Received: from mfe by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nvgy1-005Bdz-DD; Mon, 30 May 2022 17:06:01 +0200 From: Marco Felsch To: robert.foss@linaro.org, laurent.pinchart@ideasonboard.com, jernej.skrabec@gmail.com, jonas@kwiboo.se, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sam@ravnborg.org, maxime@cerno.tech Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, kernel@pengutronix.de Subject: [PATCH 2/6] dt-bindings: drm/bridge: ti-sn65dsi83: add documentation for reverse lvds lanes Date: Mon, 30 May 2022 17:05:45 +0200 Message-Id: <20220530150548.1236307-3-m.felsch@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220530150548.1236307-1-m.felsch@pengutronix.de> References: <20220530150548.1236307-1-m.felsch@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TI converter chip can swap the LVDS data lanes in a pre-defined manner. This can be useful to improve the layout characteristic. Signed-off-by: Marco Felsch --- .../bindings/display/bridge/ti,sn65dsi83.yaml | 58 ++++++++++++++++++- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml index 48a97bb3e2e0..7306b9874dc3 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml @@ -80,13 +80,67 @@ properties: - const: 4 port@2: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Video port for LVDS Channel-A output (panel or bridge). + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: | + Array of physical LVDS data lane indexes in reverse or normal + order. Specify it in reverse order to enable the bridge CHA + reverse ordering. If not specified normal order is used. + items: + oneOf: + # reverse order + - items: + - const: 4 + - const: 3 + - const: 2 + - const: 1 + # normal order + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + port@3: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Video port for LVDS Channel-B output (panel or bridge). + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: | + Array of physical LVDS data lane indexes in reverse or normal + order. Specify it in reverse order to enable the bridge CHB + reverse ordering. If not specified normal order is used. + items: + oneOf: + # reverse order + - items: + - const: 4 + - const: 3 + - const: 2 + - const: 1 + # normal order + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + required: - port@0 - port@2 From patchwork Mon May 30 15:05:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marco Felsch X-Patchwork-Id: 577338 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6DBFC433FE for ; Mon, 30 May 2022 15:49:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238978AbiE3PtJ (ORCPT ); Mon, 30 May 2022 11:49:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238539AbiE3Psz (ORCPT ); Mon, 30 May 2022 11:48:55 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20F20CE5F8 for ; Mon, 30 May 2022 08:06:12 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nvgy4-0005Kk-Bj; Mon, 30 May 2022 17:06:04 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nvgy3-005THw-Oy; Mon, 30 May 2022 17:06:02 +0200 Received: from mfe by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nvgy1-005Be2-Du; Mon, 30 May 2022 17:06:01 +0200 From: Marco Felsch To: robert.foss@linaro.org, laurent.pinchart@ideasonboard.com, jernej.skrabec@gmail.com, jonas@kwiboo.se, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sam@ravnborg.org, maxime@cerno.tech Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, kernel@pengutronix.de Subject: [PATCH 3/6] drm/bridge: ti-sn65dsi83: add support to swap the LVDS data lanes Date: Mon, 30 May 2022 17:05:46 +0200 Message-Id: <20220530150548.1236307-4-m.felsch@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220530150548.1236307-1-m.felsch@pengutronix.de> References: <20220530150548.1236307-1-m.felsch@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The chip can swap the LVDS channel A/B data lanes e.g. to improve the layout characteristic. This commit adds the feature so the system integrator can specify it within the device-tree. Signed-off-by: Marco Felsch --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 64 +++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c index 112fea004c8e..baf94b2b78a1 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -148,6 +149,8 @@ struct sn65dsi83 { int dsi_lanes; bool lvds_dual_link; bool lvds_dual_link_even_odd_swap; + bool lvds_reverse_cha; + bool lvds_reverse_chb; }; static const struct regmap_range sn65dsi83_readable_ranges[] = { @@ -441,6 +444,10 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, val = REG_LVDS_LANE_CHA_LVDS_TERM | REG_LVDS_LANE_CHB_LVDS_TERM; if (ctx->lvds_dual_link_even_odd_swap) val |= REG_LVDS_LANE_EVEN_ODD_SWAP; + if (ctx->lvds_reverse_cha) + val |= REG_LVDS_LANE_CHA_REVERSE_LVDS; + if (ctx->lvds_reverse_chb) + val |= REG_LVDS_LANE_CHB_REVERSE_LVDS; regmap_write(ctx->regmap, REG_LVDS_LANE, val); regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); @@ -566,6 +573,47 @@ static const struct drm_bridge_funcs sn65dsi83_funcs = { .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, }; +static int sn65dsi83_parse_lvds_lane_order(struct sn65dsi83 *ctx, unsigned char port) +{ + struct device *dev = ctx->dev; + struct device_node *ep; + int lvds_lanes; + int ret = 0; + + if (port < 2 || port > 3) + return -EINVAL; + + ep = of_graph_get_endpoint_by_regs(dev->of_node, port, 0); + lvds_lanes = of_property_count_u32_elems(ep, "data-lanes"); + if (lvds_lanes == 4) { + u32 lane_assignments[] = { 1, 2, 3, 4 }; + + of_property_read_u32_array(ep, "data-lanes", lane_assignments, + lvds_lanes); + if (lane_assignments[0] == 4 && + lane_assignments[1] == 3 && + lane_assignments[2] == 2 && + lane_assignments[3] == 1) { + if (port == 2) + ctx->lvds_reverse_cha = true; + else + ctx->lvds_reverse_chb = true; + } else if (lane_assignments[0] != 1 || + lane_assignments[1] != 2 || + lane_assignments[2] != 3 || + lane_assignments[3] != 4) { + dev_err(dev, "Unsupported LVDS lane order\n"); + ret = -EINVAL; + } + } else if (lvds_lanes > 0) { + dev_err(dev, "All 4 LVDS data-lanes must be specified\n"); + ret = -EINVAL; + } + of_node_put(ep); + + return ret; +} + static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) { struct drm_bridge *panel_bridge; @@ -610,6 +658,22 @@ static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) } } + /* + * Todo: + * Check if the reverse lane setup is working in dual-link as well. + */ + if (!ctx->lvds_dual_link) { + ret = sn65dsi83_parse_lvds_lane_order(ctx, 2); + if (ret) + return ret; + + if (model != MODEL_SN65DSI83) { + ret = sn65dsi83_parse_lvds_lane_order(ctx, 3); + if (ret) + return ret; + } + } + panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); if (IS_ERR(panel_bridge)) { ret = PTR_ERR(panel_bridge); From patchwork Mon May 30 15:05:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marco Felsch X-Patchwork-Id: 577340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 575C9C433EF for ; Mon, 30 May 2022 15:49:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237302AbiE3PtH (ORCPT ); Mon, 30 May 2022 11:49:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233266AbiE3Psu (ORCPT ); Mon, 30 May 2022 11:48:50 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ED6ACE5E6 for ; Mon, 30 May 2022 08:06:12 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nvgy4-0005Kr-Bl; Mon, 30 May 2022 17:06:04 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nvgy4-005TI5-CP; Mon, 30 May 2022 17:06:03 +0200 Received: from mfe by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nvgy1-005Be8-Ey; Mon, 30 May 2022 17:06:01 +0200 From: Marco Felsch To: robert.foss@linaro.org, laurent.pinchart@ideasonboard.com, jernej.skrabec@gmail.com, jonas@kwiboo.se, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sam@ravnborg.org, maxime@cerno.tech Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, kernel@pengutronix.de Subject: [PATCH 5/6] dt-bindings: drm/bridge: ti-sn65dsi83: Add reset controller documentation Date: Mon, 30 May 2022 17:05:48 +0200 Message-Id: <20220530150548.1236307-6-m.felsch@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220530150548.1236307-1-m.felsch@pengutronix.de> References: <20220530150548.1236307-1-m.felsch@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The bridge device can now also be enabled/disabled by an external reset controller. So the device now supports either enable/disable by simple GPIO or by an Reset-Controller. Signed-off-by: Marco Felsch --- .../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml index 7306b9874dc3..eff8360c184e 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml @@ -35,6 +35,12 @@ properties: vcc-supply: description: A 1.8V power supply (see regulator/regulator.yaml). + resets: + maxItems: 1 + description: | + Reset specifier for bridge_en pin. This is required only if the brdige_en + pin is connected to a reset controller. + ports: $ref: /schemas/graph.yaml#/properties/ports