From patchwork Tue May 31 13:50:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88EA7C43219 for ; Tue, 31 May 2022 13:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344889AbiEaNu4 (ORCPT ); Tue, 31 May 2022 09:50:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344867AbiEaNuo (ORCPT ); Tue, 31 May 2022 09:50:44 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC0F65AA79 for ; Tue, 31 May 2022 06:50:40 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id q7so7831344wrg.5 for ; Tue, 31 May 2022 06:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cScg/ppMZgoA29VxGDOmoca/GEpRNiY6uz4ypL3t+ho=; b=zwHfoJRh4qEpqnVW4tO8Ww9mFoI0xkeYeX75NLKUzehMYnvddYiXCNrP2wQktLHmL4 xUHKKb7OGLzcssDx/jyB4RczL28TaZiSTc9JCpmzDJYjcwk/WdM34S2cFCTARqFkGFl1 LdctYQzJ9woSuCXBJJsxCZRZHlDhQYnY+IAfX3K1OOxNV0l0E0RleUd2ISc2Rgk1qo4K fJhqz0GMYoawCe4viZIZ0erbtsOEipTnqJ8vO42ycO5gH009W5gktb3F6y4C7C3zfS+j 5f6GW9K2Xo/l6wVaOyzBpfe3OMOKhDMwN9sL4RSAhrtp1Bm0pcpeYrF7Ky+FohTwGoxI YHKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cScg/ppMZgoA29VxGDOmoca/GEpRNiY6uz4ypL3t+ho=; b=l4/A0UQ9zOlJkqJ1mP0JdYivmd6HtcSAvqkfYe2xOTRDWlg/ojxFNWR1IcmeYgfgjP RVyukf6wBGpghMPeVtfN4wTi9e5dbq1To+EuB50kTLe/Cnt5f65ym//tO4q1kY7LDlAa MnRGziVhZwhehKaSK7g1Ef8GxaaJPOvuFfFZoFW4tSNr34/5Uq40HLLhI1ZcmzgzeJ9A J8/wCkRinA166K3VApWnvTBswC/5nZlhSoj/UmOcATgzInbsv9YRy3L+boejGcHdU5uF Yy7zWIsnBg2IEd4zpwESn8fupkWM5e0Yagc56IJDuWdonIirg+0gEUh9v5qbGoWYJt46 AZ/A== X-Gm-Message-State: AOAM530gdY7K96kchyYZzNh5q09HW7Yu0DhiNqWB/klYNggHSKSkJct9 gXJmqWySmou+q9fx7FtUbbCezg== X-Google-Smtp-Source: ABdhPJyHAelw16D3P0Yimp6zHFw2pjrB1y1+t5Sxv+QQxbBuBodm5ZmZ3Iw3GAh8m1iPVVk6MgPgrA== X-Received: by 2002:adf:d1ee:0:b0:210:d63:6570 with SMTP id g14-20020adfd1ee000000b002100d636570mr20704871wrd.673.1654005039097; Tue, 31 May 2022 06:50:39 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:38 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent , Rob Herring Subject: [PATCH 01/17] dt-bindings: i2c: i2c-mt65xx: add binding for MT8365 SoC Date: Tue, 31 May 2022 15:50:10 +0200 Message-Id: <20220531135026.238475-2-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365 I2C controllers. Signed-off-by: Fabien Parent Acked-by: Rob Herring --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index 16a1a3118204..a6fe0d8b0cbe 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -43,6 +43,10 @@ properties: - enum: - mediatek,mt8195-i2c - const: mediatek,mt8192-i2c + - items: + - enum: + - mediatek,mt8365-i2c + - const: mediatek,mt8168-i2c reg: items: From patchwork Tue May 31 13:50:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 578006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2C98C433F5 for ; Tue, 31 May 2022 13:50:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344905AbiEaNux (ORCPT ); Tue, 31 May 2022 09:50:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344894AbiEaNup (ORCPT ); Tue, 31 May 2022 09:50:45 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2F115EBC5 for ; Tue, 31 May 2022 06:50:42 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id d26so13180932wrb.13 for ; Tue, 31 May 2022 06:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GdLebb0hcqumk+5oPRll761fGotaeHJ+s+cQnmwt1xo=; b=vvDy6XluCcZHIaiVjMTo9e2czawjGc4AH938vW1pCzEcW7kbxITyawjphD4EV/7vDN evc04Bbu01AxfCOacWkePRVHGvLcgU8FjxYfGe28i3qOevr+sFvsloQ5zQnu1MiWNtp9 wBAa00iDuFO00vXE9tuUDKf+8yFB7Otyji9C0BH4UBBYCvCPLHIvMPlNpnE1di8tMbcv Yc3nn94Mngd8+f5An0MCY5JQ+c6oCIWT0W/aF9xDx91B2zFOMxYepU0t+P9d7IR/dHqb dD/UeFvwFgVP7F8Ff+5GEwn+qJd5uucYG3s47GiUoWky06YiKrLkNXu/2bqq0KlPsqHJ X7Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GdLebb0hcqumk+5oPRll761fGotaeHJ+s+cQnmwt1xo=; b=JK5tT4UN61FBJLtxST2Kxy4xf+NY5NuvuRnnJUJX7jr4Qq4KUFFfV357EBbdVQWQTJ iamLBiTkb5eiDwyuO6ADtrKbN1dsMkjdw6Uxo4zIPxzLeEVrUEvcp5IMxvXxtkGOHoG/ 2FD6smPj2TqJkV+qykIkFUbXmPr8aGt0kTFAvy8p6kOlzQ7uRtTvuTB58kWFPf3USpc1 Wf2Obm1Xmz/trixbipdqGaSIhKmciYHkkJ6MlanFjwmMn1JywENpZ7bIVvn3T/tfGN5a KQ3gzqGhikGlpZkmjJz6Jki8mzN9FP2KEL90BdXhzw7/IGsjSsfJFGpYiSdS/2Lr7Y2l Ny9g== X-Gm-Message-State: AOAM531Kd0CsuohzxYoqtLLi/4kkShoP5YhftrbBy3N7ONP5IQd+Iicy MQTNhvwSdKqM4I7aHHg94Uefow== X-Google-Smtp-Source: ABdhPJzwij5huFbgeVoSJeVbVzYQRkcylviSsOwOJ7GzYS2+JjN4sQ22PXZUOKuNArAQHL/NOyjV9Q== X-Received: by 2002:a05:6000:1548:b0:20f:c4e3:637a with SMTP id 8-20020a056000154800b0020fc4e3637amr40373733wry.513.1654005041269; Tue, 31 May 2022 06:50:41 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:40 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Yong Wu , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 02/17] dt-bindings: memory: add mt8365 SoC binding documentation Date: Tue, 31 May 2022 15:50:11 +0200 Message-Id: <20220531135026.238475-3-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add MediaTek SMI bindings for MT8365 SoC. Signed-off-by: Fabien Parent --- .../bindings/memory-controllers/mediatek,smi-common.yaml | 6 ++++++ .../bindings/memory-controllers/mediatek,smi-larb.yaml | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index a98b359bf909..e1029ac99ab4 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -46,6 +46,11 @@ properties: - const: mediatek,mt7623-smi-common - const: mediatek,mt2701-smi-common + - description: for mt8365 + items: + - const: mediatek,mt8365-smi-common + - const: mediatek,mt8186-smi-common + reg: maxItems: 1 @@ -130,6 +135,7 @@ allOf: - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp + - mediatek,mt8365-smi-common then: properties: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index c886681f62a7..815d87fc64a0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -32,6 +32,11 @@ properties: - const: mediatek,mt7623-smi-larb - const: mediatek,mt2701-smi-larb + - description: for mt8365 + items: + - const: mediatek,mt8365-smi-larb + - const: mediatek,mt8186-smi-larb + reg: maxItems: 1 @@ -78,6 +83,7 @@ allOf: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8195-smi-larb + - mediatek,mt8365-smi-larb then: properties: From patchwork Tue May 31 13:50:12 2022 Content-Type: text/plain; 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Tue, 31 May 2022 06:50:43 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:42 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Wenbin Mei Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 03/17] dt-bindings: mmc: mtk-sd: add bindings for MT8365 SoC Date: Tue, 31 May 2022 15:50:12 +0200 Message-Id: <20220531135026.238475-4-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add MMC bindings for MT8365 bindings. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 2a2e9fa8c188..3195b80ef057 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -38,6 +38,9 @@ properties: - items: - const: mediatek,mt8195-mmc - const: mediatek,mt8183-mmc + - items: + - const: mediatek,mt8365-mmc + - const: mediatek,mt8183-mmc reg: minItems: 1 From patchwork Tue May 31 13:50:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84F10C43217 for ; Tue, 31 May 2022 13:51:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344872AbiEaNvB (ORCPT ); Tue, 31 May 2022 09:51:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344867AbiEaNu7 (ORCPT ); Tue, 31 May 2022 09:50:59 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D04C5562ED for ; Tue, 31 May 2022 06:50:46 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id q21so7594124wra.2 for ; Tue, 31 May 2022 06:50:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uV55XMdMMXm/8YBcA+hYcRdN/Sy/q9ytKejpU0TX1a4=; b=ydZ0fPc4/noMrgY/rszzHccN97Dm96R2jV+wrzbjo52SSgkXsjX2+EmRB8HsR5XPRy OVhxeu+TgJKJQmJ8ptz4ZS7KSw34lKfJHR/Oh1KxcrGhn/iCWSi/i3mbLTb8GgMD5vo4 pr0FmYobyv9iFimX2s+CYCufeQZNf5yKkJ6M6nUmnNbMUbsURMc58EQ4rsJoD++egq8e XahX6EwRKB1QJ10UyGUAm9BQzptgx5KvmldEadtAjoKFX5UJv5AzOa20xrPpQB/aVtrR qLyOwm378YQrHUZMrdxvMFzDfZaVWFwOrMrwzLddQGIhcZrd9/nkoQi88OD6OFhcqZvG /tww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uV55XMdMMXm/8YBcA+hYcRdN/Sy/q9ytKejpU0TX1a4=; b=D2K7q9n30y5n2suyf/VOuEPfBFEKe+0nY4DabU4z/BwYPx2QLGAGsZQS9eStibteoQ 11VTGpEBZSEk9uKFciVwUMBbNBapbWa9aJg8g21EoBKFUthtOpWA2lxDisLdgLi9ho/6 /nh4hojOvKGILWEBzJyN7pFrW66bbupwGgAW3hhIEEjuG6vzJONg+i2XSLWyX7TDj7E2 xoxZcJDHAjA1GdeaHvWu+Y2R0CYwLAmI3r4DqBSPLbuUsNHri7G6HAwCMITwLaMVnkv/ 6fnlqTsFR3AiU3aE5tXtdaE5YgiN7BYIluc8cc8mVOp9sI9CeHbD17wvmRCBCUaJ3NdY 1WaA== X-Gm-Message-State: AOAM530f55RnmdPlX83ZaCMYkm9D74QardrjP9fqTRWgB3WRGvs4UQ5Q UZfyCFxGy3U+AVtOzezJ9Ap87A== X-Google-Smtp-Source: ABdhPJxv8/PQNV+ezFLIiwnnP78JfWw4efymnBcIzCpOQsc85VBTswc/napM3IwCND/u1AFwGmeM9A== X-Received: by 2002:a05:6000:1869:b0:20f:c1a4:111 with SMTP id d9-20020a056000186900b0020fc1a40111mr43818748wri.261.1654005045408; Tue, 31 May 2022 06:50:45 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:44 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Sean Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 04/17] dt-bindings: arm: mediatek: Add binding for mt8365-evk board Date: Tue, 31 May 2022 15:50:13 +0200 Message-Id: <20220531135026.238475-5-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365-EVK board. The MT8365 EVK board has the following IOs: * DPI <-> HDMI bridge and HDMI connector. * 2 audio jack * 1 USB Type-A Host port * 2 UART to USB port * 1 battery connector * 1 eMMC * 1 SD card * 2 camera connectors * 1 M.2 slot for connectivity * 1 DSI connector + touchscreen connector * RPI compatible header * 1 Ethernet port Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 4a2bd9759c47..a4b1288fa837 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -216,6 +216,10 @@ properties: - enum: - mediatek,mt8516-pumpkin - const: mediatek,mt8516 + - items: + - enum: + - mediatek,mt8365-evk + - const: mediatek,mt8365 additionalProperties: true From patchwork Tue May 31 13:50:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 578004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 922B0C433FE for ; Tue, 31 May 2022 13:51:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344990AbiEaNvN (ORCPT ); Tue, 31 May 2022 09:51:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344941AbiEaNvA (ORCPT ); Tue, 31 May 2022 09:51:00 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8A6555373 for ; Tue, 31 May 2022 06:50:47 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id e2so18821677wrc.1 for ; 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Tue, 31 May 2022 06:50:47 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:46 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Long Cheng Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 05/17] dt-bindings: dma: mediatek,uart-dma: add MT8365 bindings Date: Tue, 31 May 2022 15:50:14 +0200 Message-Id: <20220531135026.238475-6-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation in order to support the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index 54d68fc688b5..19ea8dcbcbce 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -22,6 +22,7 @@ properties: - items: - enum: - mediatek,mt2712-uart-dma + - mediatek,mt8365-uart-dma - mediatek,mt8516-uart-dma - const: mediatek,mt6577-uart-dma - enum: From patchwork Tue May 31 13:50:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D978C4332F for ; Tue, 31 May 2022 13:51:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344957AbiEaNvP (ORCPT ); Tue, 31 May 2022 09:51:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344963AbiEaNvF (ORCPT ); Tue, 31 May 2022 09:51:05 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E319884A26 for ; Tue, 31 May 2022 06:50:50 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 67-20020a1c1946000000b00397382b44f4so1242170wmz.2 for ; Tue, 31 May 2022 06:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U4WzI4lbMxsj2AcBZqR5vJfiFGZXQzAZrwPqRI3jHz4=; b=b2zDiF5YOiseW/nuXuuY1Fytkg1NjykULZ6Hq3k0ECX4k4blxfNvKM85svhajUrUv4 NMas0MJxswcK+uegrqPPzB+9HpE3HDll6zuJdAy0cKDy5dVGjHGRK8oVHa8SK9OuZyq9 ZklXo6kN4SPbHbg8jAVuW61GvMcabXOc68x6JuTtRtmt6IpQlp5Vsp9PTkVYp/6Zh+S2 3m67s1U9KYXFLM/NUMcMHxW1UjHZLLpNbL7KpwiyWIMg6TafVndkF7il3GILAPgr/QVl c/zKokPzg1iagW/fjsvVLJVcdmIGNn/ZaikG9L7yUR/uBLIWUok6ifW4BBpNy8mlRid7 HKPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U4WzI4lbMxsj2AcBZqR5vJfiFGZXQzAZrwPqRI3jHz4=; b=U9QMXO0X9rSm1Ybetgkthty0drJ+x5SaaKNbGs8R+OHbRRy3p0ieqpu+W7pmk5gPIf rOalVMgzfYumBObT+8JpZrv2Nnf2zVkMMWLhPamZ7jhCHRZF9mzNDT8ZeBYDjV5N3Ecl Ko5sjv9xPBWz8oqdZGCDnRMM5ORsAQWnm5jHh93kmGxWiarbRT2VSWkQw3ArHSuY/WTF tkQIfmA4R3x5n2Hu4W82ZKrBkZAk2mXqLt5l1egxI83Plif7JV2nxBnlAe7DVkBOX/fD s31qdH1ou+gNpDxIVqxhs4g4/FwsI1SxUeYNjWAFExWHksYNyaVjRFbAymXWAHVF5D5h i8JA== X-Gm-Message-State: AOAM5317I7jXHd3lYxQBKvf4YrW0P97+U6qiUG8rUJcKPceZKSuufZh5 cEMKPG/XVRXo65iksj8j6zDRb73jcyCXMezE X-Google-Smtp-Source: ABdhPJyi7nZ5n+1hvGyQP/JdQ+9YpIzvsYsMnZlfaurRInqkxVdBqpLhXF6CQGT2vWAFmxAa1ycrnA== X-Received: by 2002:a05:600c:3c90:b0:39c:1f14:d2ba with SMTP id bg16-20020a05600c3c9000b0039c1f14d2bamr157154wmb.43.1654005049241; Tue, 31 May 2022 06:50:49 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:48 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Lars-Peter Clausen , Zhiyong Tao Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 06/17] dt-bindings: iio: adc: mediatek: add MT8365 SoC bindings Date: Tue, 31 May 2022 15:50:15 +0200 Message-Id: <20220531135026.238475-7-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding for the ADC present in MT8365 SoC. Signed-off-by: Fabien Parent --- .../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml index 65581ad4b816..364a23be73bc 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml @@ -37,6 +37,7 @@ properties: - mediatek,mt8186-auxadc - mediatek,mt8195-auxadc - mediatek,mt8516-auxadc + - mediatek,mt8365-auxadc - const: mediatek,mt8173-auxadc reg: From patchwork Tue May 31 13:50:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 578003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1069C433F5 for ; Tue, 31 May 2022 13:51:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243421AbiEaNvq (ORCPT ); Tue, 31 May 2022 09:51:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344941AbiEaNvO (ORCPT ); Tue, 31 May 2022 09:51:14 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FDFC8FFB2 for ; Tue, 31 May 2022 06:50:53 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id m32-20020a05600c3b2000b0039756bb41f2so1245626wms.3 for ; Tue, 31 May 2022 06:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7hTkqdJSG32FEC0xJwQxsGaVxXfP9pn5uHosSEpvk/o=; b=8V4VsGA9OVOOn0SdJ25JIZGwaIM5LceU5cEeIikivz49vnnxZAGp7IY4ojZQryeGnJ DP2gZq2HIx2X9KjjPP97ub/aV8GnlaIzRYU2dyi4ll7AaU5prn6VHbRNOuIWY32qdXGP lfSx/5pavnyO2+V0r85FCrEZZcgYKBajNvaAwL2INiM/VWtWvlm85BJkhIyhGFv2WlnA bgv9mq8TOvr/DR/S/KyRMtMk/feIQVxxIsgVxNxdt57BbR1t/pFrt7PFL6/ATtanGSR2 VQ114YE12cjm+Zs5zQGB67fBgQPSdash0s6aDAcmmp0Efp6dbTMc/oGaq8ZPhlmKU1vA No1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7hTkqdJSG32FEC0xJwQxsGaVxXfP9pn5uHosSEpvk/o=; b=2PYnNrfMMMex+18Ue5+Rwfg16ePpQqj5HcVOVJwmkzsmxMyZO1umXKyU35GZlSP/Wn Fn/ctYAACw49mU7qG5njHAELyd0UwgDfdQS0153N89WDYlCkjpP/eJkrv5ZM4O5BH0+D wY1yEa261X6fiBKgsGSNT1hX5kSUbtykm8eqal2Q2NvXiW+kF5mINFWWA8aL5ioPwQS9 vIoyidCl0JeymH2IAwDG7VZFt0YrNACr/V+OKSwbJmSiVPedh9VHDqxIvPXLEfyPRvXw n/gBGOuc8kqcPPwPGJvfNA+cW9Oyz3AvhZ7kPoBsO5bO3qbvUGhFlG5ajUrrQFAeItJ9 gKAg== X-Gm-Message-State: AOAM531D6mmmkFERFjeN+wY5pr7LU9jqs7FHNmxwBRoZqWXwuq3J5/Ga 7RB9APkBhQD/5qgy4oUQaGE16g== X-Google-Smtp-Source: ABdhPJygJdWIMEqnFljSCeHyRbLD1v7vofyqs6EKiM1gktA+EiK+fDFmHMqxmTLq4ylJWgeaim7/yw== X-Received: by 2002:a05:600c:354e:b0:397:7c1c:5b66 with SMTP id i14-20020a05600c354e00b003977c1c5b66mr23408175wmq.142.1654005051142; Tue, 31 May 2022 06:50:51 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:50 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Andrew-CT Chen , Lala Lin Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 07/17] dt-bindings: nvmem: mediatek, efuse: add MT8365 bindings Date: Tue, 31 May 2022 15:50:16 +0200 Message-Id: <20220531135026.238475-8-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add bindings documentation for the efuse driver on MT8365 SoC. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index 7c7233e29ecf..444875264493 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8192-efuse - mediatek,mt8195-efuse - mediatek,mt8516-efuse + - mediatek,mt8365-efuse - const: mediatek,efuse - const: mediatek,mt8173-efuse deprecated: true From patchwork Tue May 31 13:50:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0BC3C433EF for ; Tue, 31 May 2022 13:52:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343806AbiEaNwi (ORCPT ); Tue, 31 May 2022 09:52:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344995AbiEaNvO (ORCPT ); Tue, 31 May 2022 09:51:14 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C691F9159D for ; Tue, 31 May 2022 06:50:53 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id q7so7831344wrg.5 for ; Tue, 31 May 2022 06:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=poEfxrglOPRvGSjuKsP/EkFpCQGyu08L1eg/xjf1B1Y=; b=aHmuwAfSfJw6Mefu9ShhCni9jlWFc+9ZC9ROtMspcijeIrK4NW2NnFHPjuJNB6UnqY fbWvMizollAHpP4g1wiQxsHcPAEufWVY3Q4ZOaALL1x46y+ayC0kMwl3y50W0tLYinnr DA80hwBPdL17pWfSPFvwTEsv/ZjHjV6UvnjTBCyzpSYbQEyCVJ54PJpuaqP69QdDR2vb gzBoG9139g4a6k4E3Vmb+/SWrzsVqFxrjQzjEKsnmPqEtL/2jd0IVfoxtnmFeFHVNsMv DSidPQzDa8RiBW6TyVqha6BIvBOaxjN0Sj1OpD3TogJqehwGY2CTnXvMD3Gez73Jc5Z7 AemQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=poEfxrglOPRvGSjuKsP/EkFpCQGyu08L1eg/xjf1B1Y=; b=2SDWDAz5u5FtOOvOxu2J7LSpAcFcJ5qOhxNY/9NZ4ss3hcgT4Qax5O8Imy/e8u5Qvq 1AHfgYVBSZc/ojUZpyGdSfyGbEMVg031oEg+66P/X2XSsWOWudVpKpu+2a9oGxHJqEjk bLr7P0zZSe+R0mTvVFwY5DoBgMx+jKLxjLC5PVywyZM6KDnfH2MrW6ADidgmCIt0UYLK AG3n6a4lHVliC72liS5vZDxAgfnAnKDfmvLAmBW9IHounTi6rnufgxC1iyjHD1rgdDJ8 J/zEfosyFpl0qkXzHgaCNZ8EfB44l211RG9aLo8M3aQLDO/WPjsmSDdMEI8o0Sml8CoU C0+Q== X-Gm-Message-State: AOAM532aDRmmCIfZJsv4ffUiG6h/ForNC5TzHzK2MbLtA/zd6YcuhjTX magTsLc2IdxL0Tb2wQ87cNQWZg== X-Google-Smtp-Source: ABdhPJykTBwGPKug6M1MqnHyEK7Ev61BplKNaormccadnbmARRHHBqjjm4OJ28cN7w83/dZOCJCd0w== X-Received: by 2002:adf:cc87:0:b0:210:307b:2ec5 with SMTP id p7-20020adfcc87000000b00210307b2ec5mr9747075wrj.98.1654005053251; Tue, 31 May 2022 06:50:53 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:52 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 08/17] dt-bindings: watchdog: mtk-wdt: Add MT8365 SoC bindings Date: Tue, 31 May 2022 15:50:17 +0200 Message-Id: <20220531135026.238475-9-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index a97418c74f6b..0e63c4ba3785 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -19,6 +19,7 @@ Required properties: "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192 "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195 + "mediatek,mt8365-wdt", "mediatek,mt6589-wdt": for MT8365 - reg : Specifies base physical address and size of the registers. From patchwork Tue May 31 13:50:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 578002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2496FC433FE for ; Tue, 31 May 2022 13:52:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345138AbiEaNv7 (ORCPT ); Tue, 31 May 2022 09:51:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345026AbiEaNv2 (ORCPT ); Tue, 31 May 2022 09:51:28 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E564C985B2 for ; Tue, 31 May 2022 06:50:56 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id k19so10607720wrd.8 for ; Tue, 31 May 2022 06:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lW0yAksGLkkUyy22NDdYQDHyZq2zc0vWqxg9iWVW56I=; b=0Rpx6jMIsXbKBWz1Z4MydcV9MC4lfQ3IYbK0315TxxRiBKVFtYDLzjN7CG4UB2UfWq 06uhmo1Q6/Mi1Jb09Hw7bavVWC473lzLKiVfHrsQ5in01UXAMACueQStByBDdPzDrBqp twnBLWRJxnAEiZ0+mPXx6cIxmUygABTTEFKvNZa/MjJr/Y2grABaHGjDVverTv4ebyxt TnzynXxR7yWbhOz4huGXpOoRp1SIMztgg1r5aLLCiQ3CmPtGzWQoJt1KE4PCgOXkFwQg zaN3g5ow5FcEEOLYDOomGD2Td/iJJorkSyXXnQpmbUAJFuBArGG5g3rkIgU01hKSc2lm Z3uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lW0yAksGLkkUyy22NDdYQDHyZq2zc0vWqxg9iWVW56I=; b=AJyMM2F3VmX3ZDijSQWQmByiQVABSdorjiumpSm3+TrO5TX/oUlhJDhjqUQYFqrEOX tYWmCaMAis5N0celjrlIIwMEvCXWdmYwrs1l5LUEscn/S0hC5tz9Zr21n6hcPPZxAAJB TGPAdMPOf0vye1OYEpSvTMCfYH0PluixgnbGho3bfopKPnvYnulSiEGWaRUnIRxOZi7L /9EQhgI6bVm/obffscnUz9kxP6WoSmcfTqWZq61uWnmU1ggegpixCFpH5bjlMmVcICLp OiOh2cN1jbObqyBnsrHBXZOBcuLDvFdYvD6YzJBE8GIddiJCMmFpVjJ6MrL+DFGAcRhR pkBA== X-Gm-Message-State: AOAM532JfXpFyZctxoLC2zejRvZRfrtBcgIx2yOt9Of1dLHFySWI0Xi/ NYQPQ7Kc22IeonFYGOCosgGA7Q== X-Google-Smtp-Source: ABdhPJx92GIJhNJSvoi0FLCIeGZ8dl9Y3pv8+Zk660zC6fx9w1PvGGZpm6/Ia+aYM0mB7Jhr4qPWOw== X-Received: by 2002:a5d:448d:0:b0:20d:744:7663 with SMTP id j13-20020a5d448d000000b0020d07447663mr50722292wrq.654.1654005055117; Tue, 31 May 2022 06:50:55 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:54 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Leilk Liu Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 09/17] dt-bindings: spi: mt65xx: add MT8365 SoC bindings Date: Tue, 31 May 2022 15:50:18 +0200 Message-Id: <20220531135026.238475-10-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml index 94ef0552bd42..d3d34a3a0b7f 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml @@ -18,6 +18,7 @@ properties: - items: - enum: - mediatek,mt7629-spi + - mediatek,mt8365-spi - const: mediatek,mt7622-spi - items: - enum: From patchwork Tue May 31 13:50:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 578000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A202FC43219 for ; Tue, 31 May 2022 13:52:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235486AbiEaNwc (ORCPT ); Tue, 31 May 2022 09:52:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345029AbiEaNv2 (ORCPT ); Tue, 31 May 2022 09:51:28 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F6B9985B5 for ; Tue, 31 May 2022 06:50:57 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id p5-20020a1c2905000000b003970dd5404dso1258088wmp.0 for ; Tue, 31 May 2022 06:50:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wl0eUhfQkf22AJDmTLSjt67Vrs4AO/BddtK22iFmA/I=; b=YZO96mhcYG0MG87d8UPaolLiT4EBhzbYR+2tvzycFKH95/lqHD4Jvzk66jQVmww9GM Kfuya/cPBUoxIoak9XlXW8H5NmofpLD8gqIUsA33sVyo/Yuc72GVVUFaMBT1tI9z/EKt NS0T+fZwjd0jYvUswsjsKudEOEmH7IyunZjW0vI6BwdFL1QiOfrQQQndMC6y+6yEGjoo WUJ3xntSihv5qvWX5bY6EsT4t/XTIGneUSkxDd+JFVeUG0kyU5v35dRrRxEPhkSvKohE Q/wmLZ/0Dfhgbn0UZjwaY0AWfzaLcCmgbdayY/VxweaTPGhE8DjhUj3npWKQfucbxM0R 2K/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wl0eUhfQkf22AJDmTLSjt67Vrs4AO/BddtK22iFmA/I=; b=tWp8qq9DHaNAfLKWi58DU+1xCmUFuFBCVqTZWUv0NkUK9T9mwcjBHlIGAnXDtJ96R/ UUTGn4HhiRK+E62n7OhgmkA3FhqGFnQGqP4jKHcMu9rpRDmOD2zOdMWvX/Njsht2boYq HI8W/AhOkH2+AlLqmNXLx4DF81ysi6aNPFGe6s4dhfVSdZX/2Jdx0M5qpExs2kuq2Ynh +Mm8rkR9Wp0qYz6Ww+N7o/X7ln+vaIqaRTieIGYtm9UPnM3kE9wh/7EhHBEz7MR1K9nv MXkIKQ/C+5yufVwIaTj/Y1U68c7VsPX4fscJnZC/DeiLpQ2YpW0N/oYw9PKuSKezEqWc pNsw== X-Gm-Message-State: AOAM533oT3aEIb0Aa0suTkVfR8quoqADMu1ZZkC4/aG9xOXKB6Ianb7f oz/qCG56bQ9RAK6/1MEJdSBrnQ== X-Google-Smtp-Source: ABdhPJzY1EA1gKYAjC0/wFLQ8zOis9WUaThFryPbsCAa6HYcRuwOQnBjCPCWIyToQh8i4anN2+EsDQ== X-Received: by 2002:a05:600c:2182:b0:397:58f5:c6cf with SMTP id e2-20020a05600c218200b0039758f5c6cfmr23289080wme.86.1654005057059; Tue, 31 May 2022 06:50:57 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:56 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Greg Kroah-Hartman Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 10/17] dt-bindings: serial: mediatek: add MT8365 bindings Date: Tue, 31 May 2022 15:50:19 +0200 Message-Id: <20220531135026.238475-11-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml index 4ff27d6d4d5b..71e78f285e47 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -44,6 +44,7 @@ properties: - mediatek,mt8186-uart - mediatek,mt8192-uart - mediatek,mt8195-uart + - mediatek,mt8365-uart - mediatek,mt8516-uart - const: mediatek,mt6577-uart From patchwork Tue May 31 13:50:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63BEEC43219 for ; Tue, 31 May 2022 13:51:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244504AbiEaNvy (ORCPT ); Tue, 31 May 2022 09:51:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344941AbiEaNvr (ORCPT ); Tue, 31 May 2022 09:51:47 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BBE5986EA for ; Tue, 31 May 2022 06:50:59 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id q21so7594124wra.2 for ; Tue, 31 May 2022 06:50:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uQC4VQ4WPzHEK/K/bvUrrtdGhjy2EyWTwZNKtRp+iyw=; b=3zIN1i390joEcWbbq2lEOHhXMbqplBLfG3SD7Gn+0anr4jkoPd2gwnoMEaZyMG8yla 79QJeDtdsmbhvTN0aVi5ShWLg923FwOfwzsJscVxwTBck9XRvgDLMf1YBLIGIMtHLxp/ 2fx/3yU5USgbjMKAZuKyerFEXHn9DkEkkIQcxl7/VfGcrIpsxQUqsiMBkPIUbw5ELdWP LaEcasNOwwN6Hgwjt+9noUuQw6IjSIkKmqo07es5YJAW1c2FQFNg2FXnXV8QrSZU7KcI E/wqN9qZKk0nK7AO5t9fdLwAoMhU9MFxIRULSYgcApWN7dji4+sJeKwaQnjXe2jGwzNH ekoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uQC4VQ4WPzHEK/K/bvUrrtdGhjy2EyWTwZNKtRp+iyw=; b=CHG2hbK/YiUpFP6qya9Mhfjb+G1cC2vzkmfqmygrJ9+qQri8hz+C83kPKYEWJFOeaw YvdPz0tefMiDhDGR+MlhssWpolsAC/YuBNVZGUriAoXuzWZkZMU/tZRRD96OJfnaT2xx OmTYG7VX0+uPM4lQeOKy4MvkCAviY7sI73bg8amavufHMa682u08pTUdMSlSUopY0A73 YlKJQcsOEZXikLC6LkrlPzIbjIb87TT7IeoKbNxfQeiclTaAiMBdSxvgjCjSb+IdtkIS CtSUD/GjW7gukmaTjjukiicKWR74GCLDTqlnoluELlV6GsCZKOU9Hq6C4s+jymKAq2R2 wWzA== X-Gm-Message-State: AOAM530E9Jjd8k5LubFKckT3lerYm/vqnILBKWUzQF2kRCxOqAU47DHy OC+SvtO3+2rrtC0CnF6PZSXKTQ== X-Google-Smtp-Source: ABdhPJzt2aaYFVPwdsiueoPDpTiBXsJc2pSW2BEWEyPMk06DY6DCbjp2yLb2MuUyFpuwoIgosOJPOA== X-Received: by 2002:adf:ed86:0:b0:20e:6f48:a194 with SMTP id c6-20020adfed86000000b0020e6f48a194mr48087877wro.290.1654005059022; Tue, 31 May 2022 06:50:59 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:50:58 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 11/17] dt-bindings: phy: mediatek,dsi-phy: Add MT8365 SoC bindings Date: Tue, 31 May 2022 15:50:20 +0200 Message-Id: <20220531135026.238475-12-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index 6e4d795f9b02..9c2a7345955d 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -24,6 +24,10 @@ properties: - enum: - mediatek,mt7623-mipi-tx - const: mediatek,mt2701-mipi-tx + - items: + - enum: + - mediatek,mt8365-mipi-tx + - const: mediatek,mt8183-mipi-tx - const: mediatek,mt2701-mipi-tx - const: mediatek,mt8173-mipi-tx - const: mediatek,mt8183-mipi-tx From patchwork Tue May 31 13:50:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92A04C4332F for ; Tue, 31 May 2022 13:52:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345052AbiEaNwa (ORCPT ); Tue, 31 May 2022 09:52:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345060AbiEaNvs (ORCPT ); Tue, 31 May 2022 09:51:48 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D100994C5 for ; Tue, 31 May 2022 06:51:01 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id p19so8075313wmg.2 for ; Tue, 31 May 2022 06:51:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V0mir9eT63DKpCuSFhXy2EQ9q6hMHk3Lk25p5hkr1WY=; b=dgPXuSTwBJUbGqXppjZhZZZOomCBtiDDRzWdJYbbljs4aTyDRm+Rc7yvBXo99ZlOUR U7mwFug0gjhRtdGOHx+b6JtR/f+n8/zxm2PDGTHjIPz/KhJYudpdaSA1BwC3X7i3s4Hr HDaavWH9RbL8wPJaZbnSIeRt0gsaiINZnc/ykOQ2BIYBBEtJ2fIb/S9kytfEqSzP2NbH qCSnSlzdfu5UlZu6g48e8t4J/3G6v16GoWLx/irJQpEzoh5NlHyGsJfxl0Gw80km5oQv 3ZY1xvrun6xC9e4jGwbOr1PrJsdJ5tEYLvd9Q7LpqBKpPeYigH/lFh3JFg3igrkvpwyS XUwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V0mir9eT63DKpCuSFhXy2EQ9q6hMHk3Lk25p5hkr1WY=; b=Ue8roKiKALEP0fY3o8uV1rLp7lSntGeNeIP9Zb0LoJZ22JdtjxEqZRdtRh49uOlGiD mlu87dSnTgNPijO/ZE44gd1ZSFuH8VTsmzvm0oZe29Mr99cvUJidLlHo0uORiSXdk00e 9JqZiUILW0zUrNiSah+/B6EiXRoitI0o2baikE6Kw2c/zAOVDJ+39B0Hr/MKM/bc+XtC IBVMPsTtM0xYv2e0ToXchHVumSI2eeEz2E1lgrh8GI+e0N+2HnqRkL6QjoEco4o0aE5x QpPuQZHWm7t0E9LdtjI22+Wl2aD9gbcyE+8H0YhtuCZP7T2gaJYWLj853S3ZW1Q/bcWS ht5Q== X-Gm-Message-State: AOAM532PMrT7leRSLGvqey3npisqaliBPGmBcaudH86UF1g6t0R3tig8 v1mvhJW98RktkQZA7AttQlTGnA== X-Google-Smtp-Source: ABdhPJzCiszx6tFF9AeRKTF7WMnbdQGjSgr3MjgxoHordumIGouDeHTHRrvMyk2Xvt9rX9h430+GnQ== X-Received: by 2002:a1c:f213:0:b0:39b:ad32:5e51 with SMTP id s19-20020a1cf213000000b0039bad325e51mr10808986wmc.72.1654005060973; Tue, 31 May 2022 06:51:00 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:51:00 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Kishon Vijay Abraham I Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 12/17] dt-bindings: phy: mediatek,tphy: add MT8365 SoC bindings Date: Tue, 31 May 2022 15:50:21 +0200 Message-Id: <20220531135026.238475-13-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 7b2e1bc119be..4b638c1d4221 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -82,6 +82,7 @@ properties: - mediatek,mt8183-tphy - mediatek,mt8186-tphy - mediatek,mt8192-tphy + - mediatek,mt8365-tphy - const: mediatek,generic-tphy-v2 - items: - enum: From patchwork Tue May 31 13:50:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D46ECC433F5 for ; Tue, 31 May 2022 13:52:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345071AbiEaNwX (ORCPT ); Tue, 31 May 2022 09:52:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345074AbiEaNvt (ORCPT ); Tue, 31 May 2022 09:51:49 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F083994F6 for ; Tue, 31 May 2022 06:51:03 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id s24so11460976wrb.10 for ; Tue, 31 May 2022 06:51:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3wGkmcChS3N6J5I1U5dOklUlfdbKJPPT1/iNxESisgg=; b=fikIkFwWuhYcaTcEmINCMiakOznAvwOTyoARO2Ked0fxXRKlokFWxS4v+L3ZHkVXNE KJo6JQRplqeWtr7bcHSDaD9wimVN6J5/aFLVwkOlxuupl3wfaWdmJLh5kAYbdtTckmjS 7ZGd0V7af7yBcvxj28ftOe7vntKmkUDl58co3QLQMh7EDttwJw6VIn65mWVSUtVSY17w C+pC6wz1nhlOvs9cYDgkL55ay0oOBepTQ5OOmFShvRgJzHHRi41+K+1jqITOGGjVGPtn sjkv7Mviq+G4VnQO6P1IU33v5RSiZUvtdFZ0EWYtGwnjrF0dBp7r7qRY6vrkRwHkHUXK npvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3wGkmcChS3N6J5I1U5dOklUlfdbKJPPT1/iNxESisgg=; b=cJImL5oSQvGIXUSR6LfI3kxAkH2y5aB7A0zAqMxjjIcw8FYXcq0pqtBiDiamZK+NUd LxWf6BhbU+wcEGqpCtzp03Hefg1HTi93hG/L0gvtNA4SS1U0CDFquhC0TnCZpyHmimq6 Dk2piC+tkxSbT6/x8R57QCDlf0a3pukLS3G/2ce+OXKD/UYRT99ycF2qSI9bEcpVViAG zZAWD/49brLB8kiEzyl+qFBIZ1QQdqDXuGRGkmSX8R62KxFutA1mRAMYhIR/z7yIjwGf 5lwFJ9WQy4W0+yOHSqAfkEndxG5m2l86sVVEMkPkKnFt+GzrGrAwiTrhKvzD7iuSrJuI Zdog== X-Gm-Message-State: AOAM5305ZcmOaga2nACVcEKBII39N3Fud0yeGPCdKRlfrxUmRcsBY47x Qow1fKteCF7NSkjiJiAwYDEL7w== X-Google-Smtp-Source: ABdhPJxcPkJR1D9vj54qvl0alyjM+fo9L7Ht5RN1swDsTiyvQa4xekfb3jUiJKdRl+jEckFF9F7nug== X-Received: by 2002:adf:e0c5:0:b0:206:1ba3:26aa with SMTP id m5-20020adfe0c5000000b002061ba326aamr50251741wri.645.1654005062859; Tue, 31 May 2022 06:51:02 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:51:02 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Greg Kroah-Hartman Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 13/17] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings Date: Tue, 31 May 2022 15:50:22 +0200 Message-Id: <20220531135026.238475-14-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index df766f8de872..9ede6069d9e6 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8173-mtu3 - mediatek,mt8183-mtu3 - mediatek,mt8192-mtu3 + - mediatek,mt8365-mtu3 - const: mediatek,mtu3 reg: From patchwork Tue May 31 13:50:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 578001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4244FC433EF for ; Tue, 31 May 2022 13:52:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345099AbiEaNwS (ORCPT ); Tue, 31 May 2022 09:52:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344994AbiEaNvt (ORCPT ); Tue, 31 May 2022 09:51:49 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E3FD996A7 for ; Tue, 31 May 2022 06:51:05 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id d26so13180672wrb.13 for ; Tue, 31 May 2022 06:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F+yIDk55VuOl9cCuSgTZgPbJurzlbWspdqV8YJPygQc=; b=htvgPMPg810HOgsL/n8G+IrY6CyzUgbcv6/I4+7ytTovj325fq0rZxlNfBK0vW4cxZ dyf/Ol5KAJmMoo+mtoe9pQg/dUaVR/6Pt6UTXEVZjNmaBZvLBVhbyGexuuiR2kLNsNbz qqIE10FVgfiFvCfxWNi1gDtrnALRyhQYJuUFe9NJze697OCY0g8smzNcDk4IISkgf3gQ Xd+KrwxJ+Rlpq7XT8sg07RD2pyyxXW+HHc5rLzhGtWdYfEcwdQYYl6fYtt+EBbTNWpsA ozL8VwXPxAsUfw3sNyrqnY32vcl5ygsCmI2j8zKnVQ1fIAlOBqoyoreGhlxLkdhfmWX6 YvpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F+yIDk55VuOl9cCuSgTZgPbJurzlbWspdqV8YJPygQc=; b=QJ1ztUgNcxSksF6P8EiBvGAA+bK6XprAY6jj/RtSW1GBck2taqowpMS7YRN7SSXx7r oNpiLXaSAtH/bW/KOBB9Z/xy1M2FmsOJzyubSurS7H//8A5RtIXctzqiXhebrgO74yMQ lzF/J74J+6AXvSX4f1nC3OCL3h6gxK23+qZtXmj3LpRGwt0NvbMheP+3F09e3mWHlGF1 KqaPyI+k5I6fFO0j/XnEr9uH3VCxp/jACek0i5tkGoPfz7bBcX8FLk70TyyMr/L5p85d 8CcSCKuLVz+z0gRqk8wommz+sCiKcNGBOx7PuSwN8Mkk/1R0iYk99cWjp1UCDxk3vVu/ 6kUw== X-Gm-Message-State: AOAM53074vsoftz45h4MRMQu+/66NmxkxEDeTb7u4rHdnkkTGvv0kYlq fXppPj5QceIk9aF60qCusvRnNQ== X-Google-Smtp-Source: ABdhPJxRndr/fDoyjVrSbqXI6Y+AQpxP3kSIzUtyunLbOSK92Vlbw3Ep6IVSf+uKQoEqmyqn7EQXJA== X-Received: by 2002:adf:f405:0:b0:210:2d2d:c8ef with SMTP id g5-20020adff405000000b002102d2dc8efmr11703498wro.256.1654005064855; Tue, 31 May 2022 06:51:04 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:51:04 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, Greg Kroah-Hartman Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 14/17] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings Date: Tue, 31 May 2022 15:50:23 +0200 Message-Id: <20220531135026.238475-15-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 084d7135b2d9..65f0ce225f13 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci reg: From patchwork Tue May 31 13:50:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A0C3C433EF for ; Tue, 31 May 2022 13:52:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344974AbiEaNwt (ORCPT ); Tue, 31 May 2022 09:52:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345173AbiEaNwE (ORCPT ); Tue, 31 May 2022 09:52:04 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 169979AE55 for ; Tue, 31 May 2022 06:51:25 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id p10so18776042wrg.12 for ; Tue, 31 May 2022 06:51:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BqpZOx3pMkVOAQNQltlh6CmUED1DaV6aOqALQmMhbr0=; b=V5KO5uHzp9s6622Du0y0DXZ0jgYSd0RSHF7FMdDNrSpmwaxSJHuvsRsW2VNRNSOrSq y1EVTERgqTqh6WCBn2sK+biMlhdwtUOfHkYOUmqXbrQDQq6TzmwMWW4hoY0NxYLMZhO4 /zUBkAnzYXfWN1Faz2Htht8uMV25t30NN4Rft9LNWCIdxjcP+iALn7dnVGhi6eF+D2Ie c1wQwd04xoqHMC6impdpfDG2anes3AqwBdkw3I1EQPe7Sby21LVtVM2SUfcGLlPu8IBe xZeuyF2xsIB1Z6TwgmoiwDGkuQVf93OO4xoXfMeL7mSCgqaatv4jXFNKa+ZrohncHNl+ DqTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BqpZOx3pMkVOAQNQltlh6CmUED1DaV6aOqALQmMhbr0=; b=xhUItRH4YxSA77kte8C2jEB5WNXK8S7SSJHBQn9nUEUQGP/srPXyicO6EiCpS7Pfuf Crty1bzzjl+lOPB2A+iD60sqfZ69/HWrFpNyjz7mzThFZJ/HxqmOJcuTlKEcSEhhEAyG elHBmP2n/Kw4MAvcZhNcg27SuLwgR88Dp8KJFthaAn327jgE+qaWRfuP8PBBG6JJ6FVu OXOj9E92CLcOpne2T6xB/j7aAxRxg1EIAHvfuPInd0oZRNIDQqk9HeqRqbjr6fnMDlDd ucgib9y0ehHxz9hvvCTpzwyvHzUpgPqky5tc8t3y/6UUTdurLQ97PRZW15BWE0iLI1Wf FNmg== X-Gm-Message-State: AOAM532FOpr2xQTcKdSWygP5BMCtsSTFj5BpR2FZ6eryg+0MSg7t65/c eeyvugDUpAs9AkSThQC533ZHvw== X-Google-Smtp-Source: ABdhPJwyPR86D46MqBkUm98L4oZz3ngtWZBbWNloc28wZ9CD78yWdvfkf6FMmCABZPC3ef00LuLk6Q== X-Received: by 2002:adf:f603:0:b0:210:ddf:e04d with SMTP id t3-20020adff603000000b002100ddfe04dmr21311834wrp.463.1654005066904; Tue, 31 May 2022 06:51:06 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:51:06 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 15/17] arm64: dts: mediatek: add mt6357 device-tree Date: Tue, 31 May 2022 15:50:24 +0200 Message-Id: <20220531135026.238475-16-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add device-tree for the MT6357 PMIC. Signed-off-by: Fabien Parent --- arch/arm64/boot/dts/mediatek/mt6357.dtsi | 272 +++++++++++++++++++++++ 1 file changed, 272 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6357.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6357.dtsi b/arch/arm64/boot/dts/mediatek/mt6357.dtsi new file mode 100644 index 000000000000..a28010119e69 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6357.dtsi @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre Inc. + */ + +#include + +&pwrap { + mt6357_pmic: pmic { + compatible = "mediatek,mt6357"; + + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name = "vproc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vcore_reg: buck-vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vmodem_reg: buck-vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + }; + + mt6357_vs1_reg: buck-vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2200000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vpa_reg: buck-vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-ramp-delay = <50000>; + regulator-enable-ramp-delay = <220>; + }; + + mt6357_vfe28_reg: ldo-vfe28 { + compatible = "regulator-fixed"; + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vxo22_reg: ldo-vxo22 { + regulator-name = "vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2400000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vrf18_reg: ldo-vrf18 { + compatible = "regulator-fixed"; + regulator-name = "vrf18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vrf12_reg: ldo-vrf12 { + compatible = "regulator-fixed"; + regulator-name = "vrf12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vefuse_reg: ldo-vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn33_bt_reg: ldo-vcn33-bt { + regulator-name = "vcn33-bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn33_wifi_reg: ldo-vcn33-wifi { + regulator-name = "vcn33-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn28_reg: ldo-vcn28 { + compatible = "regulator-fixed"; + regulator-name = "vcn28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn18_reg: ldo-vcn18 { + compatible = "regulator-fixed"; + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcama_reg: ldo-vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcamd_reg: ldo-vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcamio_reg: ldo-vcamio18 { + compatible = "regulator-fixed"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vldo28_reg: ldo-vldo28 { + regulator-name = "vldo28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vsram_others_reg: ldo-vsram-others { + regulator-name = "vsram-others"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + }; + + mt6357_vsram_proc_reg: ldo-vsram-proc { + regulator-name = "vsram-proc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + }; + + mt6357_vaux18_reg: ldo-vaux18 { + compatible = "regulator-fixed"; + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vaud28_reg: ldo-vaud28 { + compatible = "regulator-fixed"; + regulator-name = "vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vio28_reg: ldo-vio28 { + compatible = "regulator-fixed"; + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vio18_reg: ldo-vio18 { + compatible = "regulator-fixed"; + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + }; + + mt6357_vdram_reg: ldo-vdram { + regulator-name = "vdram"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <3300>; + }; + + mt6357_vmc_reg: ldo-vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vmch_reg: ldo-vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vemc_reg: ldo-vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + regulator-always-on; + }; + + mt6357_vsim1_reg: ldo-vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vsim2_reg: ldo-vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vibr_reg: ldo-vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name = "vusb33"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + }; + + mt6357rtc: mt6357rtc { + compatible = "mediatek,mt6357-rtc", + "mediatek,mt6358-rtc"; + }; + + mt6357keys: mt6357keys { + compatible = "mediatek,mt6357-keys"; + }; + }; +}; From patchwork Tue May 31 13:50:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01B36C433F5 for ; Tue, 31 May 2022 13:52:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344980AbiEaNwK (ORCPT ); Tue, 31 May 2022 09:52:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345126AbiEaNv6 (ORCPT ); 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Tue, 31 May 2022 06:51:08 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 16/17] arm64: dts: mediatek: add mt8365 device-tree Date: Tue, 31 May 2022 15:50:25 +0200 Message-Id: <20220531135026.238475-17-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add device-tree for the MT8365 SoC. More information can be found about that SoC at the following address: https://www.mediatek.com/products/aiot/i350-mt8365 Signed-off-by: Fabien Parent --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 1047 ++++++++++++++++++++++ 1 file changed, 1047 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi new file mode 100644 index 000000000000..e22b1d259418 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,1047 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8365"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + color0 = &color0; + ccorr0 = &ccorr0; + aal0 = &aal0; + gamma0 = &gamma0; + dither0 = &dither0; + dsi0 = &dsi0; + dpi0 = &dpi0; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-frequency = <1600000000>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-frequency = <1600000000>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-frequency = <1600000000>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-frequency = <1600000000>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + enable-method = "psci"; + }; + }; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <650000>; + }; + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <668750>; + }; + opp-987000000 { + opp-hz = /bits/ 64 <987000000>; + opp-microvolt = <687500>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <706250>; + }; + opp-1125000000 { + opp-hz = /bits/ 64 <1125000000>; + opp-microvolt = <725000>; + }; + opp-1216000000 { + opp-hz = /bits/ 64 <1216000000>; + opp-microvolt = <750000>; + }; + opp-1308000000 { + opp-hz = /bits/ 64 <1308000000>; + opp-microvolt = <775000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <800000>; + }; + opp-1466000000 { + opp-hz = /bits/ 64 <1466000000>; + opp-microvolt = <825000>; + }; + opp-1533000000 { + opp-hz = /bits/ 64 <1533000000>; + opp-microvolt = <850000>; + }; + opp-1633000000 { + opp-hz = /bits/ 64 <1633000000>; + opp-microvolt = <887500>; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <912500>; + }; + opp-1767000000 { + opp-hz = /bits/ 64 <1767000000>; + opp-microvolt = <937500>; + }; + opp-1834000000 { + opp-hz = /bits/ 64 <1834000000>; + opp-microvolt = <962500>; + }; + opp-1917000000 { + opp-hz = /bits/ 64 <1917000000>; + opp-microvolt = <993750>; + }; + opp-2001000000 { + opp-hz = /bits/ 64 <2001000000>; + opp-microvolt = <1025000>; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x20000>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x80000>, + <0 0x0c080000 0 0x80000>; + + interrupts = ; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8365-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8365-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible = "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8365-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8365_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "mm", "mm-0", "mm-1", + "mm-2", "mm-3"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,infracfg_nao = <&infracfg_nao>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@MT8365_POWER_DOMAIN_CAM { + reg = ; + clocks = <&camsys CLK_CAM_LARB2>, + <&camsys CLK_CAM_SENIF>, + <&camsys CLK_CAMSV0>, + <&camsys CLK_CAMSV1>, + <&camsys CLK_CAM_FDVT>, + <&camsys CLK_CAM_WPE>; + clock-names = "cam-0", "cam-1", + "cam-2", "cam-3", + "cam-4", "cam-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_VDEC { + reg = ; + #power-domain-cells = <0>; + mediatek,smi = <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_VENC { + reg = ; + #power-domain-cells = <0>; + mediatek,smi = <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_APU { + reg = ; + clocks = <&infracfg CLK_IFR_APU_AXI>, + <&apu CLK_APU_IPU_CK>, + <&apu CLK_APU_AXI>, + <&apu CLK_APU_JTAG>, + <&apu CLK_APU_IF_CK>, + <&apu CLK_APU_EDMA>, + <&apu CLK_APU_AHB>; + clock-names = "apu", "apu-0", + "apu-1", "apu-2", + "apu-3", "apu-4", + "apu-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + }; + }; + + power-domain@MT8365_POWER_DOMAIN_CONN { + reg = ; + clocks = <&topckgen CLK_TOP_CONN_32K>, + <&topckgen CLK_TOP_CONN_26M>; + clock-names = "conn", "conn1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_MFG { + reg = ; + clocks = <&topckgen CLK_TOP_MFG_SEL>; + clock-names = "mfg"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_IFR_AUDIO>, + <&infracfg CLK_IFR_AUD_26M_BK>; + clock-names = "audio", "audio1", "audio2"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_DSP { + reg = ; + clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP_26M>; + clock-names = "dsp", "dsp1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8365-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + + gpt: apxgpt@10008000 { + compatible = "mediatek,mt8365-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYS_26M_D2>; + clock-names = "clk13m"; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8365-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8365-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg CLK_IFR_PWRAP_SPI>, + <&infracfg CLK_IFR_PMIC_AP>, + <&infracfg CLK_IFR_PWRAP_SYS>, + <&infracfg CLK_IFR_PWRAP_TMR>; + clock-names = "spi", "wrap", "sys", "tmr"; + }; + + keypad: kp@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts = ; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible = "mediatek,mt8365-mcucfg", "syscon"; + reg = <0 0x10200000 0 0x2000>; + #clock-cells = <1>; + }; + + sysirq: intpol-controller@10200a80 { + compatible = "mediatek,mt8365-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200a80 0 0x20>; + }; + + iommu: iommu@10205000 { + compatible = "mediatek,mt8365-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; + #iommu-cells = <1>; + }; + + infracfg_nao: infracfg-nao@1020e000 { + compatible = "syscon"; + reg = <0 0x1020e000 0 0x1000>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt8365-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_IFR_TRNG>; + clock-names = "rng"; + }; + + apdma: dma-controller@11000280 { + compatible = "mediatek,mt8365-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts = , + , + , + , + , + ; + dma-requests = <6>; + clocks = <&infracfg CLK_IFR_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt8365-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&infracfg CLK_IFR_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0 + &apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2 + &apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4 + &apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt8365-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, + <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, + <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, + <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi: spi@1100a000 { + compatible = "mediatek,mt8365-spi", + "mediatek,mt7622-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + thermal: thermal@1100b000 { + compatible = "mediatek,mt8365-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_IFR_THERM>, + <&infracfg CLK_IFR_AUXADC>; + clock-names = "therm", "auxadc"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + }; + + disp_pwm: disp-pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", + "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_IFR_DISP_PWM>; + clock-names = "main", "mm"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssusb: usb@11201000 { + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: usb@11200000 { + compatible = "mediatek,mt8365-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = ; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status = "disabled"; + }; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&infracfg CLK_IFR_MSDC0_HCLK>, + <&infracfg CLK_IFR_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&infracfg CLK_IFR_MSDC1_HCLK>, + <&infracfg CLK_IFR_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + ethernet: ethernet@112a0000 { + compatible = "mediatek,mt8365-eth"; + reg = <0 0x112a0000 0 0x1000>; + mediatek,pericfg = <&infracfg>; + interrupts = ; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&infracfg CLK_IFR_NIC_AXI>, + <&infracfg CLK_IFR_NIC_SLV_AXI>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", + "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clocks = <&clk26m>; + clock-names = "ref_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + }; + + efuse: efuse@11c50000 { + compatible = "mediatek,mt8365-efuse", "mediatek,efuse"; + reg = <0 0x11c50000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@180 { + reg = <0x180 0xc>; + }; + }; + + u3phy: t-phy@11cc0000 { + compatible = "mediatek,mt8365-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #phy-cells = <1>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port0: usb-phy@11cc0000 { + reg = <0 0x11cc0000 0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u2port1: usb-phy@11cc1000 { + reg = <0 0x11cc1000 0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + mfgcfg: syscon@13000000 { + compatible = "mediatek,mt8365-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8365-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + smi_common: smi@14002000 { + compatible = "mediatek,mt8365-smi-common", + "mediatek,mt8186-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + larb0: larb@14003000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + mediatek,larb-id = <0>; + }; + + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", + "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", + "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8365-dsi", + "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi", + "mediatek,mt8192-dpi"; + reg = <0 0x14018000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_DPI0_SEL>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>, + <&mmsys CLK_MM_DPI0_DPI0>; + clock-names = "pixel", "engine", "pll", "dpi"; + status = "disabled"; + }; + + camsys: syscon@15000000 { + compatible = "mediatek,mt8365-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_IMG>, + <&camsys CLK_CAM_LARB2>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + mediatek,larb-id = <2>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8365-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb3: larb@16010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; + mediatek,larb-id = <3>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8365-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb@17010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; + mediatek,larb-id = <1>; + }; + + apu: syscon@19020000 { + compatible = "mediatek,mt8365-apu", "syscon"; + reg = <0 0x19020000 0 0x1000>; + #clock-cells = <1>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermal 0>; + + trips { + threshold: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit0 { + temperature = <117000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu0 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu2 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <100>; + }; + }; + }; + + tzts1: tzts1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 1>; + trips {}; + cooling-maps {}; + }; + + tzts2: tzts2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 2>; + trips {}; + cooling-maps {}; + }; + + tzts3: tzts3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 3>; + trips {}; + cooling-maps {}; + }; + + tzts4: tzts4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 4>; + trips {}; + cooling-maps {}; + }; + }; + + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; +}; From patchwork Tue May 31 13:50:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 577601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39993C433F5 for ; Tue, 31 May 2022 13:52:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345034AbiEaNwp (ORCPT ); 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Tue, 31 May 2022 06:51:11 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 17/17] arm64: dts: mediatek: add mt8365-evk board device-tree Date: Tue, 31 May 2022 15:50:26 +0200 Message-Id: <20220531135026.238475-18-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add device-tree for the MT8365-EVK board. The MT8365 EVK board has the following IOs: * DPI <-> HDMI bridge and HDMI connector. * 2 audio jack * 1 USB Type-A Host port * 2 UART to USB port * 1 battery connector * 1 eMMC * 1 SD card * 2 camera connectors * 1 M.2 slot for connectivity * 1 DSI connector + touchscreen connector * RPI compatible header * 1 Ethernet port Signed-off-by: Fabien Parent --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 578 ++++++++++++++++++++ 2 files changed, 579 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c7d4636a2cb7..02a9f784358e 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -40,4 +40,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts new file mode 100644 index 000000000000..8f472caa06a3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 BayLibre, SAS. + * Author: Fabien Parent + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" +#include "mt6357.dtsi" + +/ { + model = "MediaTek MT8365 Open Platform EVK"; + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + volume-up { + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&cpu0 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu1 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu2 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu3 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&dpi0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dpi_func_pins>; + pinctrl-1 = <&dpi_idle_pins>; + assigned-clocks = <&topckgen CLK_TOP_DPI0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_LVDSPLL_D4>; + + /* + * Ethernet and HDMI are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on DPI position + */ + status = "okay"; + + port { + dpi_out: endpoint { + remote-endpoint = <&it66121_in>; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + mac-address = [00 00 00 00 00 00]; + + /* + * Ethernet and HDMI are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + */ + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + it66121hdmitx: hdmi@4c { + compatible = "ite,it66121"; + pinctrl-names = "default"; + pinctrl-0 = <&ite_pins>; + vcn33-supply = <&mt6357_vibr_reg>; + vcn18-supply = <&mt6357_vsim2_reg>; + vrf12-supply = <&mt6357_vrf12_reg>; + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + interrupts-extended = <&pio 68 IRQ_TYPE_LEVEL_LOW>; + #sound-dai-cells = <0>; + reg = <0x4c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + it66121_in: endpoint { + bus-width = <12>; + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_connector_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x12012>; + vmmc-supply = <&mt6357_vemc_reg>; + vqmmc-supply = <&mt6357_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt6357_vmch_reg>; + vqmmc-supply = <&mt6357_vio18_reg>; + status = "okay"; +}; + +&mt6357_pmic { + interrupt-parent = <&pio>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; +}; + +&mt6357_vibr_reg { + regulator-always-on; +}; + +/* Needed by MSDC1 */ +&mt6357_vmc_reg { + regulator-always-on; +}; + +&mt6357_vrf12_reg { + regulator-always-on; +}; + +&mt6357_vsim2_reg { + regulator-always-on; +}; + +&mt6357keys { + power-key { + label = "power"; + linux,keycodes = ; + wakeup-source; + }; + + volume-down { + label = "volume_down"; + linux,keycodes = ; + wakeup-source; + }; +}; + +&pio { + dpi_func_pins: dpi-func-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = ; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + ethernet_pins: ethernet-pins { + pins-ethernet { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pins-phy-reset { + pinmux = ; + }; + }; + + gpio_keys: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + pins-rst-ite { + pinmux = ; + output-high; + }; + + pins-irq-ite { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-pwr { + pinmux = , + ; + output-high; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-clk { + pinmux = ; + bias-pull-down; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins-rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1-default-pins { + pins-cd { + pinmux = ; + bias-pull-up; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + }; + }; + + usb_pins: usb-pins { + pins-id { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-usb0-vbus { + pinmux = ; + output-high; + }; + + pin-usb1-vbus { + pinmux = ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux = , + ; + }; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ssusb { + pinctrl-0 = <&usb_pins>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + usb-role-switch; + dr_mode = "otg"; + vusb33-supply = <&mt6357_vusb33_reg>; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_otg_vbus>; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_host { + vusb33-supply = <&mt6357_vusb33_reg>; + status = "okay"; +};