From patchwork Tue May 31 10:51:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 578397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ED24C433FE for ; Tue, 31 May 2022 10:52:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343581AbiEaKwC (ORCPT ); Tue, 31 May 2022 06:52:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343574AbiEaKwB (ORCPT ); Tue, 31 May 2022 06:52:01 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67C1652526 for ; Tue, 31 May 2022 03:51:59 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id v25so8892471eda.6 for ; Tue, 31 May 2022 03:51:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p7mIRFKlf7mUQrcHty6Iw1fiOYErDnQJ/9BxNwewsYs=; b=TiHu58MJlYhDvueuzEoHjnSpR3Ya+RJjug8dDTTt9WjVthO56N67D8UITUHAQInfyf x5nP4VMVucwgsYbu7uoh9+CTyGV3uuTHUUuFKKE/dmrf9iWu1qBG2r3hliuSuqRSdQmG YD2OXZ0pvFK3DODLBfIVTW1xBKHdOuOrcsrHBZWdi0gK4eGOHTzQnlWxwGFdOzTrbQ0g Sj80Bl4LQgiiIr/TGn5oBSQK+ak7bcQnGqqJMWWFUWHdAvtPUs2yG2KZTcUzw893ouol C5UVNlrPYxSoqPmaJ75K0VzyIJ8KwnG/D8kEj8hPrdB3G2HWdCqbDt0iYVBm0tO+ElRA +31g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p7mIRFKlf7mUQrcHty6Iw1fiOYErDnQJ/9BxNwewsYs=; b=x94Iaxsa26WPkPz9VwKUbXm7AKX18pgT2wuBiGHh3IwjupJ6dERRj99JkdptLyDZGy ley45KIMgGpS+9/tRA2v6U4UO1dxrewL5K2f9BuFFjcaGblPkGMCkcom/+OuUL8mmPJ/ Ffm/DldKxKKhrKBYdehEJ+8bx7PCZYoNyKhFpKZF3uFlvd74NcEPOMW6KZgd3BBxPPXv 35APZjGNb7C91+HRhYZRjTZmLgjStKwvhSi95ivk0ToIiq4W6seAmJxpmUpFl7VpfX1A JAVhpusEG+pN8wo70ZdputCSIkBTeoC3Gvcs7+2wk9HhARwLhV4LqLS57o26W/uamrr4 JeEw== X-Gm-Message-State: AOAM531OfPao62KcZXGQ6s1KZLzkxgiUeGGq99/qTbCPJjNSeYDOSKoZ S7QYjrN2BZy5mzVGJJaupGmqiw== X-Google-Smtp-Source: ABdhPJwbV5+sW0Qx8vGQ9DlloXkTdOIz0AFgs5SvDYPE7n9AHH/lMowZnogwo+2y/mLUoHVo2QoiZQ== X-Received: by 2002:a05:6402:4c1:b0:42b:e03f:d940 with SMTP id n1-20020a05640204c100b0042be03fd940mr25357406edw.235.1653994318019; Tue, 31 May 2022 03:51:58 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id q3-20020a50aa83000000b0042dc513ced8sm5117441edc.30.2022.05.31.03.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 03:51:57 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Rob Herring Subject: [PATCH v3 1/4] dt-bindings: interconnect: qcom, sdm845-cpu-bwmon: add BWMON device Date: Tue, 31 May 2022 12:51:34 +0200 Message-Id: <20220531105137.110050-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220531105137.110050-1-krzysztof.kozlowski@linaro.org> References: <20220531105137.110050-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add bindings for the Qualcomm Bandwidth Monitor device providing performance data on interconnects. The bindings describe only BWMON version 4, e.g. the instance on SDM845 between CPU and Last Level Cache Controller. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Acked-by: Georgi Djakov --- .../interconnect/qcom,sdm845-cpu-bwmon.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml new file mode 100644 index 000000000000..8c82e06ee432 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sdm845-cpu-bwmon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Interconnect Bandwidth Monitor + +maintainers: + - Krzysztof Kozlowski + +description: + Bandwidth Monitor measures current throughput on buses between various NoC + fabrics and provides information when it crosses configured thresholds. + +properties: + compatible: + enum: + - qcom,sdm845-cpu-bwmon # BWMON v4 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ddr + - const: l3c + + interrupts: + maxItems: 1 + + operating-points-v2: true + opp-table: true + + reg: + # Currently described BWMON v4 and v5 use one register address space. + # BWMON v2 uses two register spaces - not yet described. + maxItems: 1 + +required: + - compatible + - interconnects + - interconnect-names + - interrupts + - operating-points-v2 + - opp-table + - reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + + pmu@1436400 { + compatible = "qcom,sdm845-cpu-bwmon"; + reg = <0x01436400 0x600>; + + interrupts = ; + + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "ddr", "l3c"; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000 4800000>; + }; + opp-1 { + opp-peak-kBps = <1804000 9216000>; + }; + opp-2 { + opp-peak-kBps = <2188000 11980800>; + }; + opp-3 { + opp-peak-kBps = <3072000 15052800>; + }; + opp-4 { + opp-peak-kBps = <4068000 19353600>; + }; + opp-5 { + opp-peak-kBps = <5412000 20889600>; + }; + opp-6 { + opp-peak-kBps = <6220000 22425600>; + }; + opp-7 { + opp-peak-kBps = <7216000 25497600>; + }; + }; + }; From patchwork Tue May 31 10:51:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 578396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 068A7C4167D for ; Tue, 31 May 2022 10:52:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343600AbiEaKwE (ORCPT ); Tue, 31 May 2022 06:52:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343588AbiEaKwD (ORCPT ); Tue, 31 May 2022 06:52:03 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEE475717D for ; Tue, 31 May 2022 03:52:00 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id gi33so25856370ejc.3 for ; Tue, 31 May 2022 03:52:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FGYMK1Lo3BYXLHQ1Asw4OH+jm1GR+Ww05HcxTffBAr0=; b=g2x2rmFS3eTFVBVJvB5njqFwW7e2Aeh/zFv30j14MXF5HGhmbi0nGZWThVhcsNljzR fy9gJMrQbcPQe3Hzui+APF25Lp5KmPeAin3yg1KvkZ46EfXfcAR6LXS6zpf35y6hfoLr MTmO/dNN52zjqQC50rk0Oa8MM3gJKUqBTrZmMmNbLRr4NlzVoPpHvwc+4RJVI5J+bWcB Pz4oKTu4CRseBEkbsoP4g0W37FrDQyt1dgGY6d1BQV71zHM234w7tpc3dv1Q3mwK/9Jm LnGbcDgzxAwDHw0bVytRDtul1VU+btoZYdiYli1FNC+Idd7o1V1sixc/oXeh12I7Utzj rriQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FGYMK1Lo3BYXLHQ1Asw4OH+jm1GR+Ww05HcxTffBAr0=; b=OlWWU4wCEiCZKeNQHtVlpCtTsKnkvIAGGh3sO6fToYvA7wEobDhKlQWFP9GTYctB16 KKhA8lBFENjJc9J7A8yXSlIJTMQ56vyiHpvGGgLKNeFqm5RjRlAoVCPMxEuOiDSV+x5P HhNg1xKPggQib0Xxn830UDeBIi31s1RJDkRo2r/n8TwyE56sMcdvJ6M5SSO89bou1a1f doQRtCN0cfoRFc1IfxervlXHHeyz25nxoG1QRDtZ8DDTmAOg+hwX74iuLqarvAA8Ef+x ccehEdJ2cSlWxUwe4XTS0/I0fXprjuF2bJYMdU9H7Fh9JUK2pAAOaEhTUNUo6zp7/vk5 bSKw== X-Gm-Message-State: AOAM531awSx2JTnpAabHCq6Ft1tGllAtxs3udOgTcd5j0/82fuRoQKCB RzSPkTq31OAIePJwfpgCJQRwit4Qk72buN/U X-Google-Smtp-Source: ABdhPJzy6StTvg9lnGVP5LVVplRF/nJPguUHEawUEnceXrRHelw3Pc+R1nu9/x0x/a7P2AgEPzMyAw== X-Received: by 2002:a17:907:3da1:b0:6fe:ae46:997d with SMTP id he33-20020a1709073da100b006feae46997dmr45396529ejc.633.1653994319147; Tue, 31 May 2022 03:51:59 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id q3-20020a50aa83000000b0042dc513ced8sm5117441edc.30.2022.05.31.03.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 03:51:58 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thara Gopinath Subject: [PATCH v3 2/4] soc: qcom: icc-bwmon: Add bandwidth monitoring driver Date: Tue, 31 May 2022 12:51:35 +0200 Message-Id: <20220531105137.110050-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220531105137.110050-1-krzysztof.kozlowski@linaro.org> References: <20220531105137.110050-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Bandwidth monitoring (BWMON) sits between various subsytems like CPU, GPU, Last Level caches and memory subsystem. The BWMON can be configured to monitor the data throuhput between memory and other subsytems. The throughput is measured within specified sampling window and is used to vote for corresponding interconnect bandwidth. Current implementation brings support for BWMON v4, used for example on SDM845 to measure bandwidth between CPU (gladiator_noc) and Last Level Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. Co-developed-by: Thara Gopinath Signed-off-by: Thara Gopinath Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 7 + drivers/soc/qcom/Kconfig | 15 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/icc-bwmon.c | 418 +++++++++++++++++++++++++++++++++++ 4 files changed, 441 insertions(+) create mode 100644 drivers/soc/qcom/icc-bwmon.c diff --git a/MAINTAINERS b/MAINTAINERS index 6157e706ed02..bc123f706256 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16376,6 +16376,13 @@ S: Maintained F: Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt F: drivers/i2c/busses/i2c-qcom-cci.c +QUALCOMM INTERCONNECT BWMON DRIVER +M: Krzysztof Kozlowski +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/interconnect/qcom,sdm845-cpu-bwmon.yaml +F: drivers/soc/qcom/icc-bwmon.c + QUALCOMM IOMMU M: Rob Clark L: iommu@lists.linux-foundation.org diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e718b8735444..35c5192dcfc7 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -228,4 +228,19 @@ config QCOM_APR application processor and QDSP6. APR is used by audio driver to configure QDSP6 ASM, ADM and AFE modules. + +config QCOM_ICC_BWMON + tristate "QCOM Interconnect Bandwidth Monitor driver" + depends on ARCH_QCOM || COMPILE_TEST + select PM_OPP + help + Sets up driver monitoring bandwidth on various interconnects and + based on that voting for interconnect bandwidth, adjusting their + speed to current demand. + Current implementation brings support for BWMON v4, used for example + on SDM845 to measure bandwidth between CPU (gladiator_noc) and Last + Level Cache (memnoc). Usage of this BWMON allows to remove fixed + bandwidth votes from cpufreq (CPU nodes) thus achieve high memory + throughput even with lower CPU frequencies. + endmenu diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 70d5de69fd7b..d66604aff2b0 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o +obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c new file mode 100644 index 000000000000..7feb27f49291 --- /dev/null +++ b/drivers/soc/qcom/icc-bwmon.c @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021-2022 Linaro Ltd + * Author: Krzysztof Kozlowski , based on + * previous work of Thara Gopinath and msm-4.9 downstream sources. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The BWMON samples data throughput within 'sample_ms' time. With three + * configurable thresholds (Low, Medium and High) gives four windows (called + * zones) of current bandwidth: + * + * Zone 0: byte count < THRES_LO + * Zone 1: THRES_LO < byte count < THRES_MED + * Zone 2: THRES_MED < byte count < THRES_HIGH + * Zone 3: THRES_HIGH < byte count + * + * Zones 0 and 2 are not used by this driver. + */ + +/* Internal sampling clock frequency */ +#define HW_TIMER_HZ 19200000 + +#define BWMON_GLOBAL_IRQ_STATUS 0x0 +#define BWMON_GLOBAL_IRQ_CLEAR 0x8 +#define BWMON_GLOBAL_IRQ_ENABLE 0xc +#define BWMON_GLOBAL_IRQ_ENABLE_ENABLE BIT(0) + +#define BWMON_IRQ_STATUS 0x100 +#define BWMON_IRQ_STATUS_ZONE_SHIFT 4 +#define BWMON_IRQ_CLEAR 0x108 +#define BWMON_IRQ_ENABLE 0x10c +#define BWMON_IRQ_ENABLE_ZONE1_SHIFT 5 +#define BWMON_IRQ_ENABLE_ZONE2_SHIFT 6 +#define BWMON_IRQ_ENABLE_ZONE3_SHIFT 7 +#define BWMON_IRQ_ENABLE_MASK (BIT(BWMON_IRQ_ENABLE_ZONE1_SHIFT) | \ + BIT(BWMON_IRQ_ENABLE_ZONE3_SHIFT)) + +#define BWMON_ENABLE 0x2a0 +#define BWMON_ENABLE_ENABLE BIT(0) + +#define BWMON_CLEAR 0x2a4 +#define BWMON_CLEAR_CLEAR BIT(0) + +#define BWMON_SAMPLE_WINDOW 0x2a8 +#define BWMON_THRESHOLD_HIGH 0x2ac +#define BWMON_THRESHOLD_MED 0x2b0 +#define BWMON_THRESHOLD_LOW 0x2b4 + +#define BWMON_ZONE_ACTIONS 0x2b8 +/* + * Actions to perform on some zone 'z' when current zone hits the threshold: + * Increment counter of zone 'z' + */ +#define BWMON_ZONE_ACTIONS_INCREMENT(z) (0x2 << ((z) * 2)) +/* Clear counter of zone 'z' */ +#define BWMON_ZONE_ACTIONS_CLEAR(z) (0x1 << ((z) * 2)) + +/* Zone 0 threshold hit: Clear zone count */ +#define BWMON_ZONE_ACTIONS_ZONE0 (BWMON_ZONE_ACTIONS_CLEAR(0)) + +/* Zone 1 threshold hit: Increment zone count & clear lower zones */ +#define BWMON_ZONE_ACTIONS_ZONE1 (BWMON_ZONE_ACTIONS_INCREMENT(1) | \ + BWMON_ZONE_ACTIONS_CLEAR(0)) + +/* Zone 2 threshold hit: Increment zone count & clear lower zones */ +#define BWMON_ZONE_ACTIONS_ZONE2 (BWMON_ZONE_ACTIONS_INCREMENT(2) | \ + BWMON_ZONE_ACTIONS_CLEAR(1) | \ + BWMON_ZONE_ACTIONS_CLEAR(0)) + +/* Zone 3 threshold hit: Increment zone count & clear lower zones */ +#define BWMON_ZONE_ACTIONS_ZONE3 (BWMON_ZONE_ACTIONS_INCREMENT(3) | \ + BWMON_ZONE_ACTIONS_CLEAR(2) | \ + BWMON_ZONE_ACTIONS_CLEAR(1) | \ + BWMON_ZONE_ACTIONS_CLEAR(0)) +/* Value for BWMON_ZONE_ACTIONS */ +#define BWMON_ZONE_ACTIONS_DEFAULT (BWMON_ZONE_ACTIONS_ZONE0 | \ + BWMON_ZONE_ACTIONS_ZONE1 << 8 | \ + BWMON_ZONE_ACTIONS_ZONE2 << 16 | \ + BWMON_ZONE_ACTIONS_ZONE3 << 24) + +/* + * There is no clear documentation/explanation of BWMON_THRESHOLD_COUNT + * register. Based on observations, this is number of times one threshold has to + * be reached, to trigger interrupt in given zone. + * + * 0xff are maximum values meant to ignore the zones 0 and 2. + */ +#define BWMON_THRESHOLD_COUNT 0x2bc +#define BWMON_THRESHOLD_COUNT_ZONE1_SHIFT 8 +#define BWMON_THRESHOLD_COUNT_ZONE2_SHIFT 16 +#define BWMON_THRESHOLD_COUNT_ZONE3_SHIFT 24 +#define BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT 0xff +#define BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT 0xff + +/* BWMONv4 count registers use count unit of 64 kB */ +#define BWMON_COUNT_UNIT_KB 64 +#define BWMON_ZONE_COUNT 0x2d8 +#define BWMON_ZONE_MAX(zone) (0x2e0 + 4 * (zone)) + +struct icc_bwmon_data { + unsigned int sample_ms; + unsigned int default_highbw_kbps; + unsigned int default_medbw_kbps; + unsigned int default_lowbw_kbps; + u8 zone1_thres_count; + u8 zone3_thres_count; +}; + +struct icc_bwmon { + struct device *dev; + void __iomem *base; + int irq; + + unsigned int default_lowbw_kbps; + unsigned int sample_ms; + unsigned int max_bw_kbps; + unsigned int min_bw_kbps; + unsigned int target_kbps; + unsigned int current_kbps; +}; + +static void bwmon_clear(struct icc_bwmon *bwmon) +{ + /* + * Clear counters. The order and barriers are + * important. Quoting downstream Qualcomm msm-4.9 tree: + * + * The counter clear and IRQ clear bits are not in the same 4KB + * region. So, we need to make sure the counter clear is completed + * before we try to clear the IRQ or do any other counter operations. + */ + writel(BWMON_CLEAR_CLEAR, bwmon->base + BWMON_CLEAR); + + /* + * Clear zone and global interrupts. The order and barriers are + * important. Quoting downstream Qualcomm msm-4.9 tree: + * + * Synchronize the local interrupt clear in mon_irq_clear() + * with the global interrupt clear here. Otherwise, the CPU + * may reorder the two writes and clear the global interrupt + * before the local interrupt, causing the global interrupt + * to be retriggered by the local interrupt still being high. + * + * Similarly, because the global registers are in a different + * region than the local registers, we need to ensure any register + * writes to enable the monitor after this call are ordered with the + * clearing here so that local writes don't happen before the + * interrupt is cleared. + */ + writel(BWMON_IRQ_ENABLE_MASK, bwmon->base + BWMON_IRQ_CLEAR); + writel(BIT(0), bwmon->base + BWMON_GLOBAL_IRQ_CLEAR); +} + +static void bwmon_disable(struct icc_bwmon *bwmon) +{ + /* Disable interrupts. Strict ordering, see bwmon_clear(). */ + writel(0x0, bwmon->base + BWMON_GLOBAL_IRQ_ENABLE); + writel(0x0, bwmon->base + BWMON_IRQ_ENABLE); + + /* + * Disable bwmon. Must happen before bwmon_clear() to avoid spurious + * IRQ. + */ + writel(0x0, bwmon->base + BWMON_ENABLE); +} + +static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable) +{ + /* Enable interrupts */ + writel(BWMON_GLOBAL_IRQ_ENABLE_ENABLE, + bwmon->base + BWMON_GLOBAL_IRQ_ENABLE); + writel(irq_enable, bwmon->base + BWMON_IRQ_ENABLE); + + /* Enable bwmon */ + writel(BWMON_ENABLE_ENABLE, bwmon->base + BWMON_ENABLE); +} + +static unsigned int bwmon_kbps_to_count(unsigned int kbps) +{ + return kbps / BWMON_COUNT_UNIT_KB; +} + +static void bwmon_set_threshold(struct icc_bwmon *bwmon, unsigned int reg, + unsigned int kbps) +{ + unsigned int thres; + + thres = mult_frac(bwmon_kbps_to_count(kbps), bwmon->sample_ms, + MSEC_PER_SEC); + writel_relaxed(thres, bwmon->base + reg); +} + +static void bwmon_start(struct icc_bwmon *bwmon, + const struct icc_bwmon_data *data) +{ + unsigned int thres_count, irq_enable; + int window; + + bwmon_clear(bwmon); + + window = mult_frac(bwmon->sample_ms, HW_TIMER_HZ, MSEC_PER_SEC); + /* Maximum sampling window: 0xfffff */ + writel_relaxed(window, bwmon->base + BWMON_SAMPLE_WINDOW); + + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_HIGH, + data->default_highbw_kbps); + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_MED, + data->default_medbw_kbps); + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_LOW, + data->default_lowbw_kbps); + + thres_count = data->zone3_thres_count << BWMON_THRESHOLD_COUNT_ZONE3_SHIFT | + BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT << BWMON_THRESHOLD_COUNT_ZONE2_SHIFT | + data->zone1_thres_count << BWMON_THRESHOLD_COUNT_ZONE1_SHIFT | + BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT; + writel_relaxed(thres_count, bwmon->base + BWMON_THRESHOLD_COUNT); + writel_relaxed(BWMON_ZONE_ACTIONS_DEFAULT, + bwmon->base + BWMON_ZONE_ACTIONS); + + /* Write barriers in bwmon_clear() */ + irq_enable = BIT(BWMON_IRQ_ENABLE_ZONE1_SHIFT) | + BIT(BWMON_IRQ_ENABLE_ZONE3_SHIFT); + bwmon_clear(bwmon); + bwmon_enable(bwmon, BWMON_IRQ_ENABLE_MASK); +} + +static irqreturn_t bwmon_intr(int irq, void *dev_id) +{ + struct icc_bwmon *bwmon = dev_id; + unsigned int status, max; + int zone; + + status = readl(bwmon->base + BWMON_IRQ_STATUS); + status &= BWMON_IRQ_ENABLE_MASK; + if (!status) { + /* + * Only zone 1 and zone 3 interrupts are enabled but zone 2 + * threshold could be hit and trigger interrupt even if not + * enabled. + * Such spurious interrupt might come with valuable max count or + * not, so solution would be to always check all + * BWMON_ZONE_MAX() registers to find the highest value. + * Such case is currently ignored. + */ + return IRQ_NONE; + } + + bwmon_disable(bwmon); + + zone = get_bitmask_order(status >> BWMON_IRQ_STATUS_ZONE_SHIFT) - 1; + /* + * Zone max bytes count register returns count units within sampling + * window. Downstream kernel for BWMONv4 (called BWMON type 2 in + * downstream) always increments the max bytes count by one. + */ + max = readl(bwmon->base + BWMON_ZONE_MAX(zone)) + 1; + max *= BWMON_COUNT_UNIT_KB; + bwmon->target_kbps = mult_frac(max, MSEC_PER_SEC, bwmon->sample_ms); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t bwmon_intr_thread(int irq, void *dev_id) +{ + struct icc_bwmon *bwmon = dev_id; + unsigned int irq_enable = 0; + struct dev_pm_opp *opp, *target_opp; + unsigned int bw_kbps, up_kbps, down_kbps; + + bw_kbps = bwmon->target_kbps; + + target_opp = dev_pm_opp_find_bw_ceil(bwmon->dev, &bw_kbps, 0); + if (IS_ERR(target_opp) && PTR_ERR(target_opp) == -ERANGE) + target_opp = dev_pm_opp_find_bw_floor(bwmon->dev, &bw_kbps, 0); + + bwmon->target_kbps = bw_kbps; + + bw_kbps--; + opp = dev_pm_opp_find_bw_floor(bwmon->dev, &bw_kbps, 0); + if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE) + down_kbps = bwmon->target_kbps; + else + down_kbps = bw_kbps; + + up_kbps = bwmon->target_kbps + 1; + + if (bwmon->target_kbps >= bwmon->max_bw_kbps) + irq_enable = BIT(BWMON_IRQ_ENABLE_ZONE1_SHIFT); + else if (bwmon->target_kbps <= bwmon->min_bw_kbps) + irq_enable = BIT(BWMON_IRQ_ENABLE_ZONE3_SHIFT); + else + irq_enable = BWMON_IRQ_ENABLE_MASK; + + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_HIGH, up_kbps); + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_MED, down_kbps); + bwmon_clear(bwmon); + bwmon_enable(bwmon, irq_enable); + + if (bwmon->target_kbps == bwmon->current_kbps) + goto out; + + dev_pm_opp_set_opp(bwmon->dev, target_opp); + bwmon->current_kbps = bwmon->target_kbps; + +out: + dev_pm_opp_put(target_opp); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + + return IRQ_HANDLED; +} + +static int bwmon_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dev_pm_opp *opp; + struct icc_bwmon *bwmon; + const struct icc_bwmon_data *data; + int ret; + + bwmon = devm_kzalloc(dev, sizeof(*bwmon), GFP_KERNEL); + if (!bwmon) + return -ENOMEM; + + data = of_device_get_match_data(dev); + + bwmon->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(bwmon->base)) { + dev_err(dev, "failed to map bwmon registers\n"); + return PTR_ERR(bwmon->base); + } + + bwmon->irq = platform_get_irq(pdev, 0); + if (bwmon->irq < 0) { + dev_err(dev, "failed to acquire bwmon IRQ\n"); + return bwmon->irq; + } + + ret = devm_pm_opp_of_add_table(dev); + if (ret) + return dev_err_probe(dev, ret, "failed to add OPP table\n"); + + bwmon->max_bw_kbps = UINT_MAX; + opp = dev_pm_opp_find_bw_floor(dev, &bwmon->max_bw_kbps, 0); + if (IS_ERR(opp)) + return dev_err_probe(dev, ret, "failed to find max peak bandwidth\n"); + + bwmon->min_bw_kbps = 0; + opp = dev_pm_opp_find_bw_ceil(dev, &bwmon->min_bw_kbps, 0); + if (IS_ERR(opp)) + return dev_err_probe(dev, ret, "failed to find min peak bandwidth\n"); + + bwmon->sample_ms = data->sample_ms; + bwmon->default_lowbw_kbps = data->default_lowbw_kbps; + bwmon->dev = dev; + + bwmon_disable(bwmon); + ret = devm_request_threaded_irq(dev, bwmon->irq, bwmon_intr, + bwmon_intr_thread, + IRQF_ONESHOT, dev_name(dev), bwmon); + if (ret) + return dev_err_probe(dev, ret, "failed to request IRQ\n"); + + platform_set_drvdata(pdev, bwmon); + bwmon_start(bwmon, data); + + return 0; +} + +static int bwmon_remove(struct platform_device *pdev) +{ + struct icc_bwmon *bwmon = platform_get_drvdata(pdev); + + bwmon_disable(bwmon); + + return 0; +} + +/* BWMON v4 */ +static const struct icc_bwmon_data sdm845_bwmon_data = { + .sample_ms = 4, + .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ + .default_medbw_kbps = 512 * 1024, /* 512 MBps */ + .default_lowbw_kbps = 0, + .zone1_thres_count = 16, + .zone3_thres_count = 1, +}; + +static const struct of_device_id bwmon_of_match[] = { + { .compatible = "qcom,sdm845-cpu-bwmon", .data = &sdm845_bwmon_data }, + {} +}; +MODULE_DEVICE_TABLE(of, bwmon_of_match); + +static struct platform_driver bwmon_driver = { + .probe = bwmon_probe, + .remove = bwmon_remove, + .driver = { + .name = "qcom-bwmon", + .of_match_table = bwmon_of_match, + }, +}; +module_platform_driver(bwmon_driver); + +MODULE_AUTHOR("Krzysztof Kozlowski "); +MODULE_DESCRIPTION("QCOM BWMON driver"); +MODULE_LICENSE("GPL"); From patchwork Tue May 31 10:51:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 577626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB1A5C4332F for ; Tue, 31 May 2022 10:52:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343616AbiEaKwI (ORCPT ); Tue, 31 May 2022 06:52:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343602AbiEaKwF (ORCPT ); Tue, 31 May 2022 06:52:05 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0E37583A9 for ; Tue, 31 May 2022 03:52:01 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id jx22so25715442ejb.12 for ; Tue, 31 May 2022 03:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=l4c6eL6FkT3F5Q2UMeh1SdTOW/jzEthp0aJ+P51R6LI=; b=ezKQ6zWeGyXve1iTyjENVNkwv9DtZyXm+EaCQv5YRyn8Pu7QEY14SzoxTP6UcXVvY8 SNKT2aqUgKz99tKPOFRTuUIIe2yPd8Bgz72lHTaOa6k4f/LHmRSaX1IPS0V4K0/efuAg 1sOclLct0LvM55lEHU2yh6bSapLfeNno4Abq+eL8AO0pQm/XdALoPGVi6njK8xl3HGw6 vALl4o4ChpH9uYGKFSQjpDjjTf0bZcPHobSRWdXk5xR/Yrmyygl59q2sx65dC5PyLyME hN75O3Qe9lrknIc/i7Uz8uQZTZmO65ExCv9cw5F9Y8H3nYxNHLVg+Bv6UQ9PJx5yBXwM LsJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l4c6eL6FkT3F5Q2UMeh1SdTOW/jzEthp0aJ+P51R6LI=; b=7o7U8DxvP1dtIpJyQ14Yl9R8ypeHGFoSyoGZW5HrZcy0rB4RraA0dj7N5GyUhbCDC2 vJPxf/WgtAv6yRanB/sEem3EVTO4CVT1QxaIeHWFqZQVLNaY5bK1yAXsg9xbMMLg9w+X 6gzEqXjC30KOvPWGMYaEsevZ55zNpMR1RQjRA0Fdahl6CpvimuMNzSBNmjnT3t8vNavE 8f7HSJjjuSXrPnslAG4Q6Q9HkYseXEubjMIbIuyW4QTYpNiumgWJfBfL/rpsPOJv+vlb rdGi53six9kwEPElSS2pFVX6vlW0gvkaizl7DxzvaYV+wPQQUiwdfxZRYgm3X2+835e/ ZkdQ== X-Gm-Message-State: AOAM532fR9MTljNijFqWN2JVCG3L0s8Sgua+0PbA1mFHEOgWW8luzLjS OooxDw5wfGWUvzr0WmPOkKlCuQ== X-Google-Smtp-Source: ABdhPJxfZv4U0lBM9OJVvLX7P2n5KCPOoB4LZP9WL8Zcg/eBddHTbAuxRdGAVz7FKnJtIdW+j6aNyg== X-Received: by 2002:a17:907:8a11:b0:6ff:d8c:eff with SMTP id sc17-20020a1709078a1100b006ff0d8c0effmr28865372ejc.659.1653994320263; Tue, 31 May 2022 03:52:00 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id q3-20020a50aa83000000b0042dc513ced8sm5117441edc.30.2022.05.31.03.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 03:51:59 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/4] arm64: defconfig: enable Qualcomm Bandwidth Monitor Date: Tue, 31 May 2022 12:51:36 +0200 Message-Id: <20220531105137.110050-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220531105137.110050-1-krzysztof.kozlowski@linaro.org> References: <20220531105137.110050-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable the Qualcomm Bandwidth Monitor to allow scaling interconnects depending on bandwidth usage between CPU and memory. This is used already on Qualcomm SDM845 SoC. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6906b83f5e45..6edbcfd3f4ca 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1096,6 +1096,7 @@ CONFIG_QCOM_SOCINFO=m CONFIG_QCOM_STATS=m CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_APR=m +CONFIG_QCOM_ICC_BWMON=m CONFIG_ARCH_R8A77995=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77950=y From patchwork Tue May 31 10:51:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 577627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3725C433F5 for ; Tue, 31 May 2022 10:52:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343592AbiEaKwF (ORCPT ); Tue, 31 May 2022 06:52:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343595AbiEaKwD (ORCPT ); Tue, 31 May 2022 06:52:03 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC4E259093 for ; Tue, 31 May 2022 03:52:02 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id t5so16974454edc.2 for ; Tue, 31 May 2022 03:52:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0VLAI4Ml+SYHKdIrxqb9eLy4RuGSKwigpqa2hE5EhyM=; b=Ircbk0hZlXm80bfKncdNpRQnwpqdJf0Or7kiCzAJodozD6rJ0gornPINQpedK+w0Ng 4JQbNZ0/nunG08IvmzRNK9jgtl0aO0wShaJ8z25Z4NDyWjpFYv7iUyCKM7n1/FlUMmd8 kEh/YC4cqLyGtdgpOTamcW+COdIEejfU0XruVAgeEP4zHn8Jdp9REQZS+8shyUkDJWRh 1G73faKLccu2KgPk9VwpuWWtkX5/V0V3KrQ+/xRYpxRVAFbY8ua7L0SwvbpwCh1mH6sV liCys8pboL2t2sJ6zLvyxFYI8ast30W51L20UoXkDX9RL5M4QzaH8Gb4jYIDcSIGvxC0 xMuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0VLAI4Ml+SYHKdIrxqb9eLy4RuGSKwigpqa2hE5EhyM=; b=cOhpyRou7AR2dXP3Dp5To7vkXbdRQX6dKAy7OE0kmEsdwF4kPrX8C8NEotqpXJp6hI DqPcsFn2T6o1SnRxxQB/8ZHw1iryjPAA4r7erXq5PnvnYSJuRl2dUd0qM4DvsLrrsVMV NRizMXaLta7zbOGZt9cwdkVGq4gWljoJqaqPyrOEkctP8Owc+uZe+cpuTCwjb1xvoEu/ PZD+lThMaDj5zgU+585lD/xkPM8F44JBhkOI1dD6B4S4ktOFpZ96ArV/DqVM8cSjNea5 wk+6tAGW0M9Up3llp3r0swSNE1lEPjC+RLQYTxvKLDfB/YRCDPW8n0GbpRmmZPBZkCmO 58/Q== X-Gm-Message-State: AOAM532n+Msq0XsKU5AjpSyMfvmuaf+iZjn6+Cja3MsffK+NJeovXEXd AOyN83cg/nKxixi5OIqEAj57TQ== X-Google-Smtp-Source: ABdhPJxeyRyKKO7bmN1vHfs62vzjhcZu15ey+2f7vqPj4eKKuw8I/4AAaIoQs3LZtcKAYTu97DFvaQ== X-Received: by 2002:a05:6402:17c8:b0:42d:dc6f:f17c with SMTP id s8-20020a05640217c800b0042ddc6ff17cmr5646106edy.17.1653994321314; Tue, 31 May 2022 03:52:01 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id q3-20020a50aa83000000b0042dc513ced8sm5117441edc.30.2022.05.31.03.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 03:52:00 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thara Gopinath Subject: [PATCH v3 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON Date: Tue, 31 May 2022 12:51:37 +0200 Message-Id: <20220531105137.110050-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220531105137.110050-1-krzysztof.kozlowski@linaro.org> References: <20220531105137.110050-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add device node for CPU-memory BWMON device (bandwidth monitoring) on SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. Performance impact (SDM845-MTP RB3 board, linux next-20220422): 1. No noticeable impact when running with schedutil or performance governors. 2. When comparing to customized kernel with synced interconnects and without bandwidth votes from CPU freq, the sysbench memory tests show significant improvement with bwmon for blocksizes past the L3 cache. The results for such superficial comparison: sysbench memory test, results in MB/s (higher is better) bs kB | type | V | V+no bw votes | bwmon | benefit % 1 | W/seq | 14795 | 4816 | 4985 | 3.5% 64 | W/seq | 41987 | 10334 | 10433 | 1.0% 4096 | W/seq | 29768 | 8728 | 32007 | 266.7% 65536 | W/seq | 17711 | 4846 | 18399 | 279.6% 262144 | W/seq | 16112 | 4538 | 17429 | 284.1% 64 | R/seq | 61202 | 67092 | 66804 | -0.4% 4096 | R/seq | 23871 | 5458 | 24307 | 345.4% 65536 | R/seq | 18554 | 4240 | 18685 | 340.7% 262144 | R/seq | 17524 | 4207 | 17774 | 322.4% 64 | W/rnd | 2663 | 1098 | 1119 | 1.9% 65536 | W/rnd | 600 | 316 | 610 | 92.7% 64 | R/rnd | 4915 | 4784 | 4594 | -4.0% 65536 | R/rnd | 664 | 281 | 678 | 140.7% Legend: bs kB: block size in KB (small block size means only L1-3 caches are used type: R - read, W - write, seq - sequential, rnd - random V: vanilla (next-20220422) V + no bw votes: vanilla without bandwidth votes from CPU freq bwmon: bwmon without bandwidth votes from CPU freq benefit %: difference between vanilla without bandwidth votes and bwmon (higher is better) Co-developed-by: Thara Gopinath Signed-off-by: Thara Gopinath Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 54 ++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 83e8b63f0910..adffb9c70566 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2026,6 +2026,60 @@ llcc: system-cache-controller@1100000 { interrupts = ; }; + pmu@1436400 { + compatible = "qcom,sdm845-cpu-bwmon"; + reg = <0 0x01436400 0 0x600>; + + interrupts = ; + + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "ddr", "l3c"; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * The interconnect paths bandwidths taken from + * cpu4_opp_table bandwidth. + * They also match different tables from + * msm-4.9 downstream kernel: + * - the gladiator_noc-mem_noc from bandwidth + * table of qcom,llccbw (property qcom,bw-tbl); + * bus width: 4 bytes; + * - the OSM L3 from bandwidth table of + * qcom,cpu4-l3lat-mon (qcom,core-dev-table); + * bus width: 16 bytes; + */ + opp-0 { + opp-peak-kBps = <800000 4800000>; + }; + opp-1 { + opp-peak-kBps = <1804000 9216000>; + }; + opp-2 { + opp-peak-kBps = <2188000 11980800>; + }; + opp-3 { + opp-peak-kBps = <3072000 15052800>; + }; + opp-4 { + opp-peak-kBps = <4068000 19353600>; + }; + opp-5 { + opp-peak-kBps = <5412000 20889600>; + }; + opp-6 { + opp-peak-kBps = <6220000 22425600>; + }; + opp-7 { + opp-peak-kBps = <7216000 25497600>; + }; + }; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-sdm845"; reg = <0 0x01c00000 0 0x2000>,