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Defines macro ARM_SMCCC_RET_NOT_SUPPORTED as generic return identifier for when a SMCCC feature is not supported. Signed-off-by: Etienne Carriere --- include/linux/arm-smccc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 7f2be23394..94a20c9793 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -51,6 +51,10 @@ #define ARM_SMCCC_QUIRK_NONE 0 #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ +#define ARM_SMCCC_ARCH_FEATURES 0x80000001 + +#define ARM_SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1) + #ifndef __ASSEMBLY__ #include From patchwork Wed Jun 1 08:27:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 577784 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8f0c:0:0:0:0 with SMTP id mq12csp358656mab; Wed, 1 Jun 2022 01:28:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJynnzJmHKkTq8OwX8tuc7G4pQF5nQG9nWseah03fj5jXBSmCW49qZVF1B3ZRk2r/pIkzrJn X-Received: by 2002:a05:6e02:1d06:b0:2d1:a247:650a with SMTP id i6-20020a056e021d0600b002d1a247650amr25719649ila.27.1654072097216; Wed, 01 Jun 2022 01:28:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654072097; cv=none; d=google.com; s=arc-20160816; b=EK3M+JUbaMeh5MiZQpbcx3uN8OFhqUWAVJTljrphevU9ORfgsRg/a1KQ+t2sc+TQLz 7YMPItO0wK9B8lgjeWscMMxOHgmcnQy6qlPhMBkQrQlXdYZmSTIZSu52/DOeWgeSobgI 0hzmAcxp3S0jXOS23UXHX9g/tgzAg11m4cw/cy1aVWlm6G76uKpeNVveuOsb9Ezg9GCq W+wD+ANDQ5SMWTTa4iDlbS4LYSgiykXUG/AbJduxjU8PkhhJB3rVet99kEnb/4HdSbvf 6Pj8S2XxhepBfGci0CsWmLIuSZsBUruU6wFMjas8Y7I5mXj9mnKncjy7BjO5xq9lDvpo 12bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9rooIbOG/oPkGpRcc01s15uGgP1xgEet5UXtdMEMhUQ=; b=L39j9WyUnpT6ObH4kw7Oz62BNsx+SNIvEmnTaRZ2oxCrFzMBlypjWHNc+S3/Rjz33A BvMLqybH2s3OQoL9t3nswh6SI/Smrw3TRVoW5ZBgZIrCdGjoqmA0ePFHc+fhXR3vf61W vV3KAtCmaR6mxh7ov8cPb4TFyjQ+RdPBpcWOJqR/T27wEx7rIomA8Gcr86DUgUolq/JC Q860a+hLmPQArTz9OLnnWZ+qpHDIXLPI2qJUCplcsbHIJ8vlK43gwIGbI8begU052HWQ WRJ6IE8rvGKx/OCfIuYF2UoV3fp6PJ7n2t3QCZfvpxGIi41xXuiB5EadswBfa3yrXby5 njLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dl8PdCm5; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Etienne Carriere --- drivers/firmware/psci.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 657e7eb5ae..f845ba67f8 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -9,18 +9,18 @@ #include #include #include +#include #include #include -#include -#include #include -#include -#include +#include +#include #include +#include #include +#include #include #include -#include #define DRIVER_NAME "psci" From patchwork Wed Jun 1 08:27:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 577783 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8f0c:0:0:0:0 with SMTP id mq12csp358517mab; Wed, 1 Jun 2022 01:28:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx+axpjHmubmYBUf8oWEpTPP5/HqehTYp+Nz1q9B8kbdRccSo4NWb3uDujjn/AaqqaTWodv X-Received: by 2002:a92:d143:0:b0:2d3:8250:343d with SMTP id t3-20020a92d143000000b002d38250343dmr12534678ilg.249.1654072086722; Wed, 01 Jun 2022 01:28:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654072086; cv=none; d=google.com; s=arc-20160816; b=CYGubGZSdcx0aI9bjCixu6m2WJs6iMDSrweproJxKlfD8OkYxNbdllMojY2xsNxtCf zzDjitqcRi99Jn1V6wE6BwWLWr+hnlbK9L+f2uWFoMgK6e/aQtJ419mXLOe943M+TIaj GtTc3wHIEUSQFA45N/J1Esakl+IBVx0fLywi3awKMUb+hnS//P+L4x1MK+G0DojzRdH8 GBPFfmXAgdnb41Or45PM0gi+/9FBUO0HT2Kc61qlNJFSFCK8pvDyMiqJXjNhQLSOHB/b RnqG/PRfn4meTL9jyDH48jo4FPmMtwOt7u8+gJPhnVR3KS+3jMAPmAMsrCtVewW94x7J ctaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dc0PB113VvuojqFAr6i5Jpj8dScoyfXOnqOFH73bCus=; b=OPU/hOXckGhRDDwdy6VTuuY/orYTi+Fhhk7L92kSP8zAKEhnb/4E0Zb4j6BOB/MHqU fbF7vKK35+br6XrhCKFB15eaSgwHEoNuq2a5lOvfAt2Wc2IjVlC3r1QkuoNH6esmmVD5 z78h+C+y/+u6fbQAsZYtIMBQR9gRZQnvp9qipUGGef4eSe2tUOohxvvMmBe4PNzfp/bm ChITHIcvPXZdFtXdwt6EdBzALm/hInm4xcG9LwYFV1V5XZWgnoPRXxqWDzuja6I70Fm0 4QhZwK4yLygs7Ab0nW7Kg/yBIGyjkm6lfuX3fDsrmh1Mt56Nuw5SZ+4fQvcRxXiSiGof 1w+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BQXDCRaQ; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Drivers willing to be bound from Arm SMCCC features discovery can use macro ARM_SMCCC_FEATURE_DRIVER() to register to smccc feature discovery, providing target driver name and a callback function that returns whether or not the SMCCC feature is supported by the system. Signed-off-by: Etienne Carriere --- drivers/firmware/Kconfig | 8 ++++ drivers/firmware/psci.c | 81 ++++++++++++++++++++++++++++++++++++++- include/linux/arm-smccc.h | 16 ++++++++ include/linux/psci.h | 14 +++++++ 4 files changed, 118 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index ef958b3a7a..f10d1aaf4b 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -37,4 +37,12 @@ config ZYNQMP_FIRMWARE Say yes to enable ZynqMP firmware interface driver. If in doubt, say N. +config ARM_SMCCC_FEATURES + bool "Arm SMCCC features discovery" + depends on ARM_PSCI_FW + help + Discover Arm SMCCC features for which a U-Boot driver is defined. When enabled, + the PSCI driver is always probed and binds dirvers registered to the Arm SMCCC + services if any and reported as supported by the SMCCC firmware. + source "drivers/firmware/scmi/Kconfig" diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index f845ba67f8..ef3e983646 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -11,9 +11,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -95,6 +97,76 @@ static bool psci_is_system_reset2_supported(void) return false; } +static void smccc_invoke_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res) +{ + arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res); +} + +static void smccc_invoke_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res) +{ + arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res); +} + +static int bind_smccc_features(struct udevice *dev, int psci_method) +{ + struct psci_plat_data *pdata = dev_get_plat(dev); + struct arm_smccc_feature *feature; + size_t feature_cnt, n; + + if (!IS_ENABLED(CONFIG_ARM_SMCCC_FEATURES)) + return 0; + + /* + * SMCCC features discovery invoke SMCCC standard function ID + * ARM_SMCCC_ARCH_FEATURES but this sequence requires that this + * standard ARM_SMCCC_ARCH_FEATURES function ID itself is supported. + * It is queried here with invoking PSCI_FEATURES known available + * from PSCI 1.0. + */ + if (!device_is_compatible(dev, "arm,psci-1.0") || + PSCI_VERSION_MAJOR(psci_0_2_get_version()) == 0) + return 0; + + if (request_psci_features(ARM_SMCCC_ARCH_FEATURES) == + PSCI_RET_NOT_SUPPORTED) + return 0; + + if (psci_method == PSCI_METHOD_HVC) + pdata->invoke_fn = smccc_invoke_hvc; + else + pdata->invoke_fn = smccc_invoke_smc; + + feature_cnt = ll_entry_count(struct arm_smccc_feature, arm_smccc_feature); + feature = ll_entry_start(struct arm_smccc_feature, arm_smccc_feature); + + for (n = 0; n < feature_cnt; n++, feature++) { + const char *drv_name = feature->driver_name; + struct udevice *dev2; + int ret; + + if (!feature->is_supported || !feature->is_supported(pdata->invoke_fn)) + continue; + + ret = device_bind_driver(dev, drv_name, drv_name, &dev2); + if (ret) { + pr_warn("%s was not bound: %d, ignore\n", drv_name, ret); + continue; + } + + dev_set_parent_plat(dev2, dev_get_plat(dev)); + } + + return 0; +} + static int psci_bind(struct udevice *dev) { /* No SYSTEM_RESET support for PSCI 0.1 */ @@ -109,6 +181,10 @@ static int psci_bind(struct udevice *dev) pr_debug("PSCI System Reset was not bound.\n"); } + /* From PSCI v1.0 onward we can discover services through ARM_SMCCC_FEATURE */ + if (IS_ENABLED(CONFIG_ARM_SMCCC_FEATURES) && device_is_compatible(dev, "arm,psci-1.0")) + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + return 0; } @@ -136,7 +212,7 @@ static int psci_probe(struct udevice *dev) return -EINVAL; } - return 0; + return bind_smccc_features(dev, psci_method); } /** @@ -240,4 +316,7 @@ U_BOOT_DRIVER(psci) = { .of_match = psci_of_match, .bind = psci_bind, .probe = psci_probe, +#ifdef CONFIG_ARM_SMCCC_FEATURES + .plat_auto = sizeof(struct psci_plat_data), +#endif }; diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 94a20c9793..e1d09884a1 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -83,6 +83,22 @@ struct arm_smccc_quirk { } state; }; +/** + * struct arm_smccc_feature - Driver registration data for discoverable feature + * @driver_name: name of the driver relate to the SMCCC feature + * @is_supported: callback to test if SMCCC feature is supported + */ +struct arm_smccc_feature { + const char *driver_name; + bool (*is_supported)(void (*invoke_fn)(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res)); +}; + +#define ARM_SMCCC_FEATURE_DRIVER(__name) \ + ll_entry_declare(struct arm_smccc_feature, __name, arm_smccc_feature) + /** * __arm_smccc_smc() - make SMC calls * @a0-a7: arguments passed in registers 0 to 7 diff --git a/include/linux/psci.h b/include/linux/psci.h index c78c1079a8..03e4186343 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -11,6 +11,8 @@ #ifndef _UAPI_LINUX_PSCI_H #define _UAPI_LINUX_PSCI_H +#include + /* * PSCI v0.1 interface * @@ -115,6 +117,18 @@ #define PSCI_RET_DISABLED -8 #define PSCI_RET_INVALID_ADDRESS -9 +/** + * struct psci_plat_data - PSCI driver platform data + * @method: Selected invocation conduit + */ +struct psci_plat_data { + void (*invoke_fn)(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct arm_smccc_res *res); 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The driver registers as an Arm SMCCC feature driver to allow PSCI driver to bind a device for when secure monitor exposes RNG support from Arm SMCCC TRNG interface. Cc: Sughosh Ganu Cc: Heinrich Schuchardt Signed-off-by: Etienne Carriere --- MAINTAINERS | 5 + drivers/rng/Kconfig | 9 ++ drivers/rng/Makefile | 1 + drivers/rng/smccc_trng.c | 207 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 222 insertions(+) create mode 100644 drivers/rng/smccc_trng.c diff --git a/MAINTAINERS b/MAINTAINERS index 56be0bfad0..5a92b8bfcb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1231,6 +1231,11 @@ F: drivers/gpio/sl28cpld-gpio.c F: drivers/misc/sl28cpld.c F: drivers/watchdog/sl28cpld-wdt.c +SMCCC TRNG +M: Etienne Carriere +S: Maintained +F: drivers/rng/smccc_trng.c + SPI M: Jagan Teki S: Maintained diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index c10f7d345b..6f73be8f9b 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -58,4 +58,13 @@ config RNG_IPROC200 depends on DM_RNG help Enable random number generator for RPI4. + +config RNG_SMCCC_TRNG + bool "Arm SMCCC TRNG interface" + depends on DM_RNG && ARM_PSCI_FW + default y if ARM_SMCCC_FEATURES + help + Enable random number generator for platforms that support Arm + SMCCC TRNG interface. + endif diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile index 435b3b965a..20c40a964c 100644 --- a/drivers/rng/Makefile +++ b/drivers/rng/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_RNG_OPTEE) += optee_rng.o obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o +obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o diff --git a/drivers/rng/smccc_trng.c b/drivers/rng/smccc_trng.c new file mode 100644 index 0000000000..3a4bb33941 --- /dev/null +++ b/drivers/rng/smccc_trng.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Linaro Limited + */ + +#define LOG_CATEGORY UCLASS_RNG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "smccc-trng" + +/** + * Arm SMCCC TRNG firmware interface specification: + * https://developer.arm.com/documentation/den0098/latest/ + */ +#define ARM_SMCCC_TRNG_VERSION 0x84000050 +#define ARM_SMCCC_TRNG_FEATURES 0x84000051 +#define ARM_SMCCC_TRNG_GET_UUID 0x84000052 +#define ARM_SMCCC_TRNG_RND_32 0x84000053 +#define ARM_SMCCC_TRNG_RND_64 0xC4000053 + +#define ARM_SMCCC_RET_TRNG_SUCCESS ((ulong)0) +#define ARM_SMCCC_RET_TRNG_NOT_SUPPORTED ((ulong)-1) +#define ARM_SMCCC_RET_TRNG_INVALID_PARAMETER ((ulong)-2) +#define ARM_SMCCC_RET_TRNG_NO_ENTROPY ((ulong)-3) + +#define TRNG_MAJOR_MASK GENMASK(30, 16) +#define TRNG_MAJOR_SHIFT 16 +#define TRNG_MINOR_MASK GENMASK(15, 0) +#define TRNG_MINOR_SHIFT 0 + +#define TRNG_MAX_RND_64 (192 / 8) +#define TRNG_MAX_RND_32 (96 / 8) + +/** + * struct smccc_trng_priv - Private data for SMCCC TRNG support + * + * @smc64 - True if TRNG_RND_64 is supported, false if TRNG_RND_32 is supported + */ +struct smccc_trng_priv { + bool smc64; +}; + +/* + * Copy random bytes from ulong SMCCC output register to target buffer + * Defines 2 function flavors for whether ARM_SMCCC_TRNG_RND_32 or + * ARM_SMCCC_TRNG_RND_64 was used to invoke the service. + */ +static size_t smc32_copy_sample(u8 **ptr, size_t size, ulong *rnd) +{ + size_t len = min(size, sizeof(u32)); + u32 sample = *rnd; + + memcpy(*ptr, &sample, len); + *ptr += len; + + return size - len; +} + +static size_t smc64_copy_sample(u8 **ptr, size_t size, ulong *rnd) +{ + size_t len = min(size, sizeof(u64)); + u64 sample = *rnd; + + memcpy(*ptr, &sample, len); + *ptr += len; + + return size - len; +} + +static int smccc_trng_read(struct udevice *dev, void *data, size_t len) +{ + struct psci_plat_data *smccc = dev_get_parent_plat(dev); + struct smccc_trng_priv *priv = dev_get_priv(dev); + struct arm_smccc_res res; + u32 func_id; + u8 *ptr = data; + size_t rem = len; + size_t max_sz; + size_t (*copy_sample)(u8 **ptr, size_t size, ulong *rnd); + + if (priv->smc64) { + copy_sample = smc64_copy_sample; + func_id = ARM_SMCCC_TRNG_RND_64; + max_sz = TRNG_MAX_RND_64; + } else { + copy_sample = smc32_copy_sample; + func_id = ARM_SMCCC_TRNG_RND_32; + max_sz = TRNG_MAX_RND_32; + } + + while (rem) { + size_t sz = min(rem, max_sz); + + smccc->invoke_fn(func_id, sz * 8, 0, 0, 0, 0, 0, 0, &res); + + switch (res.a0) { + case ARM_SMCCC_RET_TRNG_SUCCESS: + break; + case ARM_SMCCC_RET_TRNG_NO_ENTROPY: + continue; + default: + return -EIO; + } + + rem -= sz; + + sz = copy_sample(&ptr, sz, &res.a3); + if (sz) + sz = copy_sample(&ptr, sz, &res.a2); + if (sz) + sz = copy_sample(&ptr, sz, &res.a1); + } + + return 0; +} + +static const struct dm_rng_ops smccc_trng_ops = { + .read = smccc_trng_read, +}; + +static bool smccc_trng_is_supported(void (*invoke_fn)(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res)) +{ + struct arm_smccc_res res; + + (*invoke_fn)(ARM_SMCCC_ARCH_FEATURES, ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 == ARM_SMCCC_RET_NOT_SUPPORTED) + return false; + + (*invoke_fn)(ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 & BIT(31)) + return false; + + /* Test 64bit interface and fallback to 32bit interface */ + invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_64, + 0, 0, 0, 0, 0, 0, &res); + + if (res.a0 == ARM_SMCCC_RET_TRNG_NOT_SUPPORTED) + invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_32, + 0, 0, 0, 0, 0, 0, &res); + + return res.a0 == ARM_SMCCC_RET_TRNG_SUCCESS; +} + +ARM_SMCCC_FEATURE_DRIVER(smccc_trng) = { + .driver_name = DRIVER_NAME, + .is_supported = smccc_trng_is_supported, +}; + +static int smccc_trng_probe(struct udevice *dev) +{ + struct psci_plat_data *smccc = dev_get_parent_plat(dev); + struct smccc_trng_priv *priv = dev_get_priv(dev); + struct arm_smccc_res res; + + if (!(smccc_trng_is_supported(smccc->invoke_fn))) + return -ENODEV; + + /* At least one of 64bit and 32bit interfaces is available */ + smccc->invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_64, + 0, 0, 0, 0, 0, 0, &res); + priv->smc64 = (res.a0 == ARM_SMCCC_RET_TRNG_SUCCESS); + +#ifdef DEBUG + smccc->invoke_fn(ARM_SMCCC_TRNG_GET_UUID, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != ARM_SMCCC_RET_TRNG_NOT_SUPPORTED) { + unsigned long uuid_a0 = res.a0; + unsigned long uuid_a1 = res.a1; + unsigned long uuid_a2 = res.a2; + unsigned long uuid_a3 = res.a3; + unsigned long major, minor; + + smccc->invoke_fn(ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + major = (res.a0 & TRNG_MAJOR_MASK) >> TRNG_MAJOR_SHIFT; + minor = (res.a0 & TRNG_MINOR_MASK) >> TRNG_MINOR_SHIFT; + + dev_dbg(dev, "Version %lu.%lu, UUID %08lx-%04lx-%04lx-%04lx-%04lx%08lx\n", + major, minor, uuid_a0, uuid_a1 >> 16, uuid_a1 & GENMASK(16, 0), + uuid_a2 >> 16, uuid_a2 & GENMASK(16, 0), uuid_a3); + } else { + dev_warn(dev, "Can't get TRNG UUID\n"); + } +#endif + + return 0; +} + +U_BOOT_DRIVER(smccc_trng) = { + .name = DRIVER_NAME, + .id = UCLASS_RNG, + .ops = &smccc_trng_ops, + .probe = smccc_trng_probe, + .priv_auto = sizeof(struct smccc_trng_priv), +};