From patchwork Mon Jan 14 13:24:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155462 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3654920jaa; Mon, 14 Jan 2019 05:25:17 -0800 (PST) X-Google-Smtp-Source: ALg8bN7YXGAKHrAVEd1O6Gsz36LDwG3IrhVcxIclfO8fN0N0bo5VbOjbSPmj6mjvi0GPGysHrUkc X-Received: by 2002:a17:902:d68c:: with SMTP id v12mr25148109ply.4.1547472317596; Mon, 14 Jan 2019 05:25:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472317; cv=none; d=google.com; s=arc-20160816; b=d7Dbiff0SxBYeeLemSx9/lj17Fzl++i/i/XQRfVsOVHYSHUgk4a++T/rfeLzowgilm NvLqvwlOe1zvz593PCtHY+HytDNwdHsv2rwG30LfI63ATedPCOeBMlk/J2375smco60C tg1kBY37D4hz5GPOScsyiBirTL35hkWYliR0ZMgoZKYoeEfmn8SunScSj6yB7Pfq86pH OILYI4ATrOUOvaLulnvExDivNlCfdKtV13RH45n/uQQAcHNRSLiNW1WOX4XvlElhZyz2 pukssqf3XnO8BuycZsxM81rusuzbhXGu8liYyojgGjn6QxHC1I2egGuL5Rp6o8ICH/Pq 2mXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=/1J959qeP7cM4MKMLmkewqVjCysFTBea7AaLB6rN+lY=; b=xrXDcUJLUNbt/CSwzlKreLHVkA+9rER6DgOt0C6wRWEAQyBgltO57RbF/NN/b3fYee oawEnNvCTtDvsmbAmRUrFizcTBgfM4SYCekAdbdrS6i1bwy5trYbVnHK5dZpWcZ2nsXF Nkl6fB5K2Ukt7EZ4/FipdQpJGJWPVQVhyMUdazyRCoRzJy6nwj7vvJoNYeGBbOuClf7o 7jEJBCiGV6DNCvNG50J0Q41dHesuVoXSFPoS2jCZL/lxZBwLbp6ceaGjCRmMRXtmPu3y cahp5sBRqdU+fSNGAlL6dYLOMNcYGkFLyhfv454piV90tsiP30T/5RjKgXz1sdrz8ix3 z+Fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XguTTcbM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w27si349527pge.182.2019.01.14.05.25.17; Mon, 14 Jan 2019 05:25:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XguTTcbM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726666AbfANNZQ (ORCPT + 31 others); Mon, 14 Jan 2019 08:25:16 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:40766 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726614AbfANNZO (ORCPT ); Mon, 14 Jan 2019 08:25:14 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDP1r4041058; Mon, 14 Jan 2019 07:25:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472301; bh=/1J959qeP7cM4MKMLmkewqVjCysFTBea7AaLB6rN+lY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XguTTcbMlPaXHdo+Sr5XTVFMC5/hje6r8r5Xv9a5pOyUssOCHqFJA4XbVWPYtNC5t rcASvHisswUhUWIjU2pcf8+55STLnMyZwaNYpXRDaKrvCRJ2ZgRXjnfgZ9oYwC/9y2 fef1j4oZ1sjnBuQEc4oWYdgwZpKhf1ProVMwNyno= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDP18W055900 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:01 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:00 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:00 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWN028516; Mon, 14 Jan 2019 07:24:56 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 01/24] PCI: keystone: Add start_link/stop_link dw_pcie_ops Date: Mon, 14 Jan 2019 18:54:01 +0530 Message-ID: <20190114132424.6445-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add start_link/stop_link dw_pcie_ops and invoke ks_pcie_start_link directly from host_init. start_link/stop_link ops is required for adding EP mode support. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 44 +++++++++++------------ 1 file changed, 22 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 420d30ce11f4..24c38ae570b5 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -419,18 +419,33 @@ static int ks_pcie_link_up(struct dw_pcie *pci) return (val == PORT_LOGIC_LTSSM_STATE_L0); } -static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) +static void ks_pcie_stop_link(struct dw_pcie *pci) { + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); u32 val; /* Disable Link training */ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val &= ~LTSSM_EN_VAL; ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +} + +static int ks_pcie_start_link(struct dw_pcie *pci) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct device *dev = pci->dev; + u32 val; + + if (dw_pcie_link_up(pci)) { + dev_dbg(dev, "link is already up\n"); + return 0; + } /* Initiate Link Training */ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); + + return 0; } /** @@ -515,26 +530,6 @@ static void ks_pcie_quirk(struct pci_dev *dev) } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); -static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - - if (dw_pcie_link_up(pci)) { - dev_info(dev, "Link already up\n"); - return 0; - } - - ks_pcie_initiate_link_train(ks_pcie); - - /* check if the link is up or not */ - if (!dw_pcie_wait_for_link(pci)) - return 0; - - dev_err(dev, "phy link never came up\n"); - return -ETIMEDOUT; -} - static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { unsigned int irq = desc->irq_data.hwirq; @@ -796,7 +791,7 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); - ks_pcie_establish_link(ks_pcie); + ks_pcie_stop_link(pci); ks_pcie_setup_rc_app_regs(ks_pcie); ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), @@ -813,6 +808,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); + ks_pcie_start_link(pci); + dw_pcie_wait_for_link(pci); + return 0; } @@ -875,6 +873,8 @@ static const struct of_device_id ks_pcie_of_match[] = { }; static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { + .start_link = ks_pcie_start_link, + .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, }; From patchwork Mon Jan 14 13:24:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155464 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3655186jaa; Mon, 14 Jan 2019 05:25:32 -0800 (PST) X-Google-Smtp-Source: ALg8bN7KohmVJC019wQafHHSfn2fGbuc/ryaom9ZMWDB2HW9/MxCxyqUlCHuR6aKi/HSHmXvJurn X-Received: by 2002:a62:5003:: with SMTP id e3mr26153999pfb.23.1547472332571; Mon, 14 Jan 2019 05:25:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472332; cv=none; d=google.com; s=arc-20160816; b=BQl7T0KqLLsZVQMnL3ERDbPkTnKqkuGN0a4ostHIGgXaahPgS1fO42AZ8oKTGHTihr R/8602HyvCsYzH+KwBO8vL4c64BQrvrKfPNvd/MNFtDX+XgmvPtV4mIfk2AUYkQqyZEa 5QZYtrPCRLDtjxOlfow0IuLogstA0RtGJPR4u0OTpo1B4V1E6ZvOnphM67Icpkc5UaRg 5HCbMkVAlyJvTb13YYFkll0+v8Xfs/mt+WXIWczGh5JmU+1v6IW4LXpziXH8q3JftEl+ PqIUMmTOqPQ3uRl0DGMCtKEATGXjgdGldzkQQf5oZKH3j1f8W6qmq7HJbgPMHuxWMgjY IarQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TXLdx2SAosMFqyOjlSQie8ZcUaPTkakA6by1/PgLXHo=; b=htiaTDG98h+rJHMY0/gEdh35tHxDmP3C6azaqAaNu8aXGGoA9W6S5uPhh/TOiV08/M zRAb2KOCJ8+fiRPkypu3YvHqMPs1+y9R543nDbCgggJFVVRfLIm2EjRKdDqkSwWuGXpn oUeAIo2h94gALV+p15PwsNQWElKKgs3f+CFLi4F/b5Am0njKZJN8eexNwM/1dSEDlZEF M3te+DJaN1qmHHH+Fl943rijgF/nUi7CwhAvp6hBRIN5RgwlYMGeZ0ANG0bnPzwKqJHq EgRKSlVzlPvJ+9hGNFCb/DfoLUt+8ckjkH9yAobwQfibeTUfkQa7tOKg2X0VKvoiUNy5 plSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nYzVyI5K; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q9si377168pgi.89.2019.01.14.05.25.32; Mon, 14 Jan 2019 05:25:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nYzVyI5K; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726715AbfANNZa (ORCPT + 31 others); Mon, 14 Jan 2019 08:25:30 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:40930 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726525AbfANNZ1 (ORCPT ); Mon, 14 Jan 2019 08:25:27 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPAxx019305; Mon, 14 Jan 2019 07:25:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472310; bh=TXLdx2SAosMFqyOjlSQie8ZcUaPTkakA6by1/PgLXHo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nYzVyI5KUJ+mMVZEpLIUqw5HX93v3kPPKjIRord7C45K+29Cc7nLbKzK0WvK716Hb 4OvbRZCAzQe3eOtpwps2Vgj5Uv4zo5DQuPP8Dce298Yltlu7oo6yIu39fw0saQQme/ odVtamfyu8iqSd4HWCE5Qf2DKoVUK+lOZy2tomUs= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPAOb011734 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:10 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:10 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:10 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWP028516; Mon, 14 Jan 2019 07:25:06 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 03/24] dt-bindings: PCI: keystone: Add "reg-names" binding information Date: Mon, 14 Jan 2019 18:54:03 +0530 Message-ID: <20190114132424.6445-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "reg-names" binding information in order for device tree node to be populated with the correct register strings. This will break old dt compatibility. However Keystone PCI has never worked in upstream kernel due to lack of SERDES support. Before SERDES support is added, cleanup the Keystone PCI dt-bindngs. This new binding will also be used by PCI in AM654 platform. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 2030ee0dc4f9..3a551687cfa2 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -12,8 +12,10 @@ described here as well as properties that are not applicable. Required Properties:- compatibility: "ti,keystone-pcie" -reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI device ID register. +reg: Three register ranges as listed in the reg-names property +reg-names: "dbics" for the DesignWare PCIe registers, "app" for the + TI specific application registers, "config" for the + configuration space address pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 From patchwork Mon Jan 14 13:24:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155465 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3655333jaa; Mon, 14 Jan 2019 05:25:39 -0800 (PST) X-Google-Smtp-Source: ALg8bN6dnpA/pkkWtqfhdF1w6nR2n/KYQPrt/1ir4adQUw0ZtyLAyaR2aiZ0mS9ds28r3h3gLrq8 X-Received: by 2002:a63:2054:: with SMTP id r20mr22581298pgm.328.1547472339307; Mon, 14 Jan 2019 05:25:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472339; cv=none; d=google.com; s=arc-20160816; b=sVJLKfaAjoL0e7OZDRh19Rw3FlGCTfHNNOu1BqJ96fpy9dhRtJ5K9ruCgW8kUH0Bzl ZqesKIB2pgBk5S3aMt7JTlPRgF8Wlgbfd6+lbZ7mVbPRMqE9V9u6x0RcjB8osRYBXPev oOPTTtCcsACWGX2UwbIb8v5IVT+EN/iU2gy3gQBUyjrNql66B7gR8nYXaTR4RRR+ACfq 81VI+zgsQOy1Se/yM5OL55/TJ8FqqUSetM9oOXeDrvUq6OjoSuQKS4ys2h382cbmWhdp umwWQEM5kU6XLSRTGcOwisv3WFHwavMdszY/NSxQbnmr+gH3ujWa44WcrNz+cyOLRbBv JnhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ZOxErDAenCR4nywVOJbopTCQfMydSgJQFf0ad6hjYzM=; b=oItYqHv4yfHaX2UkaSDW8Twm+VoTdwP5uAzG3m3dcrFREix2WCtOZmOfHs2SXcxDIV mTi21QqNOAzHs33Uvq9rJ5FM19T0SrsgrqVvu0CELwD3KOU8r8IpdjV1/D+sRxUqrwG3 8fwKdJ6bx+gBX7ciDVUOGnGRTdygmD1uNXbDxomjebBlCoDAY32r3OUIVSj600jHfwuM 8Pf280biaYZtgagH1600CJMmZJtQp/VN/dLmtLcum6chcJMe4lxyABMIGHSLyj+WJu2j AbllgoesL20ZDMOY6kXEaiuAZ2Hs1BW5tpvoRGOAY9NhCroo5uKbUrcOCepHlC6Bw/4b yKNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mF9gl4t4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t23si344646pgi.181.2019.01.14.05.25.38; Mon, 14 Jan 2019 05:25:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mF9gl4t4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726736AbfANNZi (ORCPT + 31 others); Mon, 14 Jan 2019 08:25:38 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37158 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726563AbfANNZg (ORCPT ); Mon, 14 Jan 2019 08:25:36 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPFgY098049; Mon, 14 Jan 2019 07:25:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472315; bh=ZOxErDAenCR4nywVOJbopTCQfMydSgJQFf0ad6hjYzM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mF9gl4t4rXakuReor+2NmekbjsQHsDqFnPgnchwmK4VZN6lkWMgbMt2i9Hrbs9sVA 5OjgHTqe7DqYPpyhsRIKH7tVjh0J2pQSEKQzrbFFNzrIbF6HrP7Ynw+qoh7LXh1csZ vwFIz4CZLWkI424EW72IKOGyj+wr0H50ETrC7zlE= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPFhj011765 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:15 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:15 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:15 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWQ028516; Mon, 14 Jan 2019 07:25:11 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 04/24] PCI: keystone: Perform host initialization in a single function Date: Mon, 14 Jan 2019 18:54:04 +0530 Message-ID: <20190114132424.6445-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Instead of having two functions ks_pcie_add_pcie_port and ks_pcie_dw_host_init for initializing host, have a single function to perform all the host initialization. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 63 +++++++++-------------- 1 file changed, 23 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index f63268aee2de..3f917ffa9105 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -446,45 +446,6 @@ static int ks_pcie_start_link(struct dw_pcie *pci) return 0; } -/** - * ks_pcie_dw_host_init() - initialize host for v3_65 dw hardware - * - * Ioremap the register resources, initialize legacy irq domain - * and call dw_pcie_v3_65_host_init() API to initialize the Keystone - * PCI host controller. - */ -static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *res; - - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; - pp->va_cfg1_base = pp->va_cfg0_base; - - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - - return dw_pcie_host_init(pp); -} - static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; @@ -826,10 +787,32 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; + struct resource *res; int ret; + /* Index 0 is the config reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + /* + * We set these same and is used in pcie rd/wr_other_conf + * functions + */ + pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + pp->va_cfg1_base = pp->va_cfg0_base; + + /* Index 1 is the application reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + pp->ops = &ks_pcie_host_ops; - ret = ks_pcie_dw_host_init(ks_pcie); + ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; From patchwork Mon Jan 14 13:24:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155468 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3656400jaa; Mon, 14 Jan 2019 05:26:34 -0800 (PST) X-Google-Smtp-Source: ALg8bN7QlSknIqNUtSOq7yq2QM4Cd21KDxF1pL0VWL5kZH0jBsSxKshaSwFEqRatwnF9JEPhsEd2 X-Received: by 2002:a17:902:a5ca:: with SMTP id t10mr25295310plq.139.1547472393960; Mon, 14 Jan 2019 05:26:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472393; cv=none; d=google.com; s=arc-20160816; b=zMquwXktR45JI33wxS+Ii/QzB8u9q7n6ZCXLeLMQXKR1Q3XI7iRWJFLmmciw0gw+QE ehwredMTmI9O6aV8Xt4J/yqmqY0hCiurfIgFRrO6Ln02xdKOpATQCI6NfA7YirFE4Yq6 6b+iV6u6uTOZioMI8eYfncLUiJlvlAbVfXC3gzWCZCvwtcQwhVqNP/ObZXgXGCzxhriP 2wUunv6ckY/u+30bOWcUstlRmOJitawaYphz2hfkepRIKBoQoiGwSOq44+6SF3gDAE1W eFi08Z14cw8FWflkYUoL8ZyPxGfAVdn/58oqIOuYQIlBqinvCWuDhWdlKCX7ZKdiJR+O EZfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=i/fk/tt+1LjhsntKlkuFU4S9fmttwzxDH8syQnMt+Q0=; b=hMkEvZxRjzdFzWlpmmjD+HI2BFV4A9qTUn6TIgrSHjeDot6Mdo3dOsTcSYIo1OBzRi xeVSRpSbdRcnc2PAMY+eVO7AZ1toyry55vt0AUDwXMU0nil/MR8r7wuyryPpIx4/tyZD ZPpHHzB8lEJDwkDyDJZKh34KReRVK0WQhsn1NrMVUpdPDabEA5LyXasTHZIiduCznoh9 dHTif43uDmI82zEiLBYFEUdbL3PT0kls2rEb8X1WZKr4UIxSVNvodKDmkDTKbzbfZ4Fn uWk5aECn+HJ3XwvRm2DKu7vj7VfFLfRoYIb/rnRGBUGxxqnv8/AxUvFVfchaKg0NB7hb 0HIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kwDa8FXb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l8si318503pgm.250.2019.01.14.05.26.33; Mon, 14 Jan 2019 05:26:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kwDa8FXb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726807AbfANN00 (ORCPT + 31 others); Mon, 14 Jan 2019 08:26:26 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37378 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726470AbfANN0Y (ORCPT ); Mon, 14 Jan 2019 08:26:24 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPPKD098075; Mon, 14 Jan 2019 07:25:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472325; bh=i/fk/tt+1LjhsntKlkuFU4S9fmttwzxDH8syQnMt+Q0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kwDa8FXbuhQUUiErE1lls7qIheWSUrEoPhE9vxxyxA3sgQR0ynmXnP5v9DGPcwU/5 o02li3c/WCT/mEBuoEX9WG6NPUEtWv7DVQx+FO/EUlb6cHlNt7cruzIwguaBhGF+Xa m5lRS8vuu8z2+hbypSt0LPymTbtu6m7XYMvdD8lU= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPPSJ093881 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:25 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:25 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:25 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWS028516; Mon, 14 Jan 2019 07:25:20 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 06/24] PCI: keystone: Move initializations to appropriate places Date: Mon, 14 Jan 2019 18:54:06 +0530 Message-ID: <20190114132424.6445-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Move host specific platform_get_resource to ks_add_pcie_port and the common platform_get_resource (applicable to both host and endpoint) to probe. This is in preparation for adding endpoint support to pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 27 +++++++++++++---------- 1 file changed, 15 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 88766d4cb50c..ce2f5c25f7a3 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -789,11 +789,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) @@ -801,13 +796,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { @@ -878,6 +866,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + struct resource *res; + void __iomem *base; u32 num_viewport; struct phy **phy; u32 num_lanes; @@ -894,6 +884,19 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); + base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; From patchwork Mon Jan 14 13:24:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155467 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3655985jaa; Mon, 14 Jan 2019 05:26:12 -0800 (PST) X-Google-Smtp-Source: ALg8bN400kntqqdrYt9ll3UpoY6Ai8KPmuzQRjOGaFSywHL9JCFQiKOHImHAr9DvtY/GdBbctuVM X-Received: by 2002:a63:c10f:: with SMTP id w15mr22598661pgf.199.1547472372694; Mon, 14 Jan 2019 05:26:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472372; cv=none; d=google.com; s=arc-20160816; b=lozDLrHHy1bRD+Du5hRGe2wbygJ8sF8g2n0uT53PhH6mIOpclZgfRuBVURtA4OwzcG CS8O/EyTYMZxRv2lq8Rok5Wbg4jpkP3ONUfHIWQMPt9W4HbqlM10QmA/OA+FNxRBiM/X QJvZ+9ZNqaM8ayLo4XJJzxrjBsyEbfSrevQV4++geb7d2iMiZbj+S+D6WcSr+wm/6Wri LeV1TKWk+diNJ5oy2F6Vr125qkYuVBoMSokxPVy1P7xKcmLYMA7P8I+yGFnih6f6JOCH xBx5UAwGzoD75MZwweJLouzfvFLqmdtkThBvA7w5yz639JJnEG/0pb79qlDRD088CxGp cJGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Oy9h1kP8jbCXe+8kD93AkYommSwhxCLq/ir/s6HONHk=; b=QdG9aYlPQr+xitlKyQacFI5yE7ahsE1rdcyQcuGcqrcrAM4J1N2kZkjlnpqCxlAg3m IDafjg+gkn8ndTB/+HhfouWyvIiyEtWdSU2P5aCjPj0c/7BktqD1y/qYB86H2ZBNGIY5 F2nHhKbYY8KBI9v2K9U8eQZoICYAdGV4e8xUPONqYozdZc/O11c6XvFAl16SZJlG1QwD Tz1BxQhugnKXuRb44Kyr161S0Dp//WF1UbuTbiWi8Bb3TarPr7nH31cvMr+HkAeBKRQ0 YVIQBHrAMPJnif9DYRYjDSFRECJVxtU31nTa+GidedtQZgeC1WCfkeN0htJJPDMgy6Yj 4FzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=I7BLWIMk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f15si327956plr.144.2019.01.14.05.26.12; Mon, 14 Jan 2019 05:26:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=I7BLWIMk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726534AbfANN0L (ORCPT + 31 others); Mon, 14 Jan 2019 08:26:11 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37306 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726554AbfANN0I (ORCPT ); Mon, 14 Jan 2019 08:26:08 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPUeB098095; Mon, 14 Jan 2019 07:25:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472330; bh=Oy9h1kP8jbCXe+8kD93AkYommSwhxCLq/ir/s6HONHk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I7BLWIMkCXUivjd681dUFmq9w/8i0HBJxqyMjwzlhD6gZVkxjv9NSCKZ9cHLWJozz gNL7mZSacsXulhaqrB71ZNrD/e0a+/JcIa7294hkMz8BuxMpfBgGj6tUymevrAhYGw gVMADyVZk9/IIPqteaKo5Zce70edB/Sv7omySTY4= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPU5q056610 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:30 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:29 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:30 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWT028516; Mon, 14 Jan 2019 07:25:25 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 07/24] dt-bindings: PCI: Add dt-binding to configure PCIe mode Date: Mon, 14 Jan 2019 18:54:07 +0530 Message-ID: <20190114132424.6445-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon register that should be used to configure PCIe in RC mode or EP mode. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 3a551687cfa2..8ee07197a063 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -23,6 +23,8 @@ pcie_msi_intc : Interrupt controller device node for MSI IRQ chip ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. +ti,syscon-pcie-mode : phandle to the device control module required to configure + PCI in either RC mode or EP mode. Example: pcie_msi_intc: msi-interrupt-controller { From patchwork Mon Jan 14 13:24:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155482 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657604jaa; Mon, 14 Jan 2019 05:27:38 -0800 (PST) X-Google-Smtp-Source: ALg8bN44lci/MJuqlEX6kC/Eer9adLwtZxTy35QjzLaU5An7ZZKX2RsdwcgiutPlRDCuHssopXMo X-Received: by 2002:a63:4926:: with SMTP id w38mr21893468pga.353.1547472458575; Mon, 14 Jan 2019 05:27:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472458; cv=none; d=google.com; s=arc-20160816; b=QF+6gDuAB56qXEA/uyzZigUbrav1NjrZfBJb3aTZnzRWZK/BIqEMzEOE+VXIYn2sxX cbCcv4O0PxpkCsEDSRNldgBKIvkOhpRh8GwAbXIjbe4iIZ+kXRFf1qAhfnA0Q6yK2a0r rE8qBufENDJCni2HTqXVesHAvc+bMhEeI7uwy8B6OG11vsHQNIh0LD5lAH7dQ7vCNiPb j4yOk31gYbye0iJiMEv0CDbbFPJ0QwwVJca0LaD+3GGjHWUdnqd9S5ijBKIOA0oJRyy2 UNRuWVXP6xsg69Q8H9RjFUkP/zaUm1QYpSIlw99uaBlWBDajAeKeUiI4M5QXHBMQr0Qg 7cZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=tWr3enOfHY/N1zh//XsnGspmWYu0ckIGK/nsnUn+GzQ=; b=Vow//QWpNoL5G8aWZjJC0x8Wjci4wY/x/vfp/5dK6ABBD+OC85JxchNA88TN9JR4vo JjpLUlt/6qQUKkTEgwOLM/ESYGaZpUJ6acARlY+3TIa81NLISRXMRWs1AwJDcdPAAclr AV8qwnWCMj6e8axIQTjmMmQ694bcyuVVkqXcwFUPMr569e+FOFCpyxur+AxnxREndJPQ LQp7VNxTtYFS5AWncMJODm3PP8hklBiRZSytjSWBXcupf4Bn8Lcz5YeuKc3K5FSQWxoh XAAhqfgtlbO3JITyMzLn7ixV7+PLxIkF7QV322KtBnUKa6XPGVA/iaDeF+PsU52wm4em ltng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=r+bkx6Le; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t20si331011pgl.211.2019.01.14.05.27.38; Mon, 14 Jan 2019 05:27:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=r+bkx6Le; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727040AbfANN1h (ORCPT + 31 others); Mon, 14 Jan 2019 08:27:37 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37648 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726518AbfANN1e (ORCPT ); Mon, 14 Jan 2019 08:27:34 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPZg6098110; Mon, 14 Jan 2019 07:25:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472335; bh=tWr3enOfHY/N1zh//XsnGspmWYu0ckIGK/nsnUn+GzQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=r+bkx6LeW0pSvKeIOFzOA37U9B2R7sdKsI7CFyRpoUBLLGahmjzR8awEFLeUvIOMe s7gm/PgXpsrFbUePRYAk73vSDWqRTKkuLR3aVdYPtITHd26/G4eVaCsr7x97ZLUzs0 Z/oATG0y6z8y9Ik+n+0TDAEm+6B98W0CLRw2bcAQ= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPZr6088866 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:35 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:34 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:34 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWU028516; Mon, 14 Jan 2019 07:25:30 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 08/24] PCI: keystone: Explicitly set the PCIe mode Date: Mon, 14 Jan 2019 18:54:08 +0530 Message-ID: <20190114132424.6445-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always relying on the default values. This is required when EP mode has to be explicitly written to BOOTCFG_DEVCFG register. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index ce2f5c25f7a3..d1ecf826dfe8 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -79,6 +79,15 @@ #define PCIE_RC_K2L 0xb00a #define PCIE_RC_K2G 0xb00b +#define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) +#define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) + +#define EP 0x0 +#define LEG_EP 0x1 +#define RC 0x2 + +#define KS_PCIE_SYSCLOCKOUTEN BIT(0) + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct keystone_pcie { @@ -859,6 +868,30 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) return ret; } +static int ks_pcie_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; + val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + static int __init ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -971,6 +1004,10 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Mon Jan 14 13:24:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155469 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3656440jaa; Mon, 14 Jan 2019 05:26:36 -0800 (PST) X-Google-Smtp-Source: ALg8bN6GUqqFJKUWqTMxzLUtCq7tAkz7soPJ1QprhTuotDG3hnk8OQYZ4a5Jzsj0B6ocWZLkpJiU X-Received: by 2002:a17:902:7687:: with SMTP id m7mr25208967pll.187.1547472396226; Mon, 14 Jan 2019 05:26:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472396; cv=none; d=google.com; s=arc-20160816; b=Ix7GKEdYvwLzBi1Xwym36AVaYL6xRxPls9G16N1gaJ5V2KD6Lv354MuiM4lwagXqCt RAVgWlxoEfQ9o7LA2f2R7+Tg/dM3OVFghhBxgGz6HaMJLuMHPbtj7DaZbEs7FCNKaD6d qVuK0yb+yMOdteb8gEZNy9EHxQZy7Lv/xoHd4IaDZyWT1MLLnjYRWU0IXPFbTNNbhS8N BEwJY3yHrFjaR+HNuf0ZmgaCL/vsP3r1lRiTGbQHFswuemtDPPH3kxRF8Z+Qwv9O0MCa PsfHoiBbVM72HVYT+A5CmTY+idEpSWzokzg7pZPRyJcIHNjiyumSFkIrzaOpl2mQrYhf IJEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7srJLFU2H5APGDHmyq9l+0rZG+OkuO025oUKh/xV4Ug=; b=FnPcvxUr5b1Bf0lp31GLcLTJGeeN45XcF1IRdJMaDitP70YyBj0JJA0TLUurk7bJvA /EXAitHgZNnLkmubu+T0M13KcW5v0hwRKTM+ijQvgN3hk01gQAOJKaOok5gFIduMYmI5 FuRYgIdMRR2grlxScNZm8Qm61OSI/GaG9ZI1Kmrgo2LcWzbcD4kjGUtLw2II951bpGmt eCim59Oewlc9tnN0WEIzBHyL/b9D1TEs364VcXTkKuWyXac6t2kw9O1Arkrg2rjsLBoJ GmaNp4lKothaPHnxcbG0elHKWHbYNeskPEvG5oEJRSmnxfkqP03RzciJI3+W01/6yY84 ZdhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fQ2FpcpH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o85si355480pfa.162.2019.01.14.05.26.35; Mon, 14 Jan 2019 05:26:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fQ2FpcpH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726836AbfANN0f (ORCPT + 31 others); Mon, 14 Jan 2019 08:26:35 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35074 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726526AbfANN0c (ORCPT ); Mon, 14 Jan 2019 08:26:32 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPeY5106802; Mon, 14 Jan 2019 07:25:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472340; bh=7srJLFU2H5APGDHmyq9l+0rZG+OkuO025oUKh/xV4Ug=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fQ2FpcpHFi9fBft51sGEOe6H5m2YVZz+0j8PiSKYDXcJMdAQeBYBTzGk8mwtul2H+ 2PvNpZW7bcN2E0ttMYe846KuE/7Mfl3L9aJVvVabvIkW4Tx2v6vrCyZlWUh5ImqgGp dlGVQXcCEZDXYY0mptaqcFLubJuAeCsxFzwtK84k= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPdbp094124 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:39 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:40 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:39 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWV028516; Mon, 14 Jan 2019 07:25:35 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 09/24] dt-bindings: PCI: Document "atu" reg-names Date: Mon, 14 Jan 2019 18:54:09 +0530 Message-ID: <20190114132424.6445-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document "atu" reg-names required to get the register space for ATU in Synopsys designware core version >= 4.80. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index c124f9bc11f3..5561a1c060d0 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -4,8 +4,11 @@ Required properties: - compatible: "snps,dw-pcie" for RC mode; "snps,dw-pcie-ep" for EP mode; -- reg: Should contain the configuration address space. -- reg-names: Must be "config" for the PCIe configuration space. +- reg: For designware cores version < 4.80 contains the configuration + address space. For designware core version >= 4.80, contains + the configuration and ATU address space +- reg-names: Must be "config" for the PCIe configuration space and "atu" for + the ATU address space. (The old way of getting the configuration address space from "ranges" is deprecated and should be avoided.) - num-lanes: number of lanes to use From patchwork Mon Jan 14 13:24:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155473 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3656686jaa; Mon, 14 Jan 2019 05:26:50 -0800 (PST) X-Google-Smtp-Source: ALg8bN7erBEByYJf7o+6QpOALPdBCcbMaVc6f3T7oJ+8UgiJgfwHopI3IVCSAq+kMGhiE5sd/uI+ X-Received: by 2002:a63:7512:: with SMTP id q18mr21005530pgc.231.1547472410009; Mon, 14 Jan 2019 05:26:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472410; cv=none; d=google.com; s=arc-20160816; b=YDrRIrAAw4OhY/MitEi/FTUdZwskceykttaFkGms540iAUoNM94DaLUNXrI6DfH5XK 1zhTgySXyMTr/K+FBQGWOKJgL1TcpmSwP3wERMXEUIKXx3ZduCS4NKFEzq7ZKDPNA6db tR4DRvjiDLOgIsf9tam5GdS4anQR95rq4dCKcjPzZvh2LiDDwm1T5S6hzgRkEhax8KlQ vfNyHt9WGhEGez8GuDB+uTKyeGocIz91q/uSjS3cm5xuQkqNuUT/XNSuQBXmk5Ie//N1 1pFmYtzAphoGbEJ9gt6A+b9HUdvaTUtAOAg/eopE1ruF7O8ArzrP/dhlKQTbsPtOuizk b0bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=5utE+jodqQLD4g3Pt/AHbdOGuOmz2jyxoVSY0CpmSSw=; b=sP7CX5j4nDFnCWDWDVRW5N8I6pm1DecbvVwC3fS4eMvedQPfBysHNCbpvpJwjpNc0t Jyp6ewNBGWylf1PJMfeZ0WTByGxUCLTx2EqL46MgJGw8rp7xvA2eLpbKDq2NM5+Ep7z+ GoJXUPIXPqhtawUsMEboLJ3d0cUWX+7G/kNNEIdwG+9vJyb7fhDANnbCSY/KTVxIXVi7 0OcKiO4UsvVZnCv1at9FoB4OPMC6dDusLX2W4YhZN4HGyll7t6JPuNK1XWdVXqfF0OQG 0V+Xx9tdYfiQBO+P1agmA+o8B00WWYzhqFcktgCEYN9hVS1yo7cjxdOkwads1HibuGS/ JqDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UexewYwf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o13si319419pgp.540.2019.01.14.05.26.49; Mon, 14 Jan 2019 05:26:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UexewYwf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726650AbfANN0t (ORCPT + 31 others); Mon, 14 Jan 2019 08:26:49 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35108 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726851AbfANN0n (ORCPT ); Mon, 14 Jan 2019 08:26:43 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPnhR106834; Mon, 14 Jan 2019 07:25:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472349; bh=5utE+jodqQLD4g3Pt/AHbdOGuOmz2jyxoVSY0CpmSSw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UexewYwfuHEcVRAYewKVPjpC+xxXDwqrCAqKCw2vcqt+sYJbM3lXDUeDwjzaBiHj4 xHIARdb88JXKBTTT7SDOg9wTmLF064a9xEsmWqcc19strsqiLYZN2GzkuEVrSz87fi WeLKtMV7pt4he7NC1pcJ+oJAsAa8fQetoWk7xtaY= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPnqL056742 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:49 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:49 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:49 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWX028516; Mon, 14 Jan 2019 07:25:45 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 11/24] PCI: dwc: Fix ATU identification for designware version >= 4.80 Date: Mon, 14 Jan 2019 18:54:11 +0530 Message-ID: <20190114132424.6445-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which hasn't populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++------ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 78539452c265..37506aba22fe 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -358,13 +358,15 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); + if (pci->version >= 0x480A || (!pci->version && + dw_pcie_iatu_unroll_enabled(pci))) { + pci->iatu_unroll_enabled = true; + if (!pci->atu_base) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? + "enabled" : "disabled"); - if (pci->iatu_unroll_enabled && !pci->atu_base) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ea4b215b605d..4ab2e3dbd6bb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -231,6 +231,7 @@ struct dw_pcie { struct pcie_port pp; struct dw_pcie_ep ep; const struct dw_pcie_ops *ops; + unsigned int version; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) From patchwork Mon Jan 14 13:24:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155472 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3656631jaa; Mon, 14 Jan 2019 05:26:47 -0800 (PST) X-Google-Smtp-Source: ALg8bN6CdPZhRmQUKQIQ6UZNoR0/hC4FB0s5rXVUXwiSoptDjn7MP85a/GxB8OjqwJlY2/Us79Lu X-Received: by 2002:a62:5b44:: with SMTP id p65mr25031036pfb.47.1547472407071; Mon, 14 Jan 2019 05:26:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472407; cv=none; d=google.com; s=arc-20160816; b=1K8AMN6hnH0f0JQZjcsWrZQpoxMqKguFkaZzn3FQ+zYxSv+TSG+GAiaKw4zF+0HCGW 2cHiWo+HONnnSZweT647iys8DYjP67Pkga2Ev20ofhIGsyWFmOmYdEN4/I8WyqiLNObP k4axkE1o7vDPi3GLzithfX9Z7mILBFBXWYRNyqVRUvC6VX5uTa7hBh7+ujW2uIKeb5JP roEtFp1mH6TJGqOGfi7sBh3tbD2YngDrAYdrCBLr5VADoxagRaT6v3v0H6Mv6AfjkBd1 hbB79pRVvpVFIod3zvKvc+0HAs6vjq40KJ7EZ7NvvHU9nyUiJRlPZog0hEHUjCoO+Dj/ xd4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=GogJmhPjCHQln5mVKUVQZbQ+wSVFSwsYqqaCZro7fL4=; b=tFzYoB0NsaeUHSKpcEVtOZ9aa0FlXezlxs0CC6aYIIP0JfJTXvGNimGhonaTgYLDOz 9NBvpo+UoiB0OK0aCPVlgL8gOG5yLur/xY051Xr0C/HZznEB7MrKt246adc5jx0trD+/ NlAfFPtuNWs10+FtKpGBCXU6rzUoonK0X6zAFPUiUs5kUjSEHF6CXjjhRY1zMxpNR8nV c30jVPrTevsIgJ3/q+qGKfzyDlmqOtzVOaz89uLDXAobT6oYj9Z4RzZD6DOm4FdKmzhD aYrL1NEEmNzdxqgtg49Pz7Timc3WDQvGN9Rhe6LDzEOawaijWRk9ytMr/VeM2bRm0314 kthw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oQwcW9+v; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Since pci-keystone.c will be used for AM65X platforms which is an ARM64 platform, allow hook_fault_code to be compiled only for ARM32. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d1ecf826dfe8..9d7cedd96505 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -693,6 +693,7 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) return ret; } +#ifdef CONFIG_ARM /* * When a PCI device does not exist during config cycles, keystone host gets a * bus error instead of returning 0xffffffff. This handler always returns 0 @@ -712,6 +713,7 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, return 0; } +#endif static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) { @@ -761,12 +763,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; +#ifdef CONFIG_ARM /* * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" */ hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); +#endif ks_pcie_start_link(pci); dw_pcie_wait_for_link(pci); From patchwork Mon Jan 14 13:24:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155470 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3656566jaa; Mon, 14 Jan 2019 05:26:43 -0800 (PST) X-Google-Smtp-Source: ALg8bN4QIMBdy98ydBAmFx4QKyJVj/l9Et3TqKmkch33T5er2HqsJoSIEU6yOJU4typBTCO9MfLI X-Received: by 2002:a63:5b48:: with SMTP id l8mr22854757pgm.80.1547472403245; Mon, 14 Jan 2019 05:26:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472403; cv=none; d=google.com; s=arc-20160816; b=vVk8wDvGvquOKZodpCV3Vozwuef1U7RLNMPRAK4zEPgvYV3vjsh21zv/q+nVM8O2B4 RcpYuAS0P/grxWuYB7qYAsjHFANCVNsmzTececXHZBOi15rZx/Q9EqHO4Wy7LfoEtgIl ixfaoN4JsfcgYKqMxJ4yTbNlP0ZsSCoCJNePu4fUGPiTJRsdpI7qucnNVZ3L75oFYduL mKP6yPI8mouTPTEFdDPLmQStX9YfYtKPO/t1FHAGUpcCPlexzFPOJ0m9WApHEnliHzHl kcvSd7eyQ5jmPhsDxPetr0Pdbh18SbIrXOvNyKwlGNvjJT8jetC2q1FsMK/kv2WHPJVY vMtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dX0AnoHumpKjN/Hxuc1DnDN/uBYu6jOtQe3dNmu6KNI=; b=TdiAbE5I/mOAToDCJ85c7Da4vPAgSAOFXxuCYUJt2Sb1NOMra/KHZ2RHgbq+isLZAy u9ncAOADQa5nkitxDl7ZB0v4DyqG1r/V7p/RXQFpq3tbt9j1M9qJwqPIj687FkQ4KpXy Lxfb+wl2jrfChnuMpOVd4WNtLP41KnIFm8ynn7TisMtEKolHQ4VNcCQSFzQMeYDx2lfX 5Qt+vLwuyBezl97zFwVoN0yjbQrf4yoPHVn73VyOs91UjVGo9fwr3o0Pe3EDy3c7a2Lr ozPg7frHMdlMjCdO2myIZiQdKXfsyDXyMpSn525Z2Bi5WuhjQk/yRxkhnsKhHF8xM8cW TKmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QeJjxbwR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 8ee07197a063..5c60e911b8b1 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -11,7 +11,8 @@ described here as well as properties that are not applicable. Required Properties:- -compatibility: "ti,keystone-pcie" +compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC + Should be "ti,am654-pcie-rc" for RC on AM654x SoC reg: Three register ranges as listed in the reg-names property reg-names: "dbics" for the DesignWare PCIe registers, "app" for the TI specific application registers, "config" for the @@ -20,6 +21,9 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines + (required if the compatible is "ti,keystone-pcie") +msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt + (required if the compatible is "ti,am654-pcie-rc". ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. 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Mon, 14 Jan 2019 07:26:03 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWa028516; Mon, 14 Jan 2019 07:25:59 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 14/24] PCI: keystone: Add support for PCIe RC in AM654x Platforms Date: Mon, 14 Jan 2019 18:54:14 +0530 Message-ID: <20190114132424.6445-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add PCIe RC support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/Kconfig | 2 +- drivers/pci/controller/dwc/pci-keystone.c | 124 +++++++++++++++++++--- 2 files changed, 113 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 548c58223868..0bb19e268a8a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -104,7 +104,7 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" - depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) + depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST help diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 9d7cedd96505..c2873339809a 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -88,8 +89,15 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) +#define AM654_PCIE_DEV_TYPE_MASK 0x3 + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +struct ks_pcie_of_data { + const struct dw_pcie_host_ops *host_ops; + unsigned int version; +}; + struct keystone_pcie { struct dw_pcie *pci; /* PCI Device ID */ @@ -229,6 +237,16 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp) return dw_pcie_allocate_domains(pp); } +static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + + dev_vdbg(dev, "dummy function so that DW core doesn't configure MSI\n"); + + return 0; +} + static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); @@ -325,6 +343,8 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) u32 val; u32 num_viewport = ks_pcie->num_viewport; struct dw_pcie *pci = ks_pcie->pci; + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; struct pcie_port *pp = &pci->pp; u64 start = pp->mem->start; u64 end = pp->mem->end; @@ -336,6 +356,9 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); ks_pcie_clear_dbi_mode(ks_pcie); + if (of_device_is_compatible(np, "ti,am654-pcie-rc")) + return; + val = ilog2(OB_WIN_SIZE); ks_pcie_app_writel(ks_pcie, OB_SIZE, val); @@ -597,6 +620,8 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); if (!intc_np) { + if (of_device_is_compatible(np, "ti,am654-pcie-rc")) + return 0; dev_WARN(dev, "msi-interrupt-controller node is absent\n"); return -EINVAL; } @@ -732,8 +757,10 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) if (ret) return ret; + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); + dw_pcie_dbi_ro_wr_dis(pci); return 0; } @@ -786,6 +813,11 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { .scan_bus = ks_pcie_v3_65_scan_bus, }; +static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { + .host_init = ks_pcie_host_init, + .msi_host_init = ks_pcie_am654_msi_host_init, +}; + static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { struct keystone_pcie *ks_pcie = priv; @@ -809,7 +841,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); @@ -819,14 +850,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } -static const struct of_device_id ks_pcie_of_match[] = { - { - .type = "pci", - .compatible = "ti,keystone-pcie", - }, - { }, -}; - static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, @@ -896,14 +919,66 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } +static int ks_pcie_am654_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = AM654_PCIE_DEV_TYPE_MASK; + val = RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + +static const struct ks_pcie_of_data ks_pcie_rc_of_data = { + .host_ops = &ks_pcie_host_ops, + .version = 0x365A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { + .host_ops = &ks_pcie_am654_host_ops, + .version = 0x490A, +}; + +static const struct of_device_id ks_pcie_of_match[] = { + { + .type = "pci", + .data = &ks_pcie_rc_of_data, + .compatible = "ti,keystone-pcie", + }, + { + .data = &ks_pcie_am654_rc_of_data, + .compatible = "ti,am654-pcie-rc", + }, + { }, +}; + static int __init ks_pcie_probe(struct platform_device *pdev) { + const struct dw_pcie_host_ops *host_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + const struct ks_pcie_of_data *data; + const struct of_device_id *match; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + void __iomem *atu_base; struct resource *res; + unsigned int version; void __iomem *base; u32 num_viewport; struct phy **phy; @@ -913,6 +988,14 @@ static int __init ks_pcie_probe(struct platform_device *pdev) int irq; int i; + match = of_match_device(of_match_ptr(ks_pcie_of_match), dev); + data = (struct ks_pcie_of_data *)match->data; + if (!data) + return -EINVAL; + + version = data->version; + host_ops = data->host_ops; + ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) return -ENOMEM; @@ -936,6 +1019,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; + pci->version = version; ret = of_property_read_u32(np, "num-viewport", &num_viewport); if (ret < 0) { @@ -1008,10 +1092,26 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - ret = ks_pcie_set_mode(dev); - if (ret < 0) - goto err_get_sync; + if (pci->version >= 0x480A) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + atu_base = devm_ioremap_resource(dev, res); + if (IS_ERR(atu_base)) { + ret = PTR_ERR(atu_base); + goto err_get_sync; + } + + pci->atu_base = atu_base; + + ret = ks_pcie_am654_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } else { + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } + pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Mon Jan 14 13:24:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155476 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3656942jaa; Mon, 14 Jan 2019 05:27:04 -0800 (PST) X-Google-Smtp-Source: ALg8bN6XXqnZ2Mgyg7iKDXEWcd1BY870c9Gvs/jL8GVx6+0GV9HLX7mG7tMcEUFL2qoVcW+kJNFm X-Received: by 2002:a63:f34b:: with SMTP id t11mr22857751pgj.341.1547472423967; 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[209.132.180.67]) by mx.google.com with ESMTP id b3si326645pgh.496.2019.01.14.05.27.03; Mon, 14 Jan 2019 05:27:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fv7lvd0y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726959AbfANN05 (ORCPT + 31 others); Mon, 14 Jan 2019 08:26:57 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37530 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726570AbfANN0z (ORCPT ); Mon, 14 Jan 2019 08:26:55 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQ9U3098224; Mon, 14 Jan 2019 07:26:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472369; bh=4d1hv974DlQuBmZ/Ggs87YZnRdDcz6OLaZ5/NqWUvn4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fv7lvd0yI0YqvB+Bmfx/l6qx2gCvEwKD1lzBoE69GFO9XpgTJIq9AiBzzNLKoSSNT Fati1EOsDVxi8Fvo/fZelkO2lr+A+tk+oMtcA+dbVVdb6VVjynLwcONmY805lEDa/b sEqMNS2SsfoWpF0c4338QThzH9rKao+kHIxVSbSU= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQ9kF012402 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:09 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:08 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:08 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWb028516; Mon, 14 Jan 2019 07:26:04 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 15/24] PCI: keystone: Invoke phy_reset API before enabling PHY Date: Mon, 14 Jan 2019 18:54:15 +0530 Message-ID: <20190114132424.6445-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SERDES connected to the PCIe controller in AM654 requires power on reset enable (POR_EN) to be set in the SERDES. The SERDES driver sets POR_EN in the reset ops and it has to be invoked before init or enable ops. In order for SERDES driver to set POR_EN, invoke phy_reset API in pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index c2873339809a..e2f4e7c01b5a 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -873,6 +873,10 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) int num_lanes = ks_pcie->num_lanes; for (i = 0; i < num_lanes; i++) { + ret = phy_reset(ks_pcie->phy[i]); + if (ret < 0) + goto err_phy; + ret = phy_init(ks_pcie->phy[i]); if (ret < 0) goto err_phy; From patchwork Mon Jan 14 13:24:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155481 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657558jaa; Mon, 14 Jan 2019 05:27:35 -0800 (PST) X-Google-Smtp-Source: ALg8bN5uEzEeuTX7P6ObW/51N1wPvkWqsjsrxouayXFRN17X/zLJVJW0RRZtOoDrSHh4MsxQO3Ko X-Received: by 2002:a63:e84c:: with SMTP id a12mr20468421pgk.241.1547472455866; Mon, 14 Jan 2019 05:27:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472455; cv=none; d=google.com; s=arc-20160816; b=1KeOO2DCX0cxnKsDhXFZDPWnQTBFlxaGd3y4YQGb/S4yaF7iEr4pKlnfW0UbWtwgIN sWPxiXrYmo85xCiVplzWD9kty1Bafq8qOb3yAvp5oz4feJZ/+bSOrQQyOdW6y3Ld/LFm LZjadQj5zxjMEHg/gaZ643+ObU4DvQiQTOEY6oJXZvpRDLJpnWsRHf2Td2KEPvrEmBXg KSnQBJhaF2SDGT+dN1mS+nLHOZIEMNXLQmOdaJdsF/sODizvoIWMwX8bcT5UA2N2QHRZ iZjkxjK/kqu8TTZ42ckCqTdMA0zT3vGz+JGXyMBxFYddT+kNh3kho6OOe1BARG2ku8sG 8rMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=1cBzf8O7pgKPJLJpe2QIGf7wnuv4q+HWdzVaE+h4hbQ=; b=kMhsNcahr4d/rNGnBcUVvG6PyFuchQS7sKPgeCPEnxNMDHCEJ7vPP9q1Ct4NsAq/3o hgiUmJyJopEnpyEzP6aWK6v1R90Ly+Nc76Lz2fOQEifQLGiBX5TczMXd8kqJynEqbKGh lxP0IIJaUIz+0DON5/vUzWPobTQyfYRvHetGHzMRxw9kWKkwgEvdAlhHXhaoyGtZXxUI uzzF7Nuv+HQuLzICyjMm6MWHhjy8yOBaWOOFRuinTGrqr06o9YtP2xVGkMe66feQhbSm BtH65Zq9g8A0mE8Qnbx3aZd8AQlcn0L80s0NlJHWnqa59ds4IJXHXPlKX4ov9Bf519HT 819w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bgyT0zhx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 15620cfa617b..b4fbb4be212f 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -401,7 +401,7 @@ dra7xx_pcie_get_features(struct dw_pcie_ep *ep) return &dra7xx_pcie_epc_features; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dra7xx_pcie_ep_init, .raise_irq = dra7xx_pcie_raise_irq, .get_features = dra7xx_pcie_get_features, diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index dba83abfe764..d00252bd8fae 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -444,7 +444,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = artpec6_pcie_ep_init, .raise_irq = artpec6_pcie_raise_irq, }; diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 3be87126aef3..0852f42ad844 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -108,7 +108,7 @@ dw_plat_pcie_get_features(struct dw_pcie_ep *ep) return &dw_plat_pcie_epc_features; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dw_plat_pcie_ep_init, .raise_irq = dw_plat_pcie_ep_raise_irq, .get_features = dw_plat_pcie_get_features, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 4ab2e3dbd6bb..8a941f2fffcb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -193,7 +193,7 @@ struct dw_pcie_ep_ops { struct dw_pcie_ep { struct pci_epc *epc; - struct dw_pcie_ep_ops *ops; + const struct dw_pcie_ep_ops *ops; phys_addr_t phys_base; size_t addr_size; size_t page_size; From patchwork Mon Jan 14 13:24:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155477 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657067jaa; Mon, 14 Jan 2019 05:27:10 -0800 (PST) X-Google-Smtp-Source: ALg8bN5li3sGJHLUrHX6OxjIsRsBRH2iEtZ1b609bJoB3KCRYvpmlb8RGWZbnJkw9om0FITNztHz X-Received: by 2002:a63:cd11:: with SMTP id i17mr23049484pgg.345.1547472430084; Mon, 14 Jan 2019 05:27:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472430; cv=none; d=google.com; s=arc-20160816; b=lI/eLZRfst4h+EqZujDiA0rmFRcUieH+P9dO0SnLbA7Zrw6wRHWcfIAKopEGNVRlF6 ZobjQ8T5LDAziChJ8j6xW3wSB17Bv68A/rIKHc9d6Vo+GCRESUbdi7oRPz9LyO273hke y3R3cCZQKF4NeYFAMaOqNDEfCCdRbQbABPh492z1rqo95sUx4WbaCfTe9kmN3OSWMdrG E/9oMqwFBnoLKZ/mXH98UbxI9+LPsCVRsO/9b4LPSLm11hKOohlbBCoCagyJCHbVMmn9 /fXT/KUpGKg+zFkmUlPM8kbJdUvccoKAd8HHyLcBoHFb4EHfXk9nLx3TDfei29r3kTH9 GnMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=jYEVHutp0v29B4vfiqJTI22HzuJxQ7SOmOLmjmfhfQ0=; b=IEypINtg0mvsVJvHtN75Xr8S1SIH7pETO83r+L4pq2TIDFA8Z7m72H2Sdjshnh0cJG BpysU43BLb5Hvsc7WaE8U+yM09PTIAtCpR6DIip4Ut+Myvv4EcShrKEotRi1/f7xSsCG a/fOfxMqXFKfuxSCEWROiS4n5pWSLKajPXzkUYzRPV06D25i8re1xm59iutclS4WPKbi cUPzWfKnaEvnSLLSrR9wuZ1Lf0kHqD6GMHaeCF8baxXhrokqEcXUttTF8jns/PNzgNSh 4iXPIH22LYxQQttxv1uVG9KgwpYitI0eSasRb1J6XZnwWyixiiGSO1F4ivyFWAzzUMMY 9dVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LgOlGy4N; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v5si321303pgh.510.2019.01.14.05.27.09; Mon, 14 Jan 2019 05:27:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LgOlGy4N; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726987AbfANN1J (ORCPT + 31 others); Mon, 14 Jan 2019 08:27:09 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:41038 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726624AbfANN04 (ORCPT ); Mon, 14 Jan 2019 08:26:56 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQNdX041522; Mon, 14 Jan 2019 07:26:23 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472383; bh=jYEVHutp0v29B4vfiqJTI22HzuJxQ7SOmOLmjmfhfQ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LgOlGy4NgpIjpvhvjeFNp7k+EJqQaC1dStD2NaujHPGsfVGi23pgkpuDx/erK03sg doJ9gkfcp6JxCExzgpHNFAQP5N6B4UTHEFD4XihreaEcNP6b0y9OWxlln5wg8QdHJI KRCXx5OH1HjHTbr0/3UfrtrGuZqPxO6o3cFJDwJ4= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQNPu089642 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:23 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:23 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:23 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWe028516; Mon, 14 Jan 2019 07:26:19 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 18/24] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Date: Mon, 14 Jan 2019 18:54:18 +0530 Message-ID: <20190114132424.6445-19-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit beb4641a787df79a ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability and __dw_pcie_ep_find_next_cap for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present. This is because of incorrect ordering of "next_cap_ptr" check. Fix it here. Fixes: beb4641a787df79a142 ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index d5144781005b..cd51b008858c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -46,16 +46,19 @@ static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, u8 cap_id, next_cap_ptr; u16 reg; + if (!cap_ptr) + return 0; + reg = dw_pcie_readw_dbi(pci, cap_ptr); - next_cap_ptr = (reg & 0xff00) >> 8; cap_id = (reg & 0x00ff); - if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) + if (cap_id > PCI_CAP_ID_MAX) return 0; if (cap_id == cap) return cap_ptr; + next_cap_ptr = (reg & 0xff00) >> 8; return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } @@ -67,9 +70,6 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); next_cap_ptr = (reg & 0x00ff); - if (!next_cap_ptr) - return 0; - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } From patchwork Mon Jan 14 13:24:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155483 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657801jaa; Mon, 14 Jan 2019 05:27:48 -0800 (PST) X-Google-Smtp-Source: ALg8bN49O910H0VLduQziO8nMUmglegpHAwZIGMFmsKTMKslO+rMhc8cmgmVz6dSKi8ARANhbPbG X-Received: by 2002:a62:3888:: with SMTP id f130mr24861977pfa.132.1547472468220; Mon, 14 Jan 2019 05:27:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472468; cv=none; d=google.com; s=arc-20160816; b=C5T8zztAbVTqFPZN16hVLTP42W781NQZbO4dug1SLzm51wSVVKyWaQVTSfX2zqCusv RhIrNPClzXGR2ZteuEHBLN20hi+JVP7VNM2UOgYJiRqRnT9l/vy1WMKmDhXG0DUjD1nM 8V14GT10RlOt1ofWMtESPiB2Gb/3OaR23lwJymFd35CqB6msH8sc9tGRwwreL7ZabHec CgPozn52R+scQ6HUQBMoLT5ZKuTxVGnMF6kjSP5yMuaP8RUXHdSoAkTPx9FKY9VUXnKy wvqcP8QYmcJ4OgLbsnoAPOZQnFUnWPvUOWZfadU65Bu9O6h3H23GZ27DlHib8INAYXYb 6dew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Qffs6RSDOTYhNf6TDkmKFW38qdsa/BRhYFbUVoB22J4=; b=tOdn5KET2bC6XFt8gObGtVVcZjkx3PNjryE5YN+vAY0RQFbR5mZb6+IJt70eKa2WJd Da9oGCMp1PMIbRHhPhSvypQFv+BRwUXOxa9kNBZwjgbPmNKLR+WI54WRxLvjd2JNKejr Ju57ZTBXnWdWfWIXLgrkmfyoG4zlqh7EVq2VKfG1rnFkgbghLEmh/5labsvXcy/7oiGU XZj0IUnzp808/n/ydx7KR255DkRIp63rZwYYcOGhSO3oT8vCWKiNVO3p7NrzkPtpINaC OdTl4Qwdc8LYje4MPAA6fdoMlFCj+0mtPxkM3bSf8QeEAhTcg7ZTFx/zA+OsX/VsoYuR lGFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZHlcraTR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t20si331011pgl.211.2019.01.14.05.27.47; Mon, 14 Jan 2019 05:27:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZHlcraTR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726763AbfANN1q (ORCPT + 31 others); Mon, 14 Jan 2019 08:27:46 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37472 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726911AbfANN0t (ORCPT ); Mon, 14 Jan 2019 08:26:49 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQSj6098291; Mon, 14 Jan 2019 07:26:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472388; bh=Qffs6RSDOTYhNf6TDkmKFW38qdsa/BRhYFbUVoB22J4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZHlcraTRgFvdLrDPcTUXknoZdwb94KBedKntzDrJTghFt1ZL3U8VoZstrwHkjwdQb ld6sRDqbBnE6CwS3GxUYm0ruMmCvGw9kpZMwrdCrUmajB09zV1h4lsCGq45VQ/Vpjr O7lUzvZ5mrPJaCFptBTabyfEtSywmWcqWd7mJ+QE= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQSVj012686 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:28 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:28 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:28 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWf028516; Mon, 14 Jan 2019 07:26:23 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 19/24] PCI: dwc: Add callbacks for accessing dbi2 address space Date: Mon, 14 Jan 2019 18:54:19 +0530 Message-ID: <20190114132424.6445-20-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like TI's AM654 doesn't have separate address space for dbi2 instead they are accessed using the same address space as dbi with some configuration bit set. In order to support such platforms, add callbacks for accessing dbi2 address space. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 31 ++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++-- 2 files changed, 41 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 37506aba22fe..ccb68e6b6d54 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -89,6 +89,37 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "Write DBI address failed\n"); } +u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size) +{ + int ret; + u32 val; + + if (pci->ops->read_dbi2) + return pci->ops->read_dbi2(pci, base, reg, size); + + ret = dw_pcie_read(base + reg, size, &val); + if (ret) + dev_err(pci->dev, "read DBI address failed\n"); + + return val; +} + +void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val) +{ + int ret; + + if (pci->ops->write_dbi2) { + pci->ops->write_dbi2(pci, base, reg, size, val); + return; + } + + ret = dw_pcie_write(base + reg, size, val); + if (ret) + dev_err(pci->dev, "write DBI address failed\n"); +} + static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 8a941f2fffcb..066ff5cf4eae 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -215,6 +215,10 @@ struct dw_pcie_ops { size_t size); void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); + u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size); + void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size, u32 val); int (*link_up)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); @@ -246,6 +250,10 @@ u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size); void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val); +u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size); +void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, @@ -289,12 +297,12 @@ static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) { - __dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val); + __dw_pcie_write_dbi2(pci, pci->dbi_base2, reg, 0x4, val); } static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); + return __dw_pcie_read_dbi2(pci, pci->dbi_base2, reg, 0x4); } static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) From patchwork Mon Jan 14 13:24:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155478 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657157jaa; Mon, 14 Jan 2019 05:27:15 -0800 (PST) X-Google-Smtp-Source: ALg8bN4ld7WeRUSEDae7zCLkwi8YALb/G8gg4XnM2Nt2/o6T8jC4+1x6NyPGevKVQTOHMQxNeYCy X-Received: by 2002:a17:902:76cb:: with SMTP id j11mr25987406plt.179.1547472435034; Mon, 14 Jan 2019 05:27:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472435; cv=none; d=google.com; s=arc-20160816; b=WsCCWdRd4EPX1sy/+GMT8bD6k1+Lb9rMwesdePw792cbBvHLZ7bQ5HB4ZWNyn8fNX0 TyfWL+rBvqh9TVQXnQuJOjOfPEzP0qcjFMrQKBggwcge/46rV36WOBdHYtT3zuHOuQE1 osRF+ajVaqXZLB8SrfNhYG7jjZgqCNOzrNI6+lQSH5pmhyrMxR0njMcQ6a+C6YTZmdbY MBi+CNjB82uPBlH/dU9ylvKewV1VWahq/9Pega/N2gmuX8FR+2i9RbId7SrAGl7SvZ2G tMU1amrFjPblNDuzQiU2OYsAVm0zOHEnIr4/5r9hb03Zfw2zgpqAmJi4cAWkbK3reygt Tt3w== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id d16si360352pfn.169.2019.01.14.05.27.14; Mon, 14 Jan 2019 05:27:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Y1KwhfVk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727006AbfANN1O (ORCPT + 31 others); Mon, 14 Jan 2019 08:27:14 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35184 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726624AbfANN1M (ORCPT ); Mon, 14 Jan 2019 08:27:12 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQXCi107005; Mon, 14 Jan 2019 07:26:33 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472393; bh=bw0Ut73XkbaUy4HNJPK+MOEGDGM+u+KTb6J5j94keH0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Y1KwhfVka4uJtVqH+UZHTB9MPmcv9JfFP6wAJu8GqYdjYmcd/CrnP73a/WEE8g4yI xXOIvQBTHY5Js79l9EAGvDCb+FwxMgyY/GR1Vm89mdYUAYQ1UuaMFrSkeDC3BEqtK6 VVG3jttxejlFOX4LnasxKwQKUfRlSIxtRZmS3tP0= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQXC5012727 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:33 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:33 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:33 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWg028516; Mon, 14 Jan 2019 07:26:28 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms Date: Mon, 14 Jan 2019 18:54:20 +0530 Message-ID: <20190114132424.6445-21-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add PCIe EP support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/Kconfig | 23 ++- drivers/pci/controller/dwc/pci-keystone.c | 216 ++++++++++++++++++++-- 2 files changed, 223 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 0bb19e268a8a..ae3465fd194b 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -105,14 +105,33 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) - depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW_HOST help Say Y here if you want to enable PCI controller support on Keystone SoCs. The PCI controller on Keystone is based on DesignWare hardware and therefore the driver re-uses the DesignWare core functions to implement the driver. +if PCI_KEYSTONE + +config PCI_KEYSTONE_HOST + bool "PCI Keystone Host Mode" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + default y + help + Enables support for the PCIe controller in the Keystone SoC to work in + host mode. + +config PCI_KEYSTONE_EP + bool "PCI Keystone Endpoint Mode" + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Enables support for the PCIe controller in the Keystone SoC to work in + endpoint mode. + +endif + config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e2f4e7c01b5a..adeb3565c11d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -50,6 +50,12 @@ #define OB_ENABLEN BIT(0) #define OB_WIN_SIZE 8 /* 8MB */ +#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) +#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) +#define PCIE_EP_IRQ_SET 0x64 +#define PCIE_EP_IRQ_CLR 0x68 +#define INT_ENABLE BIT(0) + /* IRQ register defines */ #define IRQ_EOI 0x050 @@ -90,11 +96,16 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 +#define AM654_WIN_SIZE SZ_64K + +#define APP_ADDR_SPACE_0 (16 * SZ_1K) #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct ks_pcie_of_data { + enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; unsigned int version; }; @@ -850,12 +861,139 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } +static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + u32 val; + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_read(base + reg, size, &val); + ks_pcie_clear_dbi_mode(ks_pcie); + return val; +} + +static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_write(base + reg, size, val); + ks_pcie_clear_dbi_mode(ks_pcie); +} + static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, + .read_dbi2 = ks_pcie_am654_read_dbi2, + .write_dbi2 = ks_pcie_am654_write_dbi2, }; +static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + int flags; + + ep->page_size = AM654_WIN_SIZE; + flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); +} + +static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) +{ + struct dw_pcie *pci = ks_pcie->pci; + u8 int_pin; + + int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); + if (int_pin == 0 || int_pin > 4) + return; + + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), + INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); + mdelay(1); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), + INT_ENABLE); +} + +static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + ks_pcie_am654_raise_legacy_irq(ks_pcie); + break; + case PCI_EPC_IRQ_MSI: + dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + break; + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features ks_pcie_am654_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = true, + .reserved_bar = 1 << BAR_0 | 1 << BAR_1, + .bar_fixed_64bit = 1 << BAR_0, + .bar_fixed_size[2] = SZ_1M, + .bar_fixed_size[3] = SZ_64K, + .bar_fixed_size[4] = 256, + .bar_fixed_size[5] = SZ_1M, + .align = SZ_1M, +}; + +static const struct pci_epc_features* +ks_pcie_am654_get_features(struct dw_pcie_ep *ep) +{ + return &ks_pcie_am654_epc_features; +} + +static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { + .ep_init = ks_pcie_am654_ep_init, + .raise_irq = ks_pcie_am654_raise_irq, + .get_features = &ks_pcie_am654_get_features, +}; + +static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, + struct platform_device *pdev) +{ + int ret; + struct dw_pcie_ep *ep; + struct resource *res; + struct device *dev = &pdev->dev; + struct dw_pcie *pci = ks_pcie->pci; + + ep = &pci->ep; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->phys_base = res->start; + ep->addr_size = resource_size(res); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + + return 0; +} + static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) { int num_lanes = ks_pcie->num_lanes; @@ -923,7 +1061,8 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } -static int ks_pcie_am654_set_mode(struct device *dev) +static int ks_pcie_am654_set_mode(struct device *dev, + enum dw_pcie_device_mode mode) { struct device_node *np = dev->of_node; struct regmap *syscon; @@ -936,7 +1075,18 @@ static int ks_pcie_am654_set_mode(struct device *dev) return 0; mask = AM654_PCIE_DEV_TYPE_MASK; - val = RC; + + switch (mode) { + case DW_PCIE_RC_TYPE: + val = RC; + break; + case DW_PCIE_EP_TYPE: + val = EP; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + return -EINVAL; + } ret = regmap_update_bits(syscon, 0, mask, val); if (ret) { @@ -954,6 +1104,13 @@ static const struct ks_pcie_of_data ks_pcie_rc_of_data = { static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { .host_ops = &ks_pcie_am654_host_ops, + .mode = DW_PCIE_RC_TYPE, + .version = 0x490A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { + .ep_ops = &ks_pcie_am654_ep_ops, + .mode = DW_PCIE_EP_TYPE, .version = 0x490A, }; @@ -967,16 +1124,22 @@ static const struct of_device_id ks_pcie_of_match[] = { .data = &ks_pcie_am654_rc_of_data, .compatible = "ti,am654-pcie-rc", }, + { + .data = &ks_pcie_am654_ep_of_data, + .compatible = "ti,am654-pcie-ep", + }, { }, }; static int __init ks_pcie_probe(struct platform_device *pdev) { const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; const struct ks_pcie_of_data *data; const struct of_device_id *match; + enum dw_pcie_device_mode mode; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; @@ -999,6 +1162,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) version = data->version; host_ops = data->host_ops; + ep_ops = data->ep_ops; + mode = data->mode; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) @@ -1021,16 +1186,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return PTR_ERR(base); pci->dbi_base = base; + pci->dbi_base2 = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; pci->version = version; - ret = of_property_read_u32(np, "num-viewport", &num_viewport); - if (ret < 0) { - dev_err(dev, "unable to read *num-viewport* property\n"); - return ret; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "missing IRQ resource: %d\n", irq); @@ -1079,7 +1239,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->pci = pci; ks_pcie->link = link; ks_pcie->num_lanes = num_lanes; - ks_pcie->num_viewport = num_viewport; ks_pcie->phy = phy; ret = ks_pcie_enable_phy(ks_pcie); @@ -1106,7 +1265,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->atu_base = atu_base; - ret = ks_pcie_am654_set_mode(dev); + ret = ks_pcie_am654_set_mode(dev, mode); if (ret < 0) goto err_get_sync; } else { @@ -1115,10 +1274,39 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - pci->pp.ops = host_ops; - ret = ks_pcie_add_pcie_port(ks_pcie, pdev); - if (ret < 0) - goto err_get_sync; + switch (mode) { + case DW_PCIE_RC_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + ret = of_property_read_u32(np, "num-viewport", &num_viewport); + if (ret < 0) { + dev_err(dev, "unable to read *num-viewport* property\n"); + return ret; + } + + ks_pcie->num_viewport = num_viewport; + pci->pp.ops = host_ops; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + case DW_PCIE_EP_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + pci->ep.ops = ep_ops; + ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } ks_pcie_enable_error_irq(ks_pcie); From patchwork Mon Jan 14 13:24:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155479 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657283jaa; Mon, 14 Jan 2019 05:27:21 -0800 (PST) X-Google-Smtp-Source: ALg8bN72ywLA187zgs6ZBuvZeKFND9NykbzNjWoryz1g+VAgLynxHcj1gUUEPwRoIsknq5bMxRTH X-Received: by 2002:a17:902:33c2:: with SMTP id b60mr25418200plc.211.1547472441421; Mon, 14 Jan 2019 05:27:21 -0800 (PST) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id b27si332403pgb.107.2019.01.14.05.27.21; Mon, 14 Jan 2019 05:27:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EiD2ok1L; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727036AbfANN1U (ORCPT + 31 others); Mon, 14 Jan 2019 08:27:20 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37584 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726559AbfANN1R (ORCPT ); Mon, 14 Jan 2019 08:27:17 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQc6x098319; Mon, 14 Jan 2019 07:26:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472398; bh=WBTdWRfYLKWv54dEuesWhlPv+Ca+Oa1+3N9tCdOgMMQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EiD2ok1L6yzy+FmC75cU6k4+yTVtgx09w/7qmefhAVIHquBjNjL85yvF4VQM/RG69 owmV21aQxFDSOw1jfbwF3NzIHgYRrZYzP1+SXZ7COZmWEWznnYpM7bSxwO++APcuVu NjB7RjSCavhu1EofazTRK4/ErdxF6Grh0Qj01iP4= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQcBO012761 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:38 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:37 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:38 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWh028516; Mon, 14 Jan 2019 07:26:33 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 21/24] PCI: designware-ep: Configure RESBAR to advertise the smallest size Date: Mon, 14 Jan 2019 18:54:21 +0530 Message-ID: <20190114132424.6445-22-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Configure RESBAR capability to advertise the smallest size (1MB) for couple of reasons. A) Host side resource allocation of BAR fails for larger sizes. B) Endpoint function driver does not allocate memory for all supported sizes in RESBAR capability. If and when there is a usecase required to add more flexibility using RESBAR, this can be revisited. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-ep.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index cd51b008858c..47cc06bac91f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -502,10 +502,32 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) pci_epc_mem_exit(epc); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + int dw_pcie_ep_init(struct dw_pcie_ep *ep) { + int i; int ret; + u32 reg; void *addr; + unsigned int nbars; + unsigned int offset; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; @@ -589,6 +611,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (offset) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + dw_pcie_dbi_ro_wr_en(pci); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); + dw_pcie_dbi_ro_wr_dis(pci); + } + dw_pcie_setup(pci); return 0; From patchwork Mon Jan 14 13:24:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155485 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3658016jaa; Mon, 14 Jan 2019 05:27:58 -0800 (PST) X-Google-Smtp-Source: ALg8bN7fT2wSMM5CGwbTuQVOYZ5ymBYJjzarjMN+ph1swHlRRLK1wiKvWTWnlI+SEk9QHyuSUCN1 X-Received: by 2002:a62:ca9c:: with SMTP id y28mr25236197pfk.236.1547472478699; Mon, 14 Jan 2019 05:27:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472478; cv=none; d=google.com; s=arc-20160816; b=QR2/HViAi6qAOFK0Dq5DKM3Uucoj70lx5PFxsS3eyQnebmmBgQW7i13YoLKJU7lcQy sfQ6/WDK5yWFNXG9dYFhV8aOyeP2eHIUSXk6ei2NK3k8j4JfH381l0a4FY29tiIiCHrF kjt5nIrqX3eDnuFBRaVV6JIMHLBDWbmJhbkn/OR/N7/YM3Zqw2Wf1LgiwaVamGDog+6E OYc2/Sbl7mHmGwXIJca/V6PA4e/4ifE2k1E2XeJJqjjTHmeAxN/olhb2Bd+JbD1MRwq8 UJYfVF0tBA32m8dlxUzCDxnZ4vSkbgBiBprraZVCQv5+xlhW0J/Ayn1M4kPvghIdTyEV FduA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0PiaQYnV59ccfwEhn8gPR5j82jBP2sS0jMXzDzaA8TY=; b=bjA1FyE/towRZZ5yUY5cjPoWjt9a3tqRYtyzWSoMa8A3mc/1JdACXzKrmHNhtkPd7X RGRZV8kf0jCm42lSNxFOWN0Z0cPXusK7NW/FF8iuh3ntklDiF7IOWECmdnSnwNUSdsO6 OGQIfBJvQ2BNmArEVFjwiNErDkIW2LAoaVV+ikl3dtBl4rcSe8/sQVec/T0Pr0Sl90N+ vU4LQt9+6qhEZrA8XlhNNHR3thKXX0jnVsXNshVelHUI9DmwdHDtvHOs3zvyV7NkU1U5 HU0dgMwlTWEmjWzshmYbi+2aJlzjs1s4ho0xUu2vEiYN6p2glKM+BUu8I7KkWikCB3Cy +YOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hFhA8QE8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a12si372201pll.112.2019.01.14.05.27.58; Mon, 14 Jan 2019 05:27:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hFhA8QE8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727074AbfANN15 (ORCPT + 31 others); Mon, 14 Jan 2019 08:27:57 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41344 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726717AbfANN1z (ORCPT ); Mon, 14 Jan 2019 08:27:55 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQmWa019648; Mon, 14 Jan 2019 07:26:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472408; bh=0PiaQYnV59ccfwEhn8gPR5j82jBP2sS0jMXzDzaA8TY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hFhA8QE82uMeSb5OF7qMlUx6XubeLPJNUbOTu8pcgaQaL98xcm7YrnF8fMnDsopih 7trFXBk+ZF6gKvoVgNkgxThAyfJOGvhWTOXhA+L2cb8LCuqsAyoBQnprtQsrnsGoCv mUKcD/laa7eRygEsk9MHJAKduAPXVkBzQRUa1WBg= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQmfb095069 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:48 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:46 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:47 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWj028516; Mon, 14 Jan 2019 07:26:43 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 23/24] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Date: Mon, 14 Jan 2019 18:54:23 +0530 Message-ID: <20190114132424.6445-24-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to application registers. "PCIe Inbound Address Translation" section in AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 is reserved. Configure pci_endpoint_test to use BAR_2 instead. Also set alignment to 64K since "PCIe Subsystem Address Translation" section in TRM indicates minimum ATU window size is 64K. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 896e2df9400f..6dfaeeaeec0a 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -75,6 +75,11 @@ #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 +#define PCI_DEVICE_ID_TI_AM654 0xb00c + +#define is_am654_pci_dev(pdev) \ + ((pdev)->device == PCI_DEVICE_ID_TI_AM654) + static DEFINE_IDA(pci_endpoint_test_ida); #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ @@ -588,6 +593,7 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, int ret = -EINVAL; enum pci_barno bar; struct pci_endpoint_test *test = to_endpoint_test(file->private_data); + struct pci_dev *pdev = test->pdev; mutex_lock(&test->mutex); switch (cmd) { @@ -595,6 +601,8 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, bar = arg; if (bar < 0 || bar > 5) goto ret; + if (is_am654_pci_dev(pdev) && bar == BAR_0) + goto ret; ret = pci_endpoint_test_bar(test, bar); break; case PCITEST_LEGACY_IRQ: @@ -785,10 +793,18 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) pci_disable_device(pdev); } +static const struct pci_endpoint_test_data am654_data = { + .test_reg_bar = BAR_2, + .alignment = SZ_64K, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) }, { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), + .driver_data = (kernel_ulong_t)&am654_data + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); From patchwork Mon Jan 14 13:24:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155480 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657353jaa; Mon, 14 Jan 2019 05:27:26 -0800 (PST) X-Google-Smtp-Source: ALg8bN7lrnSogkHe1NhO3Dl87rJV+3pZa1+rQmNBM2tti8vwfVQW5cg48OZ60AfALWMWMiDFYxaz X-Received: by 2002:a17:902:20c8:: with SMTP id v8mr25685010plg.319.1547472446083; Mon, 14 Jan 2019 05:27:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472446; cv=none; d=google.com; s=arc-20160816; b=wXXv90kWgFu7awLRx20I22tTxm2KGM6c1wv8vWNyGAvWasm8ErsYcGVRjZE34MpUWn aGkSiZ240QrcTdgNorXgIC9lYCeu3XSobkWAc3DMXfZQEP6jm2uHGTmTqT7JRYyl1xbu GkhRh2NhUdiDNz491vjEVTqt3AIW01Ph4FHTk4IhNe452QMJ8vQb5oWoBa0KDV2KsdIg rWeFsvTw1PSjyBFfWL+TappObva097vnbdWa0FBoLcXPqoK8R6VGj7Hh8JFhj3EEauBW x1TP+pzlYVcUcS2jGEVoM3zkZtf/5anAHvzssKSy0mmMOHbWuBCfDw9hwP7v1SsNAa8c 8r1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=yRUr73ZiS5aNXYVmbXRtJ0JSqktNkC+89EIMn+yRODs=; b=sTr8sujL9IOaVFRk5eZFi/St3SEA5CoGvxVZpQCgpTVNYnx0iFi2IPPTdkQoFAntqs ENGo2LlYKcukpDWh2KMvXTnSxSum2WJNYsdGcZjlTyn7Xz8yYkL8qbPAZUXGIV/4YHnD 8rzU5LcGSOrnGxkSgb9e95kIIvWAnx8dTs7s/iQ9GNH6TzjVdBV0XAqNjyvmxYLv5oiT +9Dnwy29Mb3N4baNGDMWfLOmMb47eKtaSISwcvRC7pnevI6H0aZBh9U/jdhbB72kzqbW MrKencQyqrnMMBLt4W8NjiiWDR2boRaCJkqpSQ9jLgfvKIp/Lu3id48eQq4sybtFZJn+ 6skg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=x62GVg5Y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z123si429499pfc.97.2019.01.14.05.27.25; Mon, 14 Jan 2019 05:27:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=x62GVg5Y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727021AbfANN1T (ORCPT + 31 others); Mon, 14 Jan 2019 08:27:19 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37566 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726680AbfANN1N (ORCPT ); Mon, 14 Jan 2019 08:27:13 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQqpT098392; Mon, 14 Jan 2019 07:26:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472412; bh=yRUr73ZiS5aNXYVmbXRtJ0JSqktNkC+89EIMn+yRODs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x62GVg5YvVaKS6/uQKvz32FziutO1EpLH1sHg6A/rpxXMq3mevZ1inmhKQVsln9/T zFWfOSPhII8wq3ipSpFNcWpkF1tuA5CniQ+QisLkL2tmYtu7bfsoCLQSabBooIlHQc Hw2bPkVvwVqx8Aq3vY5VNoXGdx96oEqWf/bcJGJQ= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQqKK057603 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:52 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:52 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:51 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWk028516; Mon, 14 Jan 2019 07:26:48 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 24/24] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test Date: Mon, 14 Jan 2019 18:54:24 +0530 Message-ID: <20190114132424.6445-25-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR") while adding test_reg_bar in order to map PCI_ENDPOINT_TEST regs to be mapped to any BAR failed to update test_reg_bar in pci_endpoint_test. This results in test_reg_bar having invalid value when used outside probe. Fix it here. Fixes: 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR") Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 6dfaeeaeec0a..46788fe854e4 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -670,6 +670,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, data = (struct pci_endpoint_test_data *)ent->driver_data; if (data) { test_reg_bar = data->test_reg_bar; + test->test_reg_bar = test_reg_bar; test->alignment = data->alignment; irq_type = data->irq_type; }