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Fixes: 657774acd00f ("ASoC: SOF: Make sof_suspend/resume IPC agnostic") Signed-off-by: Peter Ujfalusi Reviewed-by: Ranjani Sridharan Reviewed-by: Bard Liao Reviewed-by: Pierre-Louis Bossart --- sound/soc/sof/sof-priv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/sof/sof-priv.h b/sound/soc/sof/sof-priv.h index 9d7f53ff9c70..58bcb8d6f72b 100644 --- a/sound/soc/sof/sof-priv.h +++ b/sound/soc/sof/sof-priv.h @@ -376,8 +376,8 @@ struct sof_ipc_fw_tracing_ops { /** * struct sof_ipc_pm_ops - IPC-specific PM ops - * @ctx_save: Function pointer for context save - * @ctx_restore: Function pointer for context restore + * @ctx_save: Optional function pointer for context save + * @ctx_restore: Optional function pointer for context restore */ struct sof_ipc_pm_ops { int (*ctx_save)(struct snd_sof_dev *sdev); From patchwork Fri Jun 10 08:35:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?P=C3=A9ter_Ujfalusi?= X-Patchwork-Id: 580652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 729B7C43334 for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10373"; a="302936604" X-IronPort-AV: E=Sophos;i="5.91,288,1647327600"; d="scan'208";a="302936604" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2022 01:35:20 -0700 X-IronPort-AV: E=Sophos;i="5.91,288,1647327600"; d="scan'208";a="638020836" Received: from nuribebu-mobl.amr.corp.intel.com (HELO pujfalus-desk.ger.corp.intel.com) ([10.251.215.108]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2022 01:35:18 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org, pierre-louis.bossart@linux.intel.com Subject: [PATCH 2/6] ASoC: SOF: sof_ipc_pm_ops: Add support for DSP core power management Date: Fri, 10 Jun 2022 11:35:45 +0300 Message-Id: <20220610083549.16773-3-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220610083549.16773-1-peter.ujfalusi@linux.intel.com> References: <20220610083549.16773-1-peter.ujfalusi@linux.intel.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, yung-chuan.liao@linux.intel.com, ranjani.sridharan@linux.intel.com, kai.vehmanen@linux.intel.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Add a new ops for handling DSP core power state which can be used to tell the DSP to turn on/off a core (or to inform it that a core is going to be turned on/off if the core is host managed). Signed-off-by: Peter Ujfalusi Reviewed-by: Ranjani Sridharan Reviewed-by: Bard Liao Reviewed-by: Pierre-Louis Bossart --- sound/soc/sof/sof-priv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/sof/sof-priv.h b/sound/soc/sof/sof-priv.h index 58bcb8d6f72b..0544eb6a2322 100644 --- a/sound/soc/sof/sof-priv.h +++ b/sound/soc/sof/sof-priv.h @@ -378,10 +378,12 @@ struct sof_ipc_fw_tracing_ops { * struct sof_ipc_pm_ops - IPC-specific PM ops * @ctx_save: Optional function pointer for context save * @ctx_restore: Optional function pointer for context restore + * @set_core_state: Optional function pointer for turning on/off a DSP core */ struct sof_ipc_pm_ops { int (*ctx_save)(struct snd_sof_dev *sdev); int (*ctx_restore)(struct snd_sof_dev *sdev); + int (*set_core_state)(struct snd_sof_dev *sdev, int core_idx, bool on); }; /** From patchwork Fri Jun 10 08:35:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?P=C3=A9ter_Ujfalusi?= X-Patchwork-Id: 580651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C690CCA47B for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10373"; a="302936631" X-IronPort-AV: E=Sophos;i="5.91,288,1647327600"; d="scan'208";a="302936631" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2022 01:35:24 -0700 X-IronPort-AV: E=Sophos;i="5.91,288,1647327600"; d="scan'208";a="638020880" Received: from nuribebu-mobl.amr.corp.intel.com (HELO pujfalus-desk.ger.corp.intel.com) ([10.251.215.108]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2022 01:35:22 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org, pierre-louis.bossart@linux.intel.com Subject: [PATCH 4/6] ASoC: SOF: ipc4: Add set_core_state pm_ops implementation Date: Fri, 10 Jun 2022 11:35:47 +0300 Message-Id: <20220610083549.16773-5-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220610083549.16773-1-peter.ujfalusi@linux.intel.com> References: <20220610083549.16773-1-peter.ujfalusi@linux.intel.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, yung-chuan.liao@linux.intel.com, ranjani.sridharan@linux.intel.com, kai.vehmanen@linux.intel.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" IPC4 uses the SET_DX message to enable/disable cores managed by the DSP. The dx_state.core_mask indicates which core is going to change state, the dx_state.dx_mask is to power on (1) or off (0) the core. In the dx_mask only those bits (cores) checked which bit is set in the core_mask, other bits (cores) ignored. Signed-off-by: Peter Ujfalusi Reviewed-by: Ranjani Sridharan Reviewed-by: Bard Liao Reviewed-by: Pierre-Louis Bossart --- include/sound/sof/ipc4/header.h | 8 ++++++++ sound/soc/sof/ipc4.c | 26 ++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/include/sound/sof/ipc4/header.h b/include/sound/sof/ipc4/header.h index b8b8e5b5e3e1..a795deacc2ea 100644 --- a/include/sound/sof/ipc4/header.h +++ b/include/sound/sof/ipc4/header.h @@ -385,6 +385,14 @@ struct sof_ipc4_fw_version { uint16_t build; } __packed; +/* Payload data for SOF_IPC4_MOD_SET_DX */ +struct sof_ipc4_dx_state_info { + /* core(s) to apply the change */ + uint32_t core_mask; + /* core state: 0: put core_id to D3; 1: put core_id to D0 */ + uint32_t dx_mask; +} __packed __aligned(4); + /* Reply messages */ /* diff --git a/sound/soc/sof/ipc4.c b/sound/soc/sof/ipc4.c index 658802c86685..b2cb92745ec6 100644 --- a/sound/soc/sof/ipc4.c +++ b/sound/soc/sof/ipc4.c @@ -597,10 +597,36 @@ static void sof_ipc4_rx_msg(struct snd_sof_dev *sdev) } } +static int sof_ipc4_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on) +{ + struct sof_ipc4_dx_state_info dx_state; + struct sof_ipc4_msg msg; + + dx_state.core_mask = BIT(core_idx); + if (on) + dx_state.dx_mask = BIT(core_idx); + else + dx_state.dx_mask = 0; + + msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_DX); + msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST); + msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG); + msg.extension = 0; + msg.data_ptr = &dx_state; + msg.data_size = sizeof(dx_state); + + return sof_ipc4_tx_msg(sdev, &msg, msg.data_size, NULL, 0, false); +} + +static const struct sof_ipc_pm_ops ipc4_pm_ops = { + .set_core_state = sof_ipc4_set_core_state, +}; + const struct sof_ipc_ops ipc4_ops = { .tx_msg = sof_ipc4_tx_msg, .rx_msg = sof_ipc4_rx_msg, .set_get_data = sof_ipc4_set_get_data, .get_reply = sof_ipc4_get_reply, + .pm = &ipc4_pm_ops, .fw_loader = &ipc4_loader_ops, };