From patchwork Fri Jun 10 07:21:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 581245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5E95CCA482 for ; Fri, 10 Jun 2022 07:22:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346728AbiFJHWq (ORCPT ); Fri, 10 Jun 2022 03:22:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346721AbiFJHWm (ORCPT ); Fri, 10 Jun 2022 03:22:42 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF1393F333; Fri, 10 Jun 2022 00:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1654845718; bh=IQX8e4DimYSxfYiB0892MoZKJaCfS7TtVYY2navJcRE=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=CuMibIAZmB/ve2MuTr1f1+wZVderTUs7KGiC13adrseH2oLgJT4zT8wqkV4hqMauL 8W7TK1+u22oOoDY+LIJa8HI9JXrLrseZbbirKlJmpgTR57jaaVfz2mLGe9ob7FDjlf D3eeelWzAIdUfOHB8PbJG+WpyqqpqS1JuXdF7UJ4= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.195.3]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MuDXp-1nlLT91uOb-00ucv9; Fri, 10 Jun 2022 09:21:58 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v4 1/6] dt-bindings: timer: nuvoton,npcm7xx-timer: Allow specifying all clocks Date: Fri, 10 Jun 2022 09:21:36 +0200 Message-Id: <20220610072141.347795-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:yBVwif+DGktWM+o9r7sNiZrEwl/zKMtKSiq2+UCGtlsbNtgIk7x /bbX2sXzYaXAHSx44puYxomiEoqtXeh96nX3Juh/ZB+ZLZn7Na1fVtezN2XCv8yIcCHMfOp 6fh5zvIqvP5lpYYiQJ7clKDGsnJE+kiOYvK6wveqk+3IERfbN/R0A10m7PgewWhnTtZnhXG pxyEgviIcFGYC0xKZ2leg== X-UI-Out-Filterresults: notjunk:1;V03:K0:OysjaKN0sh4=:FlL2Ak8DjTMz8OOajXTmsw tDNGd70HsIgiPxXBYKsnztMa+Fk+Pml/h35M59WmgIjr6X7U/mOLkuQ2CqYDhU+5QtbWB9UTx nq2ioahzPVyDN57LmqmaFIppfYPuPZQz3APeIcRze5Qd7FnCtu4OhWynBIF+3J8ymqX1RjTxN fgoTN9Q/YbgvYTBFlVib8DB7ZSJkH/8Wnp4bcL0GfereOLuFkqzXWT82pCKgG6/CcRdO6APNO 1R/KMbXovtwtwuvHr9U4HVg4jjG86Lcb6FBhONxvyYH3nQTAtAmE/jpSoA7jNFfK8YsEuW0nC pxpCMS/iGnCkNaQD7uwxPRf5J5lOnpPzeKat0wsEq27rJbwhnDzgfm/3682Pe/1OrPRsXJRvi u56mUm4jdBx9VgD3xlauvcTHaFVap/4K+OFihvebbxT+oiR+OE1wJDINFPhwAuEGg8ap6oAbC jCaKogVszBpVuu1YBoz8dd1YoVOOPWH/CnRzgt3OUUsSGrkRr79o9cQlPp7mgPln6y8mnfYF8 b+9RWX1AYtt9Sf8pPCVs4Mra1Lp4tqVyEqqG8Z/b2bjbCJMtSbruwpExkvVWClZvhfGflRkBm 1+K6IVodoq+l8UNxpIKMA6UXhfjd5PNC75ZD5laQh0aobHF5SdjXMS0HM7XPaJ6BCnEbt8Ycu jfYp1Sj5wc1VD/NZg32B4hlS3/YGSBK3BA+B7p85BiFB7rQwOlGglNi7Wfy7A/KlwQ+6yCj2k seHkoCEKI9cJd11pQj5Z3+MVwEzs7SbugxIKmKM529HEXfKvR6+oqzRRHfnLr2m7a6dnnPDUW fHgmCami6/UnQ5crYy/O8IH2CzMEvWH5aFsZfCtpd9S0idSlkYOMxnkOTZHbG2NVUPOOOomo7 9IzKqpehLW3E009ZA8NoQKXcbIZA23AcI75h7CVRD2RMqjkNCgAUqwB0DINaC3CyrCkyIbqeN 8b7qgM8JDN0TAAGrqtBD+kZOphVKi/KJeT08BpqepDP6olk2r9fcmu/HCQhodinlbp/AoT1ex znrsGHZEmt8fmE3gExnaK0Xp0JVSqUZlQYMKsoOB8lhzR6lo7kVeJ0UnAGZrs35dljK6FJVVj BBjbXARDBPTVPT7acTieD/ZFkAbFNfWWZp1yyqGUjLXPrQqO1sU2WQ0Rw== Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The timer module contains multiple timers. In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring --- v4: - no changes v3: - Add R-b tag v2: - no changes --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 0cbc26a721514..023c999113c38 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -23,7 +23,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible From patchwork Fri Jun 10 07:21:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 581117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03E06CCA483 for ; Fri, 10 Jun 2022 07:22:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243390AbiFJHWr (ORCPT ); Fri, 10 Jun 2022 03:22:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346722AbiFJHWm (ORCPT ); Fri, 10 Jun 2022 03:22:42 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B65CC2252D; Fri, 10 Jun 2022 00:22:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1654845720; bh=j3UY4Dc5ZucxvZOdMQ7G7i2RlA13OGQcUuT05UZhmlk=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=lrCxQu9gPZP3aTtP+UdnRHWcryV1DB5W2tdNllB/hHoADU5AIO68QL4iVdWEPrdkN uhkduHL2Xr+UBH+N56b/a9IAxSGQa9tMpOh+daXNdh9Amk+1OwaRi8REfB/xke2xRB NlcaB0jBp1x1pR/OrJLhBaUFTQNO5sjxuz6XcS20= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.195.3]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MmDEm-1nHOWl3D28-00iBNh; Fri, 10 Jun 2022 09:21:59 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v4 2/6] watchdog: npcm: Enable clock if provided Date: Fri, 10 Jun 2022 09:21:37 +0200 Message-Id: <20220610072141.347795-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:2PiAR+PAhe6XaqU2LmLRzu4DoKNpDPyrJc4JH5huBAJPKh+QUNk GEOzDpM+bZrgsa1BmNgoDOQ9r66cVZRKjcB3alQsW8GAJNY5NTAIFTyua7z/2ENIPnoKfBR BQ6JrUUmfgyglEnddnaRGGdiltOocyvmmNIeOACq9Jy9kcSLBtCwaTme7HPgmzagYVKKsg+ mHOzIFNgctCPazzIs/Esw== X-UI-Out-Filterresults: notjunk:1;V03:K0:D9zi4Na8zUY=:55BG0Xozf1f51tRz3AJXiU ZJOA8AbZhrjhSU9ZfCSIhITEd6u7YHNKiXNiuEuKOWWJ9jwkiNNdBibHFNTyYJWmoQQRmjO3a I0PIU6SV/2KbtdDQzO9+ABPcQ70vgZUtAKGQL+DMKrwqNYRzkIlTTqusqbKFEXHcvuO3E9x7l W8j8fAw+ogjXTujng5Unmmecd2yfeniwRt/2lBtrZNPgo0oAziP8O/Cu3n7NsSJhF7EQ8V9wF bqQovlPWTPdroQ+zbmpMMSv0JFpINjk7kNbV7IA1JDrdKFrIGy8QoT67cC6B8sqagok0+Cnwo Yj3GMi1dHWJrtyv8eapck4/pF8iTqA1zY+KKuSv5JLej+o/uOcgG8slLw6VsXdkBlR7CX+uyo a6+1+gn0u2MLcdTpHBdx1xtxE3lEjH6fC8uU0Ji0zKI+9Je+BC95+wf45UpZ/eon9MXJxJVEb uF82Z+fWMVmHZQLDRHhEVYCyA+b/izxpCREc3Zedx76FlPjpH0FCHhZyRPjzfj2dKTWkojcJd fhlndhVuJRdQUm0WIG6A7/XaursXc7hoKJLltyP+1TFPUBbctoGzlyBAHet9JHCETbJfoVAUP Prz8+Tdw2csBL+pwj9oN7xN2YY37b8KIwrfIk33NS+f5kWsSMaQ+sBD5OM6FvRFj0fGuIId00 Y6cJB6PLmBMc5Gjk9n9U7VJH3A+ZwF+q6NVuaZ+iPtHDGiObJJjueDP4LBPNUau0VuuaaAStP xlNahj37Ym13uG5ECZe87uDB0+uqp1NzImp4x1R8BRn/yiopZvA9X1DIftmMxEKPEYXtVsndm 1pdF6m35qjjV17DRN9O4hc+qE+JBTcLPD+/+8iUqt0eF8K9tkHAUMk56FfcKyVf7wODhPOeQ7 T0H54ZAPDlylAxeYTmjnkvJS+yqhxQQm9hIKzXvgcOHzlphzi9hsFwmavftBWUE57AWcOaRLK JheqBkeOer37bDkx94pCawOd8EOiVPKMqCLydSChrvVf5hHt/doNkVDQzpf6ab+ndGihtphix 80ZKWQhJLaRvAlz0Xfc8RicvePFT6R0XKPTcAB9xkrsLOUJ6hC+9mS677sIrwAiTTfYP2dTo0 3Tl3ZvxHzu0Mo1RhTCb5fBTxmHO/7RduiljXXG3hy07PHaj8E88uqhDzA== Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org On the Nuvoton WPCM450 SoC, with its upcoming clock driver, peripheral clocks are individually gated and ungated. Therefore, the watchdog driver must be able to ungate the watchdog clock. Signed-off-by: Jonathan Neuschäfer --- v4: - Don't disable clock in npcm_wdt_restart function v3: - https://lore.kernel.org/lkml/20220508194333.2170161-4-j.neuschaefer@gmx.net/ - Add enable/disable calls to npcm_wdt_restart handler - Not applied due to the above change: Acked-by: Guenter Roeck v2: - https://lore.kernel.org/lkml/20220429172030.398011-4-j.neuschaefer@gmx.net/ - Add clk_disable_unprepare call, suggested by Guenter Roeck v1: - https://lore.kernel.org/lkml/20220422183012.444674-4-j.neuschaefer@gmx.net/ --- drivers/watchdog/npcm_wdt.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.35.1 diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index 28a24caa2627c..a5dd1c2301374 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -3,6 +3,7 @@ // Copyright (c) 2018 IBM Corp. #include +#include #include #include #include @@ -43,6 +44,7 @@ struct npcm_wdt { struct watchdog_device wdd; void __iomem *reg; + struct clk *clk; }; static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) @@ -66,6 +68,9 @@ static int npcm_wdt_start(struct watchdog_device *wdd) struct npcm_wdt *wdt = to_npcm_wdt(wdd); u32 val; + if (wdt->clk) + clk_prepare_enable(wdt->clk); + if (wdd->timeout < 2) val = 0x800; else if (wdd->timeout < 3) @@ -100,6 +105,9 @@ static int npcm_wdt_stop(struct watchdog_device *wdd) writel(0, wdt->reg); + if (wdt->clk) + clk_disable_unprepare(wdt->clk); + return 0; } @@ -147,6 +155,10 @@ static int npcm_wdt_restart(struct watchdog_device *wdd, { struct npcm_wdt *wdt = to_npcm_wdt(wdd); + /* For reset, we start the WDT clock and leave it running. */ + if (wdt->clk) + clk_prepare_enable(wdt->clk); + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg); udelay(1000); @@ -191,6 +203,10 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->reg)) return PTR_ERR(wdt->reg); + wdt->clk = devm_clk_get_optional(&pdev->dev, NULL); + if (IS_ERR(wdt->clk)) + return PTR_ERR(wdt->clk); + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; From patchwork Fri Jun 10 07:21:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 581243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5431C433EF for ; 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Fri, 10 Jun 2022 09:22:12 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Krzysztof Kozlowski Subject: [PATCH v4 3/6] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Fri, 10 Jun 2022 09:21:38 +0200 Message-Id: <20220610072141.347795-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:oBCOVoQiYTeIEeH6b1Ro7wMEWAN7NkTLykjMJfZGa+J7xGKQhzZ a6ne3cy/bSOv+OY/6OoQBHJu8Ufm3dUgzf14gUvrBIr7WhO2ToN//NDK6TXvFZxzUykzc8j 82pZHIeow6pL04QMpuARrnu63H1zAR1AOPFhl2y5+CmACK8h010dISuB998jGcRZxf+YroH EpG9ZjdNe/T4gr0EG2nWA== X-UI-Out-Filterresults: notjunk:1;V03:K0:KecseXm5aMc=:e6YrHlomRt8ARNEcnULCkk TcentPRMksSZqXLh7+RMzFwuv/ZpRCrmu2fK8F96k44BA6nmWCfeEn4eMabWZ7/Zax8bai9Kg IbOWuiBiT3rJRuagHnteIe/QFzPUVkrn/GpPHk0VBhoLwR/M0bDJYdbCZyoLeL5bFeXQVTdSP Tl9NvYL0FD7ILYmCMaS2SEnd0Iqp+HUO19Pxs9m0Gcglr35Km65WAGmy01uFsvEK81ryGQWtv i3yAP1Qvk0Q6Xm918V3HsSR6FPvpFS+JbHykS3Kks+yBU5SMwbQniJMPl19NiAY1d9+4zKrZq bIyIIhczlYzzT5rSf7eTXNY8Ew6/jG1TNA5i5l5BKI+j93IQvjtS3rJXKuOyyTU7bPSP4BKpj vu2nEpbxRjOe05fKY3B2SBOWhTt5T97LGyVe3apPFh1V3TFL0l5oAWm1XXOY9AwELJpLzSPHq TX8v2A7ov2ZYQSi7KbhPQhWOMS5tTZ1XTyB11wLZs7cdmhrJIC1k6Bo2u7hl9NRJYQEZzhkBC vXDf0fVk8Z0rCQSbx55ivI0ygP9zIcyiVY+yGyR6ix0IID2pCmxxKHLf+bJAnDr7Xt3cEJlXR 2KR5I02q2PUE/6ZFJBGZc3v8rFDGvXyu3TerRwMCv0mjv7pn4If3wHNsPA4SLKwgErYP9G6BO T5z6iuLPJYLqOB6DlXv/jI38u0TZuOrGCe1WNn5wLdRF2n2bIjB4ZDuxJVLNLgmRr4XAICLjo fXLUADEm9o6OoYfo2/MdsqyoL6t24CC+F8vAYwsiIQH0pdw2JTimg0oOt2XZXsZ8/y/YrqzOa kYEDD3dTgUbE9BxzH3btdY8op/qWZPcBcW+vHN2kBUtDtAmaJB/cN3kkLEkDxVjFNCMiTtyh9 Uv0mbd8hlwlKGIb0ChXTqZh1+EQnkqfVY+N/YBaXGRgTPs+SsfWxn9plU51Bw7grEWWd40sry 9OusBzIb+sEIhniqixK1s2H5cIvFizfevPtAMJPCVZnleprwR5PARHByExsQU7NFyqUXGdoF4 Nra0rWQgXqEFfp3Fy0zK3qkNu+ZVscnFXvIEccl8apVTM5roiUdH1RzRNagi84kqH8V1+KxvO xuRGachzOVfPugocd+yR7OAowWujGqBwuuh1tn4q9nVW7a0AdJXiNBh6Q== Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v4: - Add R-b tag v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..525024a58df4c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */ From patchwork Fri Jun 10 07:21:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 581118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD7F7CCA47F for ; Fri, 10 Jun 2022 07:22:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346709AbiFJHWp (ORCPT ); Fri, 10 Jun 2022 03:22:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346717AbiFJHWl (ORCPT ); Fri, 10 Jun 2022 03:22:41 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEE1B27CEE; Fri, 10 Jun 2022 00:22:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1654845734; bh=NbDW4XwdgK46oK2YiOWDkK6AGkXvlfDDkYk+K6FV4wk=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=RmpFEGmRk+oiHoUPgCkFP9znHCxEBnurmy/o+eYeEtkVLfJpsNKuW9/AbTpq+Wlle V7Q3Hh2ak0h3ime1UaCOiVv9pjWdx2C0j07LjMeoD3Iax7W7nneQwqDL/4Z8IcNPw0 2KIBQb/rIpG/yvyw2RC8Vr1Iuq5RvXgnchAeYoks= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.195.3]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1Mf0BG-1nWGtz3AdO-00gXtd; Fri, 10 Jun 2022 09:22:13 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski Subject: [PATCH v4 4/6] ARM: dts: wpcm450: Add clock controller node Date: Fri, 10 Jun 2022 09:21:39 +0200 Message-Id: <20220610072141.347795-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:BXn0QGc3JuUPTaSOXaj6sTF2BeHa/XxMxh/h2OaaAJOa3Q9w41S XaTeKudTF7JB8x0yO0Xej2toVOlo7h7XC/4bkGJq8tago4kmd9REtJPypCdliGhmTbwOGwb usOsY1my7tUegRcMeSv8lvJ5dy69usb3bVy5BL6O3reQIhKl1b70OtMyOI7cpSNS72u+3Nl 2dj42D2wRoo4j6bZY3qhQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:vajEJH9ax24=:Pw5Pnl/rdMY3cOgPy4E2Bo mVMScqEXaK4KXwGkclcOzeo8mEWZG8p8Z9fLftKud2AcsSioBqASCH4j24t55R1FRQUBeOaYI Tp9gqyUmoawwlugMaukYO6I2mJVpdgcxwG9a/ymqJ6ZlQuqA3+Bf6X3Z+1LixQpM49Bj/TumG qecOoeSzR9vm0Pk3Ehe/L9ZNPEUaXWJ7ehrBIWaD+X/1QbeJlikizcsvXKk9UYKDjZNqZ18Xw XCvcgN3YdxXlDhyVgkBTp8JCXiy6JMpRt1oC0+m5VkFRXVQJ36Iq7lf8o05F0KOnfizKZ8HKX h3sURq3DlSYPuow6iWysOAErHC6fIWy35+dIz1xLgJAH5TMxPARE1opE6rYe6Z34sEAz9FjVM utQBgn01OpSYkMVAd+hGH/le0iV7uS7WQojNOHzKS/X9PvOCtLrLsMVT0wjwc2YXF14MxRBX1 MehkVa7Uji6lh8+WNWHjkC/S9tD8fLndS2XqiBA8VBoqtrzLRsreCOxyGYyhC4a8XKg5gLJpF nOgHDKMcjHRQRGec2xKuINmBvdf51Zzput/EIwmH5r028MiLV4+YpfwQpXWNleLnI0OH5Cn9I AJCqSv37SoH8McFBd3CWEUQsG9bSnIMSGfb7dyvQPkJw4eq5eNBGPU6ebHiRQzHSKmsDrNdyi FUhpWGjWsrSJYa7ifrrbG/kPKjqWZR8EHL+0IOaBCboLYUDZwrnHhww+8K128jRiOmDt2n9z1 CGkU8nQwaiq5j7viGhlAh5SyNkxIU7JuenIF0Twb2VTi1rAa5Mksaen/5VWU3q4ToUrClCLyV q3g5fgqTDs/Os7qXQ/INgHJOUMO1t+4jJc0K9zl9Omb3uGHJuP+v5yGy40nOgmT9uTcjMnPS3 kx4GfnNTy0Ju8ORMoxBEabicyIP+6wyIKE0JChCxumx0+za9OBsHYR/QexG5q/XYnLH1cr74d CFsPCHt/AuHs9eImIst88kythA+zXK/LsylPtsaVeydoJnoMNwMrnSmEJ1IFhaymb5Guf+I0e eRm2ZQQtNmo5AqHAVOFHBary6nDLTFcFI42kFjVvbhsDN29R+TF2M5Hdc0E4pGjcn6k2Afic6 HVFXVky79TKO2n/NoXp01nrvOOatoh04lEuHr6/SGKgLt+IcdCCCKFDig== Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This declares the clock controller and the necessary 48 Mhz reference clock in the WPCM450 device. Switching devices over to the clock controller is intentionally done in a separate patch to give time for the clock controller driver to land. Signed-off-by: Jonathan Neuschäfer --- v4: - no changes v3: - Change clock-output-names and clock-names from "refclk" to "ref" v2: - https://lore.kernel.org/lkml/20220429172030.398011-6-j.neuschaefer@gmx.net/ - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index b9b669cd632f1..332cc222c7dc5 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -37,6 +37,14 @@ clk24m: clock-24mhz { #clock-cells = <0>; }; + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -49,6 +57,15 @@ gcr: syscon@b0000000 { reg = <0xb0000000 0x200>; }; + clk: clock-controller@b0000200 { + compatible = "nuvoton,wpcm450-clk"; + reg = <0xb0000200 0x100>; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; From patchwork Fri Jun 10 07:21:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 581116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45444CCA487 for ; Fri, 10 Jun 2022 07:22:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244158AbiFJHWr (ORCPT ); Fri, 10 Jun 2022 03:22:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343810AbiFJHWm (ORCPT ); Fri, 10 Jun 2022 03:22:42 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 390F55B8B2; Fri, 10 Jun 2022 00:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1654845736; bh=0zqHMNeMQrtU1b+MfBRSDC8nTugSCgehnUO7Pj1llsw=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=MK6H7uLloj+rKzjGVhOKGWgDsiZxQgKlxMB+IjX3+aNGCrmyOIpdAd02GZ2uOt+HQ ItEcnrSsKS58xQ5asP7IMtTsDAJeWeuZ4A3CEVaTt47ZOQPLrr+qpMlWlWvl7oNE2E 3dNQA6uXCJPy7DrGKGsaslJz5N8ZE39dZSI4W/YQ= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.195.3]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1M6DWi-1o69c81hUm-006cbI; Fri, 10 Jun 2022 09:22:16 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v4 5/6] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver Date: Fri, 10 Jun 2022 09:21:40 +0200 Message-Id: <20220610072141.347795-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:rHFZj7VQBz0QbZx53TLLbHc15qcq7lDeghyiY5FdApMao2tEJyg x1Hdw+Jzj86CjplY14Ql23+PKhvu+GwCUjvVZFDhbR2KncPmmIwKae+x9GKNyx68xRcXoYb bH8Thhjnzsh3bQ3PAiLMtUs4U3UnsG76kGYTiqEnMZ4fBJUDiXfaW7psgKrxKE36qoRniRy +4srbeXMk5TiMd3gIdaZw== X-UI-Out-Filterresults: notjunk:1;V03:K0:G16Cgx5x+y0=:Rp7y5THS2ZcJ1bkdnqB0yt Wi7bA84dC38hQXug4VX3J9cmN7tefSDqLJ6XQCkGQmVEgPEcheo8iHqnrKA0V5cR44MYmnyBH m4yi3aBpLX0bOAlLZS09LXFH4ICuGTc5f3ZnePXNwH9TT7sLbFlSp/jJiQg1yzLeOsnwlZrmA rXeEnHLut4iyy+rxq6dkKDDsr//EHOoPdM9azMkZ68xchHYXrSqBlLTKQ/vF35tRclEX2kUmb 9aRRO0CKI5Dy6eQ6FbAlvo/5evm4udb+v+kGVoc2Z8MEFy6Fz62HnP6ZLpz/HXvjGT4a5SOQF P07I63SfQJOQwVGd4aTO42hT/bgNOsyBkgv4k5FPRCZtW7+6BVtBPvzEyaknP6v2fGgRQcE9Q CV8j3YFfqOvpDmCD9s3qGUC1IYO1ucksuuoQZPDzabORKDmXjyEwwoP+qDx/vZ3BQnHN0UhW3 AgwDQpIK0RVjM9RdHRjAnWE2NMlvS+jYanmDEmQ9uDVrUN3fiRzNMuAfuvNYUkg6gxkobJRHj 0kGOGzNbMHA5YqdzCB1fbmYpWLnthalAaUnHG/0sD+8XTufWkTuk4wq+VMWkJTPRp93bygUcw Q+IVzy2Mpy55QTIby4EnYQKfAAAmEYEcP+NTx5f9Cn55RDicORuXRsjWeoNSPU2h4P4JL+OLm p3dSjKcHnwTYJPvv2cN+z94ZvgEmvSDo1lBuemEB0hcNO5pGLqeKLhQyZqLTtE8elblWTCNS7 66V4JkpDdZ/+yNHFFd9HJg1P6K0UUVwW2qB8LTa4lu7m7fevJwgX/PCKlhPQYb3AUr51GmsYp r5DoED8t9DvlFOB5yBj91PWxu/lVxQJqhWCL4SZQDrXACCPVQPn8hVi2Uz3CRjS5dypb9tW2J usAe65/LMGcscasG/G2GceLNeQ2GA9tIu+7HhhbD6O83vndBIQC+h8NlWTHhxfZvyl6z72G0p 87deMMxOzbMFTFenMoWRJ7iDTtouXiJmUaQ+RPUL3D4v5iIfPrCNpvimIkH5EeKL3yH+Q4O9y 4yZuUsxV5xe1l5shU5a5FGJCAiTedy9m48qMxIZpAak3mpPEAulZVHorwpp/8mpyoTJUDuBqI yRpIEznzPRYtIp671SxbqYBfPPQm9u5WMLFNdMIpTTsWrPuxFEwVtic9g== Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This driver implements the following features w.r.t. the clock and reset controller in the WPCM450 SoC: - It calculates the rates for all clocks managed by the clock controller - It leaves the clock tree mostly unchanged, except that it enables/ disables clock gates based on usage. - It exposes the reset lines managed by the controller using the Generic Reset Controller subsystem NOTE: If the driver and the corresponding devicetree node are present, the driver will disable "unused" clocks. This is problem until the clock relations are properly declared in the devicetree (in a later patch). Until then, the clk_ignore_unused kernel parameter can be used as a workaround. Signed-off-by: Jonathan Neuschäfer --- v4: - Fix reset controller initialization v3: - https://lore.kernel.org/lkml/20220508194333.2170161-7-j.neuschaefer@gmx.net/ - Change reference clock name from "refclk" to "ref" - Remove unused variable in return path of wpcm450_clk_register_pll - Remove unused divisor tables v2: - https://lore.kernel.org/lkml/20220429172030.398011-7-j.neuschaefer@gmx.net/ - no changes --- drivers/clk/Makefile | 1 + drivers/clk/clk-wpcm450.c | 364 ++++++++++++++++++++++++++++++++++++++ drivers/reset/Kconfig | 2 +- 3 files changed, 366 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/clk-wpcm450.c -- 2.35.1 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d5db170d38d2d..d6737e6d62feb 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -74,6 +74,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o +obj-$(CONFIG_ARCH_WPCM450) += clk-wpcm450.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name diff --git a/drivers/clk/clk-wpcm450.c b/drivers/clk/clk-wpcm450.c new file mode 100644 index 0000000000000..88fe5583e009d --- /dev/null +++ b/drivers/clk/clk-wpcm450.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton WPCM450 clock and reset controller driver. + * + * Copyright (C) 2022 Jonathan Neuschäfer + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct wpcm450_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_wpcm450_clk_pll(_hw) container_of(_hw, struct wpcm450_clk_pll, hw) + +#define PLLCON_FBDV GENMASK(24, 16) +#define PLLCON_PRST BIT(13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + unsigned long fbdv, indv, otdv; + u64 rate; + u32 pllcon; + + if (parent_rate == 0) { + pr_err("%s: parent rate is zero", __func__); + return 0; + } + + pllcon = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, pllcon) + 1; + fbdv = FIELD_GET(PLLCON_FBDV, pllcon) + 1; + otdv = FIELD_GET(PLLCON_OTDV, pllcon) + 1; + + rate = (u64)parent_rate * fbdv; + do_div(rate, indv * otdv); + + return rate; +} + +static int wpcm450_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + + return !(pllcon & PLLCON_PRST); +} + +static void wpcm450_clk_pll_disable(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + pllcon |= PLLCON_PRST | PLLCON_PWDEN; + writel(pllcon, pll->pllcon); +} + +static const struct clk_ops wpcm450_clk_pll_ops = { + .recalc_rate = wpcm450_clk_pll_recalc_rate, + .is_enabled = wpcm450_clk_pll_is_enabled, + .disable = wpcm450_clk_pll_disable +}; + +static struct clk_hw * +wpcm450_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags) +{ + struct wpcm450_clk_pll *pll; + struct clk_init_data init; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &wpcm450_clk_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + ret = clk_hw_register(NULL, &pll->hw); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + return &pll->hw; +} + +#define REG_CLKEN 0x00 +#define REG_CLKSEL 0x04 +#define REG_CLKDIV 0x08 +#define REG_PLLCON0 0x0c +#define REG_PLLCON1 0x10 +#define REG_PMCON 0x14 +#define REG_IRQWAKECON 0x18 +#define REG_IRQWAKEFLAG 0x1c +#define REG_IPSRST 0x20 + +struct wpcm450_pll_data { + const char *name; + const char *parent_name; + unsigned int reg; + unsigned long flags; +}; + +static const struct wpcm450_pll_data pll_data[] = { + { "pll0", "ref", REG_PLLCON0, 0 }, + { "pll1", "ref", REG_PLLCON1, 0 }, +}; + +struct wpcm450_clksel_data { + const char *name; + const char *const *parent_names; + unsigned int num_parents; + const u32 *table; + int shift; + int width; + int index; + unsigned long flags; +}; + +static const u32 parent_table[] = { 0, 1, 2 }; +static const char *const default_parents[] = { "pll0", "pll1", "ref" }; +static const char *const huart_parents[] = { "ref", "refdiv2" }; + +static const struct wpcm450_clksel_data clksel_data[] = { + { "cpusel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 0, 2, -1, CLK_IS_CRITICAL }, + { "clkout", default_parents, ARRAY_SIZE(default_parents), + parent_table, 2, 2, -1, 0 }, + { "usbphy", default_parents, ARRAY_SIZE(default_parents), + parent_table, 6, 2, -1, 0 }, + { "uartsel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 8, 2, WPCM450_CLK_USBPHY, 0 }, + { "huartsel", huart_parents, ARRAY_SIZE(huart_parents), + parent_table, 10, 1, -1, 0 }, +}; + +static const struct clk_div_table div_fixed2[] = { + { .val = 0, .div = 2 }, + { } +}; + +struct wpcm450_clkdiv_data { + const char *name; + const char *parent_name; + int div_flags; + const struct clk_div_table *table; + int shift; + int width; + unsigned long flags; +}; + +static struct wpcm450_clkdiv_data clkdiv_data_early[] = { + { "refdiv2", "ref", 0, div_fixed2, 0, 0 }, +}; + +static const struct wpcm450_clkdiv_data clkdiv_data[] = { + { "cpu", "cpusel", 0, div_fixed2, 0, 0, CLK_IS_CRITICAL }, + { "adcdiv", "ref", CLK_DIVIDER_POWER_OF_TWO, NULL, 28, 2, 0 }, + { "apb", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 26, 2, 0 }, + { "ahb", "cpu", CLK_DIVIDER_POWER_OF_TWO, NULL, 24, 2, 0 }, + { "uart", "uartsel", 0, NULL, 16, 4, 0 }, + { "ahb3", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 8, 2, 0 }, +}; + +struct wpcm450_clken_data { + const char *name; + const char *parent_name; + int bitnum; + unsigned long flags; +}; + +static const struct wpcm450_clken_data clken_data[] = { + { "fiu", "ahb3", WPCM450_CLK_FIU, 0 }, + { "xbus", "ahb3", WPCM450_CLK_XBUS, 0 }, + { "kcs", "apb", WPCM450_CLK_KCS, 0 }, + { "shm", "ahb3", WPCM450_CLK_SHM, 0 }, + { "usb1", "ahb", WPCM450_CLK_USB1, 0 }, + { "emc0", "ahb", WPCM450_CLK_EMC0, 0 }, + { "emc1", "ahb", WPCM450_CLK_EMC1, 0 }, + { "usb0", "ahb", WPCM450_CLK_USB0, 0 }, + { "peci", "apb", WPCM450_CLK_PECI, 0 }, + { "aes", "apb", WPCM450_CLK_AES, 0 }, + { "uart0", "uart", WPCM450_CLK_UART0, 0 }, + { "uart1", "uart", WPCM450_CLK_UART1, 0 }, + { "smb2", "apb", WPCM450_CLK_SMB2, 0 }, + { "smb3", "apb", WPCM450_CLK_SMB3, 0 }, + { "smb4", "apb", WPCM450_CLK_SMB4, 0 }, + { "smb5", "apb", WPCM450_CLK_SMB5, 0 }, + { "huart", "huartsel", WPCM450_CLK_HUART, 0 }, + { "pwm", "apb", WPCM450_CLK_PWM, 0 }, + { "timer0", "refdiv2", WPCM450_CLK_TIMER0, 0 }, + { "timer1", "refdiv2", WPCM450_CLK_TIMER1, 0 }, + { "timer2", "refdiv2", WPCM450_CLK_TIMER2, 0 }, + { "timer3", "refdiv2", WPCM450_CLK_TIMER3, 0 }, + { "timer4", "refdiv2", WPCM450_CLK_TIMER4, 0 }, + { "mft0", "apb", WPCM450_CLK_MFT0, 0 }, + { "mft1", "apb", WPCM450_CLK_MFT1, 0 }, + { "wdt", "refdiv2", WPCM450_CLK_WDT, 0 }, + { "adc", "adcdiv", WPCM450_CLK_ADC, 0 }, + { "sdio", "ahb", WPCM450_CLK_SDIO, 0 }, + { "sspi", "apb", WPCM450_CLK_SSPI, 0 }, + { "smb0", "apb", WPCM450_CLK_SMB0, 0 }, + { "smb1", "apb", WPCM450_CLK_SMB1, 0 }, +}; + +static DEFINE_SPINLOCK(wpcm450_clk_lock); + +static void __init wpcm450_clk_init(struct device_node *clk_np) +{ + struct clk_hw_onecell_data *clk_data; + static struct clk_hw **hws; + static struct clk_hw *hw; + void __iomem *clk_base; + int i, ret; + struct reset_simple_data *reset; + + clk_base = of_iomap(clk_np, 0); + if (!clk_base) { + pr_err("%pOFP: failed to map registers\n", clk_np); + of_node_put(clk_np); + return; + } + of_node_put(clk_np); + + clk_data = kzalloc(struct_size(clk_data, hws, WPCM450_NUM_CLKS), GFP_KERNEL); + if (!clk_data) + goto err_unmap; + + clk_data->num = WPCM450_NUM_CLKS; + hws = clk_data->hws; + + for (i = 0; i < WPCM450_NUM_CLKS; i++) + hws[i] = ERR_PTR(-ENOENT); + + // PLLs + for (i = 0; i < ARRAY_SIZE(pll_data); i++) { + const struct wpcm450_pll_data *data = &pll_data[i]; + + hw = wpcm450_clk_register_pll(clk_base + data->reg, data->name, + data->parent_name, data->flags); + if (IS_ERR(hw)) { + pr_info("Failed to register PLL: %pe", hw); + goto err_free; + } + } + + // Early divisors (REF/2) + for (i = 0; i < ARRAY_SIZE(clkdiv_data_early); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data_early[i]; + + hw = clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register div table: %pe\n", hw); + goto err_free; + } + } + + // Selects/muxes + for (i = 0; i < ARRAY_SIZE(clksel_data); i++) { + const struct wpcm450_clksel_data *data = &clksel_data[i]; + + hw = clk_hw_register_mux_table(NULL, data->name, data->parent_names, + data->num_parents, data->flags, + clk_base + REG_CLKSEL, data->shift, + BIT(data->width) - 1, 0, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register mux: %pe\n", hw); + goto err_free; + } + if (data->index >= 0) + clk_data->hws[data->index] = hw; + } + + // Divisors + for (i = 0; i < ARRAY_SIZE(clkdiv_data); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data[i]; + + hw = clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register divider: %pe\n", hw); + goto err_free; + } + } + + // Enables/gates + for (i = 0; i < ARRAY_SIZE(clken_data); i++) { + const struct wpcm450_clken_data *data = &clken_data[i]; + + hw = clk_hw_register_gate(NULL, data->name, data->parent_name, data->flags, + clk_base + REG_CLKEN, data->bitnum, + data->flags, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register gate: %pe\n", hw); + goto err_free; + } + clk_data->hws[data->bitnum] = hw; + } + + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, clk_data); + if (ret) + pr_err("Failed to add DT provider: %d\n", ret); + + // Reset controller + reset = kzalloc(sizeof(*reset), GFP_KERNEL); + if (!reset) + goto err_free; + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.nr_resets = WPCM450_NUM_RESETS; + reset->rcdev.ops = &reset_simple_ops; + reset->rcdev.of_node = clk_np; + reset->membase = clk_base + REG_IPSRST; + ret = reset_controller_register(&reset->rcdev); + if (ret) + pr_err("Failed to register reset controller: %d\n", ret); + + of_node_put(clk_np); + return; + +err_free: + kfree(clk_data->hws); +err_unmap: + iounmap(clk_base); + of_node_put(clk_np); +} + +CLK_OF_DECLARE(wpcm450_clk_init, "nuvoton,wpcm450-clk", wpcm450_clk_init); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 93c8d07ee3280..1e9badf8878bb 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -201,7 +201,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC + default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC || ARCH_NPCM help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, From patchwork Fri Jun 10 07:21:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 581244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAB8ECCA48C for ; Fri, 10 Jun 2022 07:22:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346738AbiFJHWs (ORCPT ); Fri, 10 Jun 2022 03:22:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346456AbiFJHWm (ORCPT ); Fri, 10 Jun 2022 03:22:42 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68C60CE0B; Fri, 10 Jun 2022 00:22:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1654845738; bh=6We94l3lbFtVURMV4QMSE5PpvIk0qqwAzLwUr6CCrCw=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=NL+S91NdZDtjFCi8UAx+8CdEsO/P3xL+aRxK8SCTk6/qo5Hc2DLa/4/1WIf8XgZnb n2H+q38MKZRAIw2OSxvUd6+3BMqKCU9CgbUXBZlT4hCoCmBkUtcVvPUF8cPB7YvlN6 Q4fFPNbuwbaAeekoxkPVbCMrHWNalXFQeab0TLf8= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.195.3]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MG9kC-1nyQNB3YWC-00GWNP; Fri, 10 Jun 2022 09:22:17 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski Subject: [PATCH v4 6/6] ARM: dts: wpcm450: Switch clocks to clock controller Date: Fri, 10 Jun 2022 09:21:41 +0200 Message-Id: <20220610072141.347795-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:a+f+h0WVs/fv4wcts19D+GINBFdJUog3YzlAfih/ywvkXDMuV6O J03O9XTJW0v348QMAv+oxGA4CgZP2NVhaLr58/c+oaGf2aY079XyF7dycZEj5F9uEY8WuSS WGvzILZLGTMf6ea4C2OtAqe0n4vdZuhABnmzln0Ice39p7lrFGIt/lYUmjQQJk5bFHoWD0z MrO7bfY2wWt+gbIbCNoaw== X-UI-Out-Filterresults: notjunk:1;V03:K0:0XrQDZfgnAw=:fii0JarWt4mr8rSUZPxTiR 03W/bonVOGBCZFyYYvjkQ32o4n6VHB9a30AonqPpRe9QftC/YyoM8f3+W4aIgN5UG2qOeFRJ1 yqLGnK8HDFW3S4QlBBBbynOAau/eh9MVnd7cwTkXryd/jSTtqX34Lnt7BtV/ZkxKinJtYD+Cn PVljnCCEbR2Ar+6Oh9ah62IRHcDC/yJ1HS8+geCHuUeWk15UXgpz+aQlXqMtHJZsGAGuxGiNc FVIFTd7rlYcpVF6d9UwJoDEvIuPPmCjbYdlolwoM+7fpO2WKoxvA65GH6OBfeEc0j7Fk8YOFZ 9BCC5r74Ioofwb3OWiDsqA2Mk81/njHm1t9ddSNGlI/t/3nyXC0Gg3zhF7v8264x1kVYuowbU kaySeHk9OBme5uznoP+VdaZLE1U6Gzb+jC3VMoN+JPPkAsqfmM7ssLYrX6G762xMVz/sRwKfz mc8WRFSYi03owDqUdHd/LLcBzIg6Bk+N6xRM+0/HSprq4DenVgCaEHtFt0ujafAtZW0SQ8FPR nNY42B8wTSKYx9ox2dxQt6v2J7yyvHdo7yR4kvO2P3vkU7mqEtIvKegI/hZws3bWA+TLQiOcX yk5MnrvRPoixjbSRT1Pc02lLddhMSJ8jLTZarPMiZlhGEOfzhuPz+vKdCLKJk46+6fhula5Kn 8cWq3nNNLIIb+ijp3HdHkl8tcF3wnwuSVBWY8VYWDnfUM8dTx2E6Yz+VkHQRhKa/glUocq7O6 kBiyT6H040wPWyY9xyzvAh2+4dM4EJSnL4SXnU+vubEq4vIEk/Y5NIoEVtedaQo1ZzFcU3Kq3 ODYFPz7CLbk2ks5h9mmUeDn9l/sdNWS6QDEHgwXyGM5mdT3AWLoE7M6CElA3TqHseahKN7L1E ib63guKn6o42VIGa2gJlPbkMVtTqOsyz5TOXcIEqlFxfs0dcznPzOAe27ClFr8EZ6Bgc6KlfO UioZpvAFA0FObzAKDPVAQG4qkhz3T+b6RHq7CtBCOnC58eOexgEM3vpvdHBZjozhRr/cvsL0t BchZ/5UPaj46VNC+MNQVqqsCmUkHh2H9sxZ1N9Mk6KkHGuiEjDoqbA4etqZpa4YuSkXuIwV+j 0jxkV60KpSw0iVgSx5kgKLIzotYwnodTYFGYTNYpsg0TubSsKeTVu3hNw== Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer --- v2-v4: - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 332cc222c7dc5..439f9047ad651 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neuschäfer #include +#include / { compatible = "nuvoton,wpcm450"; @@ -30,13 +31,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; @@ -71,7 +65,7 @@ serial0: serial@b8000000 { reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART0>; pinctrl-names = "default"; pinctrl-0 = <&bsp_pins>; status = "disabled"; @@ -82,7 +76,7 @@ serial1: serial@b8000100 { reg = <0xb8000100 0x20>; reg-shift = <2>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART1>; status = "disabled"; }; @@ -90,14 +84,18 @@ timer0: timer@b8001000 { compatible = "nuvoton,wpcm450-timer"; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_TIMER0>, + <&clk WPCM450_CLK_TIMER1>, + <&clk WPCM450_CLK_TIMER2>, + <&clk WPCM450_CLK_TIMER3>, + <&clk WPCM450_CLK_TIMER4>; }; watchdog0: watchdog@b800101c { compatible = "nuvoton,wpcm450-wdt"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 {