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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id n4-20020a05600c4f8400b003971fc23185sm20679416wmq.20.2022.06.20.13.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:17 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 02/49] regmap-irq: Fix offset/index mismatch in read_sub_irq_data() Date: Mon, 20 Jun 2022 21:05:57 +0100 Message-Id: <20220620200644.1961936-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We need to divide the sub-irq status register offset by register stride to get an index for the status buffer to avoid an out of bounds write when the register stride is greater than 1. Fixes: a2d21848d921 ("regmap: regmap-irq: Add main status register support") Signed-off-by: Aidan MacDonald Reviewed-by: Matti Vaittinen Reviewed-by: Guru Das Srinagesh --- drivers/base/regmap/regmap-irq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 4f785bc7981c..a6db605707b0 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -387,6 +387,7 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, subreg = &chip->sub_reg_offsets[b]; for (i = 0; i < subreg->num_regs; i++) { unsigned int offset = subreg->offset[i]; + unsigned int index = offset / map->reg_stride; if (chip->not_fixed_stride) ret = regmap_read(map, @@ -395,7 +396,7 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, else ret = regmap_read(map, chip->status_base + offset, - &data->status_buf[offset]); + &data->status_buf[index]); if (ret) break; From patchwork Mon Jun 20 20:05:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FD5BCCA481 for ; Mon, 20 Jun 2022 20:06:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245663AbiFTUGb (ORCPT ); Mon, 20 Jun 2022 16:06:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245336AbiFTUG3 (ORCPT ); Mon, 20 Jun 2022 16:06:29 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC4751AF11; Mon, 20 Jun 2022 13:06:22 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id z17so6379642wmi.1; Mon, 20 Jun 2022 13:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n7C5fvVEgBv5GCdLdnesehqd1UexDtPscEtDq8TpQ98=; b=iqvQ3lEYGu10uGW18Rm99ayT8x3XLn8XsO9ymyUHVGvqkrAaQyuQPHeJloUfiJLsCF brvGIxTPxFY1qneHHNIXCVo9xBJ6RdKlEW0a+M06XrPY9smcUzKXBODzoRGSYX2fBOi0 ois+9p71zNywpoyFgK1TIsJrPw8oRs+q2dNOU0miygmL4JPhI83OXUTFGpe0qYtNO5ma dzfiFEZpepT2Nxpnrff763DGS7DNF3ILweh1b8BAmm8zFxc2WGUKCoGEy5vMCKQkMK8d xKAxIIl3WT/W48wenSiIcIm+nDxzv7O78vP0Jryl5YepV6he0PFC0T0HzFB52vF6jmKy 3vzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n7C5fvVEgBv5GCdLdnesehqd1UexDtPscEtDq8TpQ98=; b=hqTC+A8TMPNVvhtHEWDZLAh5CqI/bO7ipg3P2RWcZ7W3Jxyhya4kGOK9mDucOHnFJz /OJ48Ca9EloWPsfMwF9GR7SIT4o1wMWSZTv/vrl2jauPiUncH6vrRyS1hvs7xiYJJ/iQ bmSDT9BFKV/j4drpAym9zYUKGUJsI1kXUEGuGrtCgf6+hmj2wa6JRLeZaZE9yplaJHgx LMb077YwRsrLfEJ4DN1SEgbLK9okIOTxEoRu0VX/ZMxOk7vOCYq0KWlhWxBs3GFMvgCk +0HA0QIbSzOlmFHedPFuq3eyHM7rp1+5DmreK8iRoksLk0BqrTbBZ0lipp34eMVC+c0N x+SA== X-Gm-Message-State: AOAM531cjriSjSs0ze8voBqeHoRF+QQ3GU2IwoOp9c1E23CuMoPupRcD 2JuWXUmxu+UzSb5rlyCRGOw= X-Google-Smtp-Source: ABdhPJx6f36rmenVzwLf28ElgO1YJCiHAg7RsENbp/+lJ/G4kOpdScdIio38B+uaAC+s+EJF6BDpIQ== X-Received: by 2002:a05:600c:4f14:b0:39c:8612:a95e with SMTP id l20-20020a05600c4f1400b0039c8612a95emr37337282wmq.107.1655755581260; Mon, 20 Jun 2022 13:06:21 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id d8-20020adfc088000000b00213ba0cab3asm14319173wrf.44.2022.06.20.13.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:20 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 04/49] regmap-irq: Introduce config registers for irq types Date: Mon, 20 Jun 2022 21:05:59 +0100 Message-Id: <20220620200644.1961936-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Config registers provide a more uniform approach to handling irq type registers. They are essentially an extension of the virtual registers used by the qcom-pm8008 driver. Config registers can be represented as a 2D array: config_base[0] reg0,0 reg0,1 reg0,2 reg0,3 config_base[1] reg1,0 reg1,1 reg1,2 reg1,3 config_base[2] reg2,0 reg2,1 reg2,2 reg2,3 There are 'num_config_bases' base registers, each of which is used to address 'num_config_regs' registers. The addresses are calculated in the same way as for other bases. It is assumed that an irq's type is controlled by one column of registers; that column is identified by the irq's 'type_reg_offset'. The set_type_config() callback is responsible for updating the config register contents. It receives an array of buffers (each represents a row of registers) and the index of the column to update, along with the 'struct regmap_irq' description and requested irq type. Buffered values are written to registers in regmap_irq_sync_unlock(). Note that the entire register contents are overwritten, which is a minor change in behavior from type registers via 'type_base'. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 102 ++++++++++++++++++++++++++++++- include/linux/regmap.h | 12 ++++ 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 59cfd4000e63..be35f2e41b8c 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -39,6 +39,7 @@ struct regmap_irq_chip_data { unsigned int *type_buf; unsigned int *type_buf_def; unsigned int **virt_buf; + unsigned int **config_buf; unsigned int irq_reg_stride; unsigned int type_reg_stride; @@ -231,6 +232,17 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } } + for (i = 0; i < d->chip->num_config_bases; i++) { + for (j = 0; j < d->chip->num_config_regs; j++) { + reg = sub_irq_reg(d, d->chip->config_base[i], j); + ret = regmap_write(map, reg, d->config_buf[i][j]); + if (ret != 0) + dev_err(d->map->dev, + "Failed to write config %x: %d\n", + reg, ret); + } + } + if (d->chip->runtime_pm) pm_runtime_put(map->dev); @@ -298,6 +310,10 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type) reg = t->type_reg_offset / map->reg_stride; + if (d->chip->set_type_config) + return d->chip->set_type_config(d->config_buf, type, + irq_data, reg); + if (t->type_reg_mask) d->type_buf[reg] &= ~t->type_reg_mask; else @@ -603,6 +619,62 @@ static const struct irq_domain_ops regmap_domain_ops = { .xlate = irq_domain_xlate_onetwocell, }; +/** + * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. + * + * @buf: Buffer containing configuration register values, this is a 2D array of + * `num_config_bases` rows, each of `num_config_regs` elements. + * @type: The requested IRQ type. + * @irq_data: The IRQ being configured. + * @idx: Index of the irq's config registers within each array `buf[i]` + * + * This is a &struct regmap_irq_chip->set_type_config callback suitable for + * chips with one config register. Register values are updated according to + * the &struct regmap_irq_type data associated with an IRQ. + */ +int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx) +{ + const struct regmap_irq_type *t = &irq_data->type; + + if (t->type_reg_mask) + buf[0][idx] &= ~t->type_reg_mask; + else + buf[0][idx] &= ~(t->type_falling_val | + t->type_rising_val | + t->type_level_low_val | + t->type_level_high_val); + + switch (type) { + case IRQ_TYPE_EDGE_FALLING: + buf[0][idx] |= t->type_falling_val; + break; + + case IRQ_TYPE_EDGE_RISING: + buf[0][idx] |= t->type_rising_val; + break; + + case IRQ_TYPE_EDGE_BOTH: + buf[0][idx] |= (t->type_falling_val | + t->type_rising_val); + break; + + case IRQ_TYPE_LEVEL_HIGH: + buf[0][idx] |= t->type_level_high_val; + break; + + case IRQ_TYPE_LEVEL_LOW: + buf[0][idx] |= t->type_level_low_val; + break; + + default: + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(regmap_irq_set_type_config_simple); + /** * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling * @@ -728,6 +800,24 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } } + if (chip->num_config_bases && chip->num_config_regs) { + /* + * Create config_buf[num_config_bases][num_config_regs] + */ + d->config_buf = kcalloc(chip->num_config_bases, + sizeof(*d->config_buf), GFP_KERNEL); + if (!d->config_buf) + goto err_alloc; + + for (i = 0; i < chip->num_config_regs; i++) { + d->config_buf[i] = kcalloc(chip->num_config_regs, + sizeof(unsigned int), + GFP_KERNEL); + if (!d->config_buf[i]) + goto err_alloc; + } + } + d->irq_chip = regmap_irq_chip; d->irq_chip.name = chip->name; d->irq = irq; @@ -904,6 +994,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, kfree(d->virt_buf[i]); kfree(d->virt_buf); } + if (d->config_buf) { + for (i = 0; i < chip->num_config_bases; i++) + kfree(d->config_buf[i]); + kfree(d->config_buf); + } kfree(d); return ret; } @@ -944,7 +1039,7 @@ EXPORT_SYMBOL_GPL(regmap_add_irq_chip); void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) { unsigned int virq; - int hwirq; + int i, hwirq; if (!d) return; @@ -974,6 +1069,11 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) kfree(d->mask_buf); kfree(d->status_reg_buf); kfree(d->status_buf); + if (d->config_buf) { + for (i = 0; i < d->chip->num_config_bases; i++) + kfree(d->config_buf[i]); + kfree(d->config_buf); + } kfree(d); } EXPORT_SYMBOL_GPL(regmap_del_irq_chip); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 8952fa3d0d59..e48d65756fb4 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1460,6 +1460,7 @@ struct regmap_irq_sub_irq_map { * @wake_base: Base address for wake enables. If zero unsupported. * @type_base: Base address for irq type. If zero unsupported. * @virt_reg_base: Base addresses for extra config regs. + * @config_base: Base address for IRQ type config regs. If null unsupported. * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. * @mask_invert: Inverted mask register: cleared bits are masked out. @@ -1489,12 +1490,15 @@ struct regmap_irq_sub_irq_map { * If zero unsupported. * @type_reg_stride: Stride to use for chips where type registers are not * contiguous. + * @num_config_bases: Number of config base registers. + * @num_config_regs: Number of config registers for each config base register. * @handle_pre_irq: Driver specific callback to handle interrupt from device * before regmap_irq_handler process the interrupts. * @handle_post_irq: Driver specific callback to handle interrupt from device * after handling the interrupts in regmap_irq_handler(). * @set_type_virt: Driver specific callback to extend regmap_irq_set_type() * and configure virt regs. + * @set_type_config: Callback used for configuring irq types. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. * @@ -1517,6 +1521,7 @@ struct regmap_irq_chip { unsigned int wake_base; unsigned int type_base; unsigned int *virt_reg_base; + const unsigned int *config_base; unsigned int irq_reg_stride; bool mask_writeonly:1; bool init_ack_masked:1; @@ -1539,17 +1544,24 @@ struct regmap_irq_chip { int num_type_reg; int num_virt_regs; + int num_config_bases; + int num_config_regs; unsigned int type_reg_stride; int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); int (*set_type_virt)(unsigned int **buf, unsigned int type, unsigned long hwirq, int reg); + int (*set_type_config)(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx); void *irq_drv_data; }; struct regmap_irq_chip_data; +int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx); + int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, int irq_base, const struct regmap_irq_chip *chip, struct regmap_irq_chip_data **data); From patchwork Mon Jun 20 20:06:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45C99CCA480 for ; Mon, 20 Jun 2022 20:06:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343589AbiFTUGf (ORCPT ); Mon, 20 Jun 2022 16:06:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245078AbiFTUG3 (ORCPT ); Mon, 20 Jun 2022 16:06:29 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3C781CFE9; Mon, 20 Jun 2022 13:06:24 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id g4so16059750wrh.11; Mon, 20 Jun 2022 13:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+RKr+XEaRdRjV4wQDDo6dA3o5NhQRFg9bdRqt89GYJ0=; b=MFe3Q+6q+h4xcL+TmQJO+X66B7qIj60KwU1bFNqVSVGdb6rLV0HBSOV2kqB2IjbUOu EeUFb2zxP73mwWK5HebDmiVlcTN8/lZAhuLs1PYprMOgS3IJsFXo991qtdEe757TgDt9 PNPQFGJRS+9ee64SFv8BTOpI+yUy8iMY6XDOthlwL791AZzHrgjOrzL2Z+WNMe4Q5oWF qoB1e1HBzkv5OpvL4CfZkeKUFNVwqSHVXe+sPPHD6FW/G5Yf9GVjSClhAKk8/5129GdY Md+190DcO8iXrY/zsP1mYBAaO/sM8k8KeCFB2bYWTrEW6jR8+hXYDV/1ognbiuUqqzMD dr9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+RKr+XEaRdRjV4wQDDo6dA3o5NhQRFg9bdRqt89GYJ0=; b=2Mu1u3QsFS+VHDyubNuraQmf+2ck1Xd8ppLpLdJGoCmfzhvlNbfGCIVTA/iru/LNUv Ix8r366Qk7c/KYfc52aGfpbmhqfPglthJ8JdwZi+QC/33qhCKgFXKHLVHv8gMWsohvuy aL+Q1GBq5GBPfivYRYopKMVNV8DUL5xc94boTrYMpcShmTQaEOamK+aNCHyJSkud9xQW r4jGZiv77O0S7cV2lS34adORHFuI6pqH5wGS/T9naz6Zl+Hti31k1nyfgm3BRWXDTOVP vfdk5YFM7fZCpaamqSr87p6YLhvrEAe+ZBeookf/aBS/fIurUv6cikf/UzAk6Mc5DB4y UXQA== X-Gm-Message-State: AJIora9CgNVj41q40z4cfH+F1huZBsqmertO2mPAogjGR6xsT+Z3cgJi yj2EJNlY8jdEwaMDA3m4PlY= X-Google-Smtp-Source: AGRyM1s4brtjxXAe+5dbgtT8AX6IW9qXMEOUfwY6ndJ5c4LaV2MOHLy/q9oiZpUl7AFgXk1xm6zPXA== X-Received: by 2002:a5d:6d8f:0:b0:218:45ef:30c2 with SMTP id l15-20020a5d6d8f000000b0021845ef30c2mr23978566wrs.411.1655755582833; Mon, 20 Jun 2022 13:06:22 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id x13-20020adfdd8d000000b0021b81855c1csm12567311wrl.27.2022.06.20.13.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:22 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 05/49] mfd: qcom-pm8008: Convert irq chip to config regs Date: Mon, 20 Jun 2022 21:06:00 +0100 Message-Id: <20220620200644.1961936-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use config registers to simplify the driver, putting all of the code for irq type configuration in one place instead of splitting it up arbitrarily between type and virtual registers. Remove the initial register setting in pm8008_init(). The comment indicates this is a hack to work around quirks in regmap-irq, but this is not necessary if using config registers. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 76 +++++++++++---------------------------- 1 file changed, 21 insertions(+), 55 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index c472d7f8103c..da16566f7883 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -73,15 +73,16 @@ static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs), }; -static unsigned int pm8008_virt_regs[] = { +static unsigned int pm8008_config_regs[] = { + PM8008_TYPE_BASE, PM8008_POLARITY_HI_BASE, PM8008_POLARITY_LO_BASE, }; enum { + SET_TYPE_INDEX, POLARITY_HI_INDEX, POLARITY_LO_INDEX, - PM8008_NUM_VIRT_REGS, }; static struct regmap_irq pm8008_irqs[] = { @@ -95,32 +96,36 @@ static struct regmap_irq pm8008_irqs[] = { REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)), }; -static int pm8008_set_type_virt(unsigned int **virt_buf, - unsigned int type, unsigned long hwirq, - int reg) +static int pm8008_set_type_config(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx) { switch (type) { case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: - virt_buf[POLARITY_HI_INDEX][reg] &= ~pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] &= ~irq_data->mask; + buf[POLARITY_LO_INDEX][idx] |= irq_data->mask; break; case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: - virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] &= ~pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] |= irq_data->mask; + buf[POLARITY_LO_INDEX][idx] &= ~irq_data->mask; break; case IRQ_TYPE_EDGE_BOTH: - virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] |= irq_data->mask; + buf[POLARITY_LO_INDEX][idx] |= irq_data->mask; break; default: return -EINVAL; } + if (type & IRQ_TYPE_EDGE_BOTH) + buf[SET_TYPE_INDEX][idx] |= irq_data->mask; + else + buf[SET_TYPE_INDEX][idx] &= ~irq_data->mask; + return 0; } @@ -128,20 +133,19 @@ static struct regmap_irq_chip pm8008_irq_chip = { .name = "pm8008_irq", .main_status = I2C_INTR_STATUS_BASE, .num_main_regs = 1, - .num_virt_regs = PM8008_NUM_VIRT_REGS, .irqs = pm8008_irqs, .num_irqs = ARRAY_SIZE(pm8008_irqs), .num_regs = PM8008_NUM_PERIPHS, .not_fixed_stride = true, .sub_reg_offsets = pm8008_sub_reg_offsets, - .set_type_virt = pm8008_set_type_virt, .status_base = PM8008_STATUS_BASE, .mask_base = PM8008_MASK_BASE, .unmask_base = PM8008_UNMASK_BASE, - .type_base = PM8008_TYPE_BASE, .ack_base = PM8008_ACK_BASE, - .virt_reg_base = pm8008_virt_regs, - .num_type_reg = PM8008_NUM_PERIPHS, + .config_base = pm8008_config_regs, + .num_config_bases = ARRAY_SIZE(pm8008_config_regs), + .num_config_regs = PM8008_NUM_PERIPHS, + .set_type_config = pm8008_set_type_config, }; static struct regmap_config qcom_mfd_regmap_cfg = { @@ -150,34 +154,6 @@ static struct regmap_config qcom_mfd_regmap_cfg = { .max_register = 0xFFFF, }; -static int pm8008_init(struct pm8008_data *chip) -{ - int rc; - - /* - * Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework - * reads this as the default value instead of zero, the HW default. - * This is required to enable the writing of TYPE registers in - * regmap_irq_sync_unlock(). - */ - rc = regmap_write(chip->regmap, - (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), - BIT(0)); - if (rc) - return rc; - - /* Do the same for GPIO1 and GPIO2 peripherals */ - rc = regmap_write(chip->regmap, - (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); - if (rc) - return rc; - - rc = regmap_write(chip->regmap, - (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); - - return rc; -} - static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, int client_irq) { @@ -185,20 +161,10 @@ static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, struct regmap_irq_type *type; struct regmap_irq_chip_data *irq_data; - rc = pm8008_init(chip); - if (rc) { - dev_err(chip->dev, "Init failed: %d\n", rc); - return rc; - } - for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) { type = &pm8008_irqs[i].type; - type->type_reg_offset = pm8008_irqs[i].reg_offset; - type->type_rising_val = pm8008_irqs[i].mask; - type->type_falling_val = pm8008_irqs[i].mask; - type->type_level_high_val = 0; - type->type_level_low_val = 0; + type->type_reg_offset = pm8008_irqs[i].reg_offset; if (type->type_reg_offset == PM8008_MISC) type->types_supported = IRQ_TYPE_EDGE_RISING; From patchwork Mon Jun 20 20:06:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68608C43334 for ; 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id n23-20020a05600c3b9700b0039c5224bfcbsm20984858wms.46.2022.06.20.13.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:26 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 08/49] sound: soc: codecs: wcd938x: Remove spurious type_base from irq chip Date: Mon, 20 Jun 2022 21:06:03 +0100 Message-Id: <20220620200644.1961936-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This chip does not set num_type_regs or define any supported IRQ types, so regmap-irq can't configure its IRQ types. Including type_base in the chip definition is therefore redundant. Signed-off-by: Aidan MacDonald --- sound/soc/codecs/wcd938x.c | 1 - 1 file changed, 1 deletion(-) diff --git a/sound/soc/codecs/wcd938x.c b/sound/soc/codecs/wcd938x.c index c1b61b997f69..acba253b791e 100644 --- a/sound/soc/codecs/wcd938x.c +++ b/sound/soc/codecs/wcd938x.c @@ -1298,7 +1298,6 @@ static struct regmap_irq_chip wcd938x_regmap_irq_chip = { .num_regs = 3, .status_base = WCD938X_DIGITAL_INTR_STATUS_0, .mask_base = WCD938X_DIGITAL_INTR_MASK_0, - .type_base = WCD938X_DIGITAL_INTR_LEVEL_0, .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, .use_ack = 1, .runtime_pm = true, From patchwork Mon Jun 20 20:06:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1539C43334 for ; Mon, 20 Jun 2022 20:06:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343792AbiFTUG6 (ORCPT ); Mon, 20 Jun 2022 16:06:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343578AbiFTUGf (ORCPT ); Mon, 20 Jun 2022 16:06:35 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A69C1EAF8; Mon, 20 Jun 2022 13:06:32 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id c130-20020a1c3588000000b0039c6fd897b4so8271179wma.4; Mon, 20 Jun 2022 13:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NSMrw3v+dSzormMBlFnVqYO9Ybr8y9x05CczXbq+F0o=; b=Z5NU7srurHjdW0PF4O55elxfUZBgUDk5YPFMpg1RdqsrfEMk7qqDL8ep246OtTDiC4 6ju1VuX4sBfj/74uye9hCH9gCwZwRwcHtZnxI5fARi8+LKkAfdtx6MsYh7Pd2V1TJjz4 mBfORf4k+PothfafLBhj4toSDqA8T3fphY7zdnpKPOEXFqu9HOx5TIDgCjq0SHrD5+CC INWDLlQYTChLHohDgNjGViE1FGyoeWG6e0guIJwG/DdPTqvgerAxAxO0lis9868OmZEE CKl/wzAj2Z91E8tmS3NFKhGL/f5b2L127K+Vv0HRjyl36ABwGlxo+z8eyN1C5YXCAV/1 VXTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NSMrw3v+dSzormMBlFnVqYO9Ybr8y9x05CczXbq+F0o=; b=JGnCOgr+9Dk9QepWwHUxOPRbJspBfCevP8F8PAlsKD3C9dAOJOkrKbT8Jf6IGDRDtD wWk9VQdumKCNv8TfLhH4600mMw1gEd8OSf0iw1LvyuMNc9G1tmq2IfmFtuVjcjkf96ts aAMAUst1r7Qa8PYTipfvj6i4rbabpJDiOfLXGRkEad4lj8twM4GOhXX9mR2/a+oeWsy4 AP5CGs2FMvCRXV0+Axx4wcPVOXR27c8zhdlQu6s7v1kTfnsZ+SNk5pZmStLMBUWfFHTN qCtOek4J1fidirxgVWiG/hb63Ly8kBWxfEOzWsWRNJUcqGwl/hnlGTT0U7NsY0SNeL2M mipQ== X-Gm-Message-State: AJIora9CCSaQIrJ3s7TcD+kPbwC86xER6FHBNev2xgHPR8ABbfUhxomW v0gZj04yQl07bDo+0/4s4QA= X-Google-Smtp-Source: AGRyM1v4nGqgjAhTskzkWcEAA3t4wJpSGRdFd7rK8rtyVQboY6GtKy9ysgj/zJBTNIGbPGeagfeUtA== X-Received: by 2002:a05:600c:3d18:b0:39c:474c:eb with SMTP id bh24-20020a05600c3d1800b0039c474c00ebmr26181880wmb.87.1655755590681; Mon, 20 Jun 2022 13:06:30 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id u25-20020adfa199000000b002184a3a3641sm14724036wru.100.2022.06.20.13.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:30 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 10/49] regmap-irq: Remove virtual registers support Date: Mon, 20 Jun 2022 21:06:05 +0100 Message-Id: <20220620200644.1961936-11-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Virtual registers can be removed, since config registers implement the same functionality. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 42 -------------------------------- include/linux/regmap.h | 9 ------- 2 files changed, 51 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index be35f2e41b8c..5a3e255816fd 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -38,7 +38,6 @@ struct regmap_irq_chip_data { unsigned int *wake_buf; unsigned int *type_buf; unsigned int *type_buf_def; - unsigned int **virt_buf; unsigned int **config_buf; unsigned int irq_reg_stride; @@ -218,20 +217,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } } - if (d->chip->num_virt_regs) { - for (i = 0; i < d->chip->num_virt_regs; i++) { - for (j = 0; j < d->chip->num_regs; j++) { - reg = sub_irq_reg(d, d->chip->virt_reg_base[i], - j); - ret = regmap_write(map, reg, d->virt_buf[i][j]); - if (ret != 0) - dev_err(d->map->dev, - "Failed to write virt 0x%x: %d\n", - reg, ret); - } - } - } - for (i = 0; i < d->chip->num_config_bases; i++) { for (j = 0; j < d->chip->num_config_regs; j++) { reg = sub_irq_reg(d, d->chip->config_base[i], j); @@ -346,10 +331,6 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type) return -EINVAL; } - if (d->chip->set_type_virt) - return d->chip->set_type_virt(d->virt_buf, type, data->hwirq, - reg); - return 0; } @@ -782,24 +763,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, goto err_alloc; } - if (chip->num_virt_regs) { - /* - * Create virt_buf[chip->num_extra_config_regs][chip->num_regs] - */ - d->virt_buf = kcalloc(chip->num_virt_regs, sizeof(*d->virt_buf), - GFP_KERNEL); - if (!d->virt_buf) - goto err_alloc; - - for (i = 0; i < chip->num_virt_regs; i++) { - d->virt_buf[i] = kcalloc(chip->num_regs, - sizeof(unsigned int), - GFP_KERNEL); - if (!d->virt_buf[i]) - goto err_alloc; - } - } - if (chip->num_config_bases && chip->num_config_regs) { /* * Create config_buf[num_config_bases][num_config_regs] @@ -989,11 +952,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, kfree(d->mask_buf); kfree(d->status_buf); kfree(d->status_reg_buf); - if (d->virt_buf) { - for (i = 0; i < chip->num_virt_regs; i++) - kfree(d->virt_buf[i]); - kfree(d->virt_buf); - } if (d->config_buf) { for (i = 0; i < chip->num_config_bases; i++) kfree(d->config_buf[i]); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index e48d65756fb4..bb8c89a83b51 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1459,7 +1459,6 @@ struct regmap_irq_sub_irq_map { * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. * @type_base: Base address for irq type. If zero unsupported. - * @virt_reg_base: Base addresses for extra config regs. * @config_base: Base address for IRQ type config regs. If null unsupported. * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. @@ -1486,8 +1485,6 @@ struct regmap_irq_sub_irq_map { * assigned based on the index in the array of the interrupt. * @num_irqs: Number of descriptors. * @num_type_reg: Number of type registers. - * @num_virt_regs: Number of non-standard irq configuration registers. - * If zero unsupported. * @type_reg_stride: Stride to use for chips where type registers are not * contiguous. * @num_config_bases: Number of config base registers. @@ -1496,8 +1493,6 @@ struct regmap_irq_sub_irq_map { * before regmap_irq_handler process the interrupts. * @handle_post_irq: Driver specific callback to handle interrupt from device * after handling the interrupts in regmap_irq_handler(). - * @set_type_virt: Driver specific callback to extend regmap_irq_set_type() - * and configure virt regs. * @set_type_config: Callback used for configuring irq types. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. @@ -1520,7 +1515,6 @@ struct regmap_irq_chip { unsigned int ack_base; unsigned int wake_base; unsigned int type_base; - unsigned int *virt_reg_base; const unsigned int *config_base; unsigned int irq_reg_stride; bool mask_writeonly:1; @@ -1543,15 +1537,12 @@ struct regmap_irq_chip { int num_irqs; int num_type_reg; - int num_virt_regs; int num_config_bases; int num_config_regs; unsigned int type_reg_stride; int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); - int (*set_type_virt)(unsigned int **buf, unsigned int type, - unsigned long hwirq, int reg); int (*set_type_config)(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); void *irq_drv_data; From patchwork Mon Jun 20 20:06:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B4DFCCA483 for ; Mon, 20 Jun 2022 20:07:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245078AbiFTUHB (ORCPT ); Mon, 20 Jun 2022 16:07:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343676AbiFTUGm (ORCPT ); Mon, 20 Jun 2022 16:06:42 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A8841CB34; Mon, 20 Jun 2022 13:06:35 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id e25so12215512wrc.13; Mon, 20 Jun 2022 13:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ygggAhOijcuCf3qt1rizt96GNeoo90FsvWvR8LV1nyI=; b=T/UvuXuobHYQjUmOyYbANq63UlOF39LoQ9F0gifyzekhcyCOQUypCEyXG/OKpb2La8 Q6xZerE2gogPQTVjnWE4wmzodDreHkzH5Hob1Yofhw+6nVU3v+x19k/F+1fzWd07Nhyx t3dlqulqzXj03B/a7eof6RPLvdFSbbKgQ0qPPyyfUc0DvtgH5rSWtXFv/QKk3GFNsmgf ba5ere/Jpb7EyG3rOfQF0QhkkW/aBY4cYS4Nq+Vs12xBWeLC+F11zEPyoGk+7XAQtopt 0onYAtqYMepxk8EG5VyJd6DPsfXoBs96h/qfy/t4bsS9pyheZRo3qyXWG31pXvk7VX4q +KwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ygggAhOijcuCf3qt1rizt96GNeoo90FsvWvR8LV1nyI=; b=w2T+aWxjx6v3xximQzIXNjApU8RxRVb8aLcnU0lCxR2hSrYBoDuoJn1ugbnYt5uUvi QuZglYsg7Yu5UIafaYTb+R/8/Ux3Z7qN5XKvwef9fWKcJBl0VE3RMtdQxOAS2CzSRnPU EA7bsLcjgZd1aXQ75ru6r0SuDXBY3E/VzTVAHJ2CWCpUQrZ9eSubyF/h2ucmS8EFL1G5 As5Bb2eiypl/BYVnzt7i7Q0626fC8qjYEUN4StSj3LcVQrv3f8aKOqUf5lBHtdHVcMEH gm+MPLZW7n+4syllERXEcq1Fl7t/2Tq2Eb18U+gfZahdx9WsaI/KYzpFyHAkq0jiCug7 DX6w== X-Gm-Message-State: AJIora8ak51DZVUUunTpQNpK7j6hFl+sICbigqmw3rSiOH8lEpz+NY/U GGyAdXyW3Z0S6oHcIW0yUbM= X-Google-Smtp-Source: AGRyM1solEebsJ8aWFaYBBFyec3sD94nnN3uwK9ZwQuWOqy8ZNWOPbTCC9XYFknZ9HYg3JgppifEhQ== X-Received: by 2002:adf:ef42:0:b0:21b:8e58:f24b with SMTP id c2-20020adfef42000000b0021b8e58f24bmr7538227wrp.257.1655755593841; Mon, 20 Jun 2022 13:06:33 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id a17-20020adffad1000000b0021b8749728dsm8178248wrs.73.2022.06.20.13.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:33 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 12/49] regmap-irq: Remove unused type_reg_stride field Date: Mon, 20 Jun 2022 21:06:07 +0100 Message-Id: <20220620200644.1961936-13-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It appears that no chip ever required a nonzero type_reg_stride and commit 1066cfbdfa3f ("regmap-irq: Extend sub-irq to support non-fixed reg strides") broke support. Just remove the field. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 6 ------ include/linux/regmap.h | 3 --- 2 files changed, 9 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 85d7fd4e07d7..b24818ad36e6 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -40,7 +40,6 @@ struct regmap_irq_chip_data { unsigned int **config_buf; unsigned int irq_reg_stride; - unsigned int type_reg_stride; bool clear_status:1; }; @@ -738,11 +737,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; - if (chip->type_reg_stride) - d->type_reg_stride = chip->type_reg_stride; - else - d->type_reg_stride = 1; - if (!map->use_single_read && map->reg_stride == 1 && d->irq_reg_stride == 1) { d->status_reg_buf = kmalloc_array(chip->num_regs, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 879afdc81526..1966ad4d0fa5 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1483,8 +1483,6 @@ struct regmap_irq_sub_irq_map { * @irqs: Descriptors for individual IRQs. Interrupt numbers are * assigned based on the index in the array of the interrupt. * @num_irqs: Number of descriptors. - * @type_reg_stride: Stride to use for chips where type registers are not - * contiguous. * @num_config_bases: Number of config base registers. * @num_config_regs: Number of config registers for each config base register. * @handle_pre_irq: Driver specific callback to handle interrupt from device @@ -1535,7 +1533,6 @@ struct regmap_irq_chip { int num_config_bases; int num_config_regs; - unsigned int type_reg_stride; int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); From patchwork Mon Jun 20 20:06:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF3B2CCA482 for ; Mon, 20 Jun 2022 20:07:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343885AbiFTUHD (ORCPT ); Mon, 20 Jun 2022 16:07:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343711AbiFTUGn (ORCPT ); Mon, 20 Jun 2022 16:06:43 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55AAD1D0F7; Mon, 20 Jun 2022 13:06:38 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id x6-20020a1c7c06000000b003972dfca96cso6194029wmc.4; Mon, 20 Jun 2022 13:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+NtcVbwET9acvq+sAYxoy+CjdvzW22WJrtUFi1dmUOo=; b=A+HDr9UU7+WRxYQh+og339fpLCReWCpP3YFgyupAlmxOcZBf7A6aFnN8naHelyc52s wQK8Fy9G6v6mTrGSQG4iRbkz5YauYi4iPPwJMQ1JvKJvozZ8vtLRWwHh4bZf1gWdX2JC dbwqJKti3GJ9HNo1vXGhcyksOzCb4wnGEGjB9WKXRA8144i5ltsXiu2qsbBUMRpGeiKM foGh+rMJtGnYFLs3jAHQB2MuzI/dNK6UnFensNutj1IivbApMFbM7lKCQeTK27rVsLY0 i4E+b9E7gLbrO8WdSQ5sENJyJXaP1cu0PzOoAW96YwnClCEE3EdUU+uTD9Lm7PL5cykC bC6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+NtcVbwET9acvq+sAYxoy+CjdvzW22WJrtUFi1dmUOo=; b=tHXFgqGmPfxtLQw8oZYnncGODCQui1vPd9M9rS5JdfPmOMNVEqt45adX+kAyDCBf1I c0FwjNZ1dwQR5wuerYXXeU8PsR/3RnTGb0aieys/VGYqJ2AqzaK+x6c4IcRYZr4V9ajN mRmBgCNKzJNxLpmtlgQ2Y+pjoPOU6LmMYbfXjqohPhCmPgr0gWGBod16Y7yUaoWwC5rA EYJdjAGNXf052tFOTLhMhyIFuzkz1oYaB6kwbs6WIjnDIhe9rxsWZF7T3BRTLpuGuJdd vMLFU963cY3MD2tYAByk/EzvI+YoDbTJZSacDEkFpCx6WSGFNJx/7OpSl8vjbzb7wxDa wieA== X-Gm-Message-State: AJIora+9aCqNLZ1+1Tou9Vlms7YA0r/rK4m56U9NDZQKh4rJUSS136yo KxGZYURYqClxVdLR97Ahf6E= X-Google-Smtp-Source: AGRyM1uQGdQ7m3OGY9UqaMyRP6uDRepmxOPNYfAd9XL91yLtMli/B6mx4CKZxfd/noc8TeLSorNR9Q== X-Received: by 2002:a05:600c:1547:b0:39c:804c:dc23 with SMTP id f7-20020a05600c154700b0039c804cdc23mr26538403wmg.23.1655755596798; Mon, 20 Jun 2022 13:06:36 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id l15-20020a05600c2ccf00b003974a00697esm20182858wmc.38.2022.06.20.13.06.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:36 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 14/49] regmap-irq: Do not use regmap_irq_update_bits() for wake regs Date: Mon, 20 Jun 2022 21:06:09 +0100 Message-Id: <20220620200644.1961936-15-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org regmap_irq_update_bits() is misnamed and should only be used for updating mask registers, since it checks the mask_writeonly flag. As there are no users of mask_writeonly, it is safe to replace the wake register updates with regmap_update_bits(). Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index b24818ad36e6..dd22d13c54c8 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -157,11 +157,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg = sub_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { if (d->chip->wake_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->wake_buf[i]); else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->wake_buf[i]); if (ret != 0) @@ -823,11 +823,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, reg = sub_irq_reg(d, d->chip->wake_base, i); if (chip->wake_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], 0); else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->wake_buf[i]); if (ret != 0) { From patchwork Mon Jun 20 20:06:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5F33CCA481 for ; Mon, 20 Jun 2022 20:07:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343743AbiFTUHK (ORCPT ); Mon, 20 Jun 2022 16:07:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343745AbiFTUGs (ORCPT ); Mon, 20 Jun 2022 16:06:48 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 968EF1EC6A; Mon, 20 Jun 2022 13:06:41 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id v14so16097604wra.5; Mon, 20 Jun 2022 13:06:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A1yO+P1r84NYRYcFw/ZOtSs0+i9q2Gv8RY8Jy0yOWqY=; b=j2RQqZvh6APhdsK/EoTEu81N6Pul31dRgCB3yZd8hs5x1U3Wtqcpi2IyHAfCICffHg gRE46BYS28U7XDvZvtUKB6Bkt51LTKNLuZl3ptMzn6BQlBgLD2r3jh/R/AjmK32xBhB/ 0LpqqAVt8CRLw8siXXmzBnqgCtafznYB6s/GT5pjpaL3Ybu6ff4EmEAU0UeweWfDlu9D gOHJaQkTCVmjnZ/VC5kfoHwVeu8ak+VVcbBIvos7fbcasrp9o1zr3tS8GqZqPBD0EZVy 6K+rt8doOLqgDBdCB8rSjJnqOboGjisOhkwGg2ROmQbfj+bRGDs7mmQs1WJsKO3Yyqid O2RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A1yO+P1r84NYRYcFw/ZOtSs0+i9q2Gv8RY8Jy0yOWqY=; b=nWtFLrsNs08MUomBWrE63NIqwQg/SOLXW5Rcr0mg6ZbwkoFDvDCv98bY2CMQgVoAkt +/k2eQCiHQCok9vxaTQylr45iKTeI5VAfEEhgNsSBwwR0dOBcyTzHar/J8O8j9Ip2bDn qh/lyUvc79e3BixIyxKkyWjoKdKSg89i8017XK+m/CqjYvPkamLghRIpk3GqnIRYEXHY vlreE12If2Hq9xLOCpuXaYbVMEFBALv2fJw0lGEKPcjdUs4aL6sgpGhlgMbldkALJnEt EzT7z3IVu6dGyrkvJy3XuhabYUucbiX2oD+WjB58/dCv10trDSwkJYeeyyu/6zAaMFhh gL8g== X-Gm-Message-State: AJIora8qIndvBiFDtAjWTTuWfFA1c2WBHphhMS3HI8OckDT17+6LQbHI wuxEfg0pCUkMQtyh16QqqtY= X-Google-Smtp-Source: AGRyM1vhjUq4WlL+gX1y0tyZ4A5CURR86xjVYNDJLu6ZP96h77dZI91Uh7rAWnxqjmtwV7H8z5gWhg== X-Received: by 2002:a5d:67c3:0:b0:21b:8cd4:ad60 with SMTP id n3-20020a5d67c3000000b0021b8cd4ad60mr8680011wrw.380.1655755600064; Mon, 20 Jun 2022 13:06:40 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id n1-20020a5d4201000000b0021a36955493sm14274307wrq.74.2022.06.20.13.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:39 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 16/49] regmap-irq: Rename regmap_irq_update_bits() Date: Mon, 20 Jun 2022 21:06:11 +0100 Message-Id: <20220620200644.1961936-17-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This function should only be used for updating mask bits, since it checks the mask_writeonly flag. To avoid confusion, rename it to regmap_irq_update_mask_bits(). Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 4c0d7f7aa544..875415fc3133 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -79,9 +79,9 @@ static void regmap_irq_lock(struct irq_data *data) mutex_lock(&d->lock); } -static int regmap_irq_update_bits(struct regmap_irq_chip_data *d, - unsigned int reg, unsigned int mask, - unsigned int val) +static int regmap_irq_update_mask_bits(struct regmap_irq_chip_data *d, + unsigned int reg, unsigned int mask, + unsigned int val) { if (d->chip->mask_writeonly) return regmap_write(d->map, reg, val & mask); @@ -129,11 +129,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg = sub_irq_reg(d, d->chip->mask_base, i); if (d->chip->mask_invert) { - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); } else if (d->chip->unmask_base) { /* set mask with mask_base register */ - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret < 0) dev_err(d->map->dev, @@ -142,12 +142,12 @@ static void regmap_irq_sync_unlock(struct irq_data *data) unmask_offset = d->chip->unmask_base - d->chip->mask_base; /* clear mask with unmask_base register */ - ret = regmap_irq_update_bits(d, + ret = regmap_irq_update_mask_bits(d, reg + unmask_offset, d->mask_buf_def[i], d->mask_buf[i]); } else { - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], d->mask_buf[i]); } if (ret != 0) @@ -761,17 +761,17 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, reg = sub_irq_reg(d, d->chip->mask_base, i); if (chip->mask_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf[i], ~d->mask_buf[i]); else if (d->chip->unmask_base) { unmask_offset = d->chip->unmask_base - d->chip->mask_base; - ret = regmap_irq_update_bits(d, + ret = regmap_irq_update_mask_bits(d, reg + unmask_offset, d->mask_buf[i], d->mask_buf[i]); } else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf[i], d->mask_buf[i]); if (ret != 0) { dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", From patchwork Mon Jun 20 20:06:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F556CCA481 for ; Mon, 20 Jun 2022 20:07:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343563AbiFTUHQ (ORCPT ); Mon, 20 Jun 2022 16:07:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343777AbiFTUGz (ORCPT ); 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id n15-20020a5d4c4f000000b0021b966abc19sm300460wrt.19.2022.06.20.13.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:42 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 18/49] mfd: qcom-pm8008: Add broken_mask_unmask irq chip flag Date: Mon, 20 Jun 2022 21:06:13 +0100 Message-Id: <20220620200644.1961936-19-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The qcom-pm8008 appears to use "1 to enable" convention for enabling interrupts, with separate set and clear registers. It's relying on masks and unmasks being inverted from their intuitive meaning, so it needs the broken_mask_unmask flag. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index da16566f7883..18095e72714e 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -141,6 +141,7 @@ static struct regmap_irq_chip pm8008_irq_chip = { .status_base = PM8008_STATUS_BASE, .mask_base = PM8008_MASK_BASE, .unmask_base = PM8008_UNMASK_BASE, + .broken_mask_unmask = true, .ack_base = PM8008_ACK_BASE, .config_base = pm8008_config_regs, .num_config_bases = ARRAY_SIZE(pm8008_config_regs), From patchwork Mon Jun 20 20:06:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583338 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B41FC43334 for ; Mon, 20 Jun 2022 20:07:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343832AbiFTUHV (ORCPT ); Mon, 20 Jun 2022 16:07:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245574AbiFTUG7 (ORCPT ); Mon, 20 Jun 2022 16:06:59 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF9D61F2E3; Mon, 20 Jun 2022 13:06:47 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id a10so6374645wmj.5; Mon, 20 Jun 2022 13:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1GpLIZISKqF9zFT4V1VJAxmf6nn2WqheoAcUl14eN+0=; b=jmla8ZkAOgrPskXynLCx05NWcsoEkbzw4ryinc4jYDe2RQIqHhPmV85RQKl7U9EmUI bF6TQ7O+iemjbNinkBjDldrg2yYic5jWOfe5sSL2/VPNdE+cj0lrEbPwTlpJTZs7BttW crq3WUJJa6c/dObTJx9WHn0Fl68Y8gRDUlBvzH70ODYLEG0pgioICXVMDThfVXbcB68W ixmvmMn2GGU7Gnw+8ih+LjNZ3VEsZF5IpRaRfmraY75SBGsUraU0gCZChrsxbjdlp0c3 X2WoHLbmrUSCLmnOMru0muZcahA8wUBHqdqxnvkpgp8UxCePBtXvm2MD7P0hwoO2uvZb BGGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1GpLIZISKqF9zFT4V1VJAxmf6nn2WqheoAcUl14eN+0=; b=HTw4yWS7AhzBS2WDE6OGr+XoGE0RKJqtRAXRKnXTFTF3SAZRcoZmEFZ3Ci44dv8RJb r+ENdeah9BprgFcLlxFo5o+mNzQbQPTOTh2vlSb83h2p7tEWXLEc25Qh5m20heHwTAA1 CAT6+KIMqmLyjEACiB7XNJ5VMr+21ZVZMIdqLYgO9VpZe0pvkiB/E103J5P0H9jFz8cq 4KTxTtTmqKrmtCLrk7b1W2oV2Vg2S6nuymoGINUY4sZ4cCBcz8gtQoDL31dspdxQQKUH 2VMaBD+72/tMpP3U0+dygfZLiyTnoNrQym469Y5QcQsxPhcLG0be3Y0Q0nh2EG709ad+ NSUQ== X-Gm-Message-State: AOAM533FjnZmUjwnGKDMVgjuFbCxABAe/P0JhgCcSqvlWA9IHgsEgUyG Ugm7a9bHqZ4fCc2liR/oIas= X-Google-Smtp-Source: ABdhPJx5dO+fQ4bSwFvdlpiB13bqVgu0Tmz5FemzXFKDgDhK5sVpfqzf/x7Jf9ygCYEoM4c832uaSw== X-Received: by 2002:a05:600c:19cb:b0:397:51db:446f with SMTP id u11-20020a05600c19cb00b0039751db446fmr36963462wmq.182.1655755605944; Mon, 20 Jun 2022 13:06:45 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id t17-20020adfe111000000b002102cc4d63asm17480550wrz.81.2022.06.20.13.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:45 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 20/49] regmap-irq: Fix inverted handling of unmask registers Date: Mon, 20 Jun 2022 21:06:15 +0100 Message-Id: <20220620200644.1961936-21-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To me "unmask" suggests that we write 1s to the register when an interrupt is enabled. This also makes sense because it's the opposite of what the "mask" register does (write 1s to disable an interrupt). But regmap-irq does the opposite: for a disabled interrupt, it writes 1s to "unmask" and 0s to "mask". This is surprising and deviates from the usual way mask registers are handled. Additionally, mask_invert didn't interact with unmask registers properly -- it caused them to be ignored entirely. Fix this by making mask and unmask registers orthogonal, using the following behavior: * Mask registers are written with 1s for disabled interrupts. * Unmask registers are written with 1s for enabled interrupts. This behavior supports both normal or inverted mask registers and separate set/clear registers via different combinations of mask_base/unmask_base. The mask_invert flag is made redundant, since an inverted mask register can be described more directly as an unmask register. To cope with existing drivers that rely on the old "backward" behavior, check for the broken_mask_unmask flag and swap the roles of mask/unmask registers. This is a compatibility measure which can be dropped once the drivers are updated to use the new, more consistent behavior. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 96 +++++++++++++++++--------------- include/linux/regmap.h | 7 ++- 2 files changed, 55 insertions(+), 48 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 875415fc3133..082a2981120c 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -30,6 +30,9 @@ struct regmap_irq_chip_data { int irq; int wake_count; + unsigned int mask_base; + unsigned int unmask_base; + void *status_reg_buf; unsigned int *main_status_buf; unsigned int *status_buf; @@ -95,7 +98,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) struct regmap *map = d->map; int i, j, ret; u32 reg; - u32 unmask_offset; u32 val; if (d->chip->runtime_pm) { @@ -124,35 +126,23 @@ static void regmap_irq_sync_unlock(struct irq_data *data) * suppress pointless writes. */ for (i = 0; i < d->chip->num_regs; i++) { - if (!d->chip->mask_base) - continue; - - reg = sub_irq_reg(d, d->chip->mask_base, i); - if (d->chip->mask_invert) { + if (d->mask_base) { + reg = sub_irq_reg(d, d->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, - d->mask_buf_def[i], ~d->mask_buf[i]); - } else if (d->chip->unmask_base) { - /* set mask with mask_base register */ + d->mask_buf_def[i], d->mask_buf[i]); + if (ret != 0) + dev_err(d->map->dev, "Failed to sync masks in %x\n", + reg); + } + + if (d->unmask_base) { + reg = sub_irq_reg(d, d->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); - if (ret < 0) - dev_err(d->map->dev, - "Failed to sync unmasks in %x\n", + if (ret != 0) + dev_err(d->map->dev, "Failed to sync masks in %x\n", reg); - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; - /* clear mask with unmask_base register */ - ret = regmap_irq_update_mask_bits(d, - reg + unmask_offset, - d->mask_buf_def[i], - d->mask_buf[i]); - } else { - ret = regmap_irq_update_mask_bits(d, reg, - d->mask_buf_def[i], d->mask_buf[i]); } - if (ret != 0) - dev_err(d->map->dev, "Failed to sync masks in %x\n", - reg); reg = sub_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { @@ -634,7 +624,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, int i; int ret = -ENOMEM; u32 reg; - u32 unmask_offset; if (chip->num_regs <= 0) return -EINVAL; @@ -732,6 +721,24 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->chip = chip; d->irq_base = irq_base; + /* + * Swap role of mask_base and unmask_base if mask bits are inverted. + * + * Historically, chips that specify both mask_base and unmask_base + * got inverted mask behavior; this was arguably a bug in regmap-irq + * and there was no way to get the normal, non-inverted behavior. + * Those chips will set the broken_mask_unmask flag. They don't set + * mask_invert so there is no need to worry about interactions with + * that flag. + */ + if (chip->mask_invert || chip->broken_mask_unmask) { + d->mask_base = chip->unmask_base; + d->unmask_base = chip->mask_base; + } else { + d->mask_base = chip->mask_base; + d->unmask_base = chip->unmask_base; + } + if (chip->irq_reg_stride) d->irq_reg_stride = chip->irq_reg_stride; else @@ -755,28 +762,27 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, /* Mask all the interrupts by default */ for (i = 0; i < chip->num_regs; i++) { d->mask_buf[i] = d->mask_buf_def[i]; - if (!chip->mask_base) - continue; - reg = sub_irq_reg(d, d->chip->mask_base, i); - - if (chip->mask_invert) + if (d->mask_base) { + reg = sub_irq_reg(d, d->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, - d->mask_buf[i], ~d->mask_buf[i]); - else if (d->chip->unmask_base) { - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; - ret = regmap_irq_update_mask_bits(d, - reg + unmask_offset, - d->mask_buf[i], - d->mask_buf[i]); - } else + d->mask_buf_def[i], d->mask_buf[i]); + if (ret != 0) { + dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", + reg, ret); + goto err_alloc; + } + } + + if (d->unmask_base) { + reg = sub_irq_reg(d, d->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, - d->mask_buf[i], d->mask_buf[i]); - if (ret != 0) { - dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", - reg, ret); - goto err_alloc; + d->mask_buf_def[i], ~d->mask_buf[i]); + if (ret != 0) { + dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", + reg, ret); + goto err_alloc; + } } if (!chip->init_ack_masked) diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 21a70fd99493..0cf3c4a66946 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1451,10 +1451,11 @@ struct regmap_irq_sub_irq_map { * main_status set. * * @status_base: Base status register address. - * @mask_base: Base mask register address. + * @mask_base: Base mask register address. Mask bits are set to 1 when an + * interrupt is masked, 0 when unmasked. * @mask_writeonly: Base mask register is write only. - * @unmask_base: Base unmask register address. for chips who have - * separate mask and unmask registers + * @unmask_base: Base unmask register address. Unmask bits are set to 1 when + * an interrupt is unmasked and 0 when masked. * @ack_base: Base ack address. If zero then the chip is clear on read. * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id l9-20020a05600c4f0900b0039db500714fsm16981828wmq.6.2022.06.20.13.06.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:48 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 22/49] mfd: sun4i-gpadc: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:17 +0100 Message-Id: <20220620200644.1961936-23-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/sun4i-gpadc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/sun4i-gpadc.c b/drivers/mfd/sun4i-gpadc.c index cfe14d9bf6dc..edc180d83a4b 100644 --- a/drivers/mfd/sun4i-gpadc.c +++ b/drivers/mfd/sun4i-gpadc.c @@ -34,9 +34,8 @@ static const struct regmap_irq_chip sun4i_gpadc_regmap_irq_chip = { .name = "sun4i_gpadc_irq_chip", .status_base = SUN4I_GPADC_INT_FIFOS, .ack_base = SUN4I_GPADC_INT_FIFOS, - .mask_base = SUN4I_GPADC_INT_FIFOC, + .unmask_base = SUN4I_GPADC_INT_FIFOC, .init_ack_masked = true, - .mask_invert = true, .irqs = sun4i_gpadc_regmap_irq, .num_irqs = ARRAY_SIZE(sun4i_gpadc_regmap_irq), .num_regs = 1, From patchwork Mon Jun 20 20:06:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A35D3CCA480 for ; Mon, 20 Jun 2022 20:07:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343942AbiFTUHr (ORCPT ); Mon, 20 Jun 2022 16:07:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343925AbiFTUHH (ORCPT ); Mon, 20 Jun 2022 16:07:07 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A28241EAFB; Mon, 20 Jun 2022 13:06:53 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id o8so16102762wro.3; Mon, 20 Jun 2022 13:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/LPf9h09XUJR/z/RdQdPV0VQS/kTyakjP+1OAofeWXA=; b=fwpJrSBMfmFPeeNXJrlpjWlkFshzFm6Y1DWOVq+h4L71A/9e1R5aHmopQ9JlXAYX77 p/aPMsuwp0jXJ6JA/lErm+8RcPw1nwj/qzcNe82rYLGJJE87iMHlnWgUuO98N/3+uLWl HoFIstzlvMDtCLgfhnOriWLoNwZv6+3clTJtgU5AJImo5hzLcA8Xl5biIy+qCPN0Yl2h sSZ3MIekuF7sfDNA5dosij4OPFFY4DXnc1sarY9jKvYuFBzZIvgCKpyr0XlJB/Ymar7p 76Xyx3zNFdDnkRRyU54ZBIwLy/ubU9zZyaI0NzK9C8RtA20uucTc0zHujNOvDTsjWaG+ UbTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/LPf9h09XUJR/z/RdQdPV0VQS/kTyakjP+1OAofeWXA=; b=5zyP9iDTayzNUHX2jrK+4Xo5jIqFGovJwmn+wIC7M4AsNJ7EYYdogvIhJQMe8nFpPZ eAYPUIYEqkQKdp/OCHaxgEfpRbBGB17KwPG4K251Xc2kf+GlmeY3fcSy6U5EDq6UEZ54 Yl3Qbo98UI9Ja9mARBjHXAfFC+iD5EYK0z3GKUx0OjSyZUkuyKJwTYissorNQ7+sovMF tKVjFPZyM8em5prJ60wH7zb9IhrQ5MV6d/mW4EJdgeQe5U4bMXbkAFoYsuA7HwH6xO/c H3WBgZjL9tnTLmInF6O0x7S1IHg0zyOleBLjpzYJcRf7zj7d0QN8RBoSOM33tW7NcGVf AaQQ== X-Gm-Message-State: AJIora8PZvyImUZP81FSpprzxuzHg3xPc3RKGHLQorF0X8L9hJ68Rnkv UOXackf/n29UDvusJxQcRGE= X-Google-Smtp-Source: AGRyM1saqWHhZeAqgNDua/lIIE8QUgq+ce7t9oCt2daRUSekH7GNKx27L1qwZwbxMxNYwR5edglGYw== X-Received: by 2002:a05:6000:156c:b0:218:5691:e72b with SMTP id 12-20020a056000156c00b002185691e72bmr24333023wrz.95.1655755612132; Mon, 20 Jun 2022 13:06:52 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id h17-20020a05600c2cb100b00397393419e3sm20418814wmc.28.2022.06.20.13.06.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:51 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 24/49] mfd: rt5033: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:19 +0100 Message-Id: <20220620200644.1961936-25-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/rt5033.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/rt5033.c b/drivers/mfd/rt5033.c index f1236a9acf30..dc9bf4057a09 100644 --- a/drivers/mfd/rt5033.c +++ b/drivers/mfd/rt5033.c @@ -29,8 +29,7 @@ static const struct regmap_irq rt5033_irqs[] = { static const struct regmap_irq_chip rt5033_irq_chip = { .name = "rt5033", .status_base = RT5033_REG_PMIC_IRQ_STAT, - .mask_base = RT5033_REG_PMIC_IRQ_CTRL, - .mask_invert = true, + .unmask_base = RT5033_REG_PMIC_IRQ_CTRL, .num_regs = 1, .irqs = rt5033_irqs, .num_irqs = ARRAY_SIZE(rt5033_irqs), From patchwork Mon Jun 20 20:06:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03FC4C43334 for ; Mon, 20 Jun 2022 20:09:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343818AbiFTUJZ (ORCPT ); Mon, 20 Jun 2022 16:09:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244837AbiFTUHQ (ORCPT ); Mon, 20 Jun 2022 16:07:16 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5138F201BB; Mon, 20 Jun 2022 13:06:57 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id c21so16101137wrb.1; Mon, 20 Jun 2022 13:06:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aFyu5esk/Zb2lNQzmvPRJ9QuwxnaeJqoP/Ih9wxKaVE=; b=Hx66dBMoypw3HFQ6ZlYKo/eR568ezNz8W5y6iElQBkDHOOhjdkd2OOUeXyuM4IJATJ nOWdw0iuhlEmOX8vNXfnAWlMC147l0U4mfE3S2gNMusmdyP2zWZJyHYTvmwCppX/Iskv vwfm6snjUXGKxpT/jRbYfj6RIQgagfupLw7jvBu/UAvy5tQBhPO9eQAGfcl+0IEp9k+M wAT+eo4bwJp8EjwTVNo5vMEs/MgiikrzJ6fDgsNBPx0jramgLds5jhx1zxPNI3c4MG3Q IGQX9FrRR/YfkFCB3wF6UfpCKRFn8rTPevafX0DQ9EPElddTBsBLn3qw+l3BZXYk9GKI 5nXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aFyu5esk/Zb2lNQzmvPRJ9QuwxnaeJqoP/Ih9wxKaVE=; b=lPH4BUV7yDD2elo5qJ1dTeVjPZVDTYv+IdLqSK1NmK1aXdT+8OqWqTQHiwQwQ5hCPn s/3FdVIv5GNxcbMMflwLZIWI7L9bfuXJdFBsO53yG3Js/tK4iLcexXMfxBblKt3gkVC9 YYRDQ+tcPXTCA6L5+0OSwwGpUnLf5zYlOFXgCMGk17APWujxTWan6EaQAT7iXY6reBhF cin552d+3yYO6TssGC45bnH+rBP6eIaOH1e23BdE0gUfzkjN9NFOGEUy348vpmA6k8b1 ycs+AjFPjm0bDoom4+H5zfMtzfcvwIBpWb1OfITUBfW16Ll5jvIOYaFFl/LoMGh48ph/ umhA== X-Gm-Message-State: AJIora+caxppXCZVXOgWxKx1vZJD6m0yFYSZa8NSqvH4u2UhepFXDJRD JjVtTKkGNR6olKBB7NXXkZk= X-Google-Smtp-Source: AGRyM1tHw8LdpOYQ4ocdkg/wb7xbdY+ptC8YBcgzkEw+K1EEKq9i385MNLM8p7QV0MNlJKBoINhp9g== X-Received: by 2002:a5d:5847:0:b0:218:5319:f4e3 with SMTP id i7-20020a5d5847000000b002185319f4e3mr25586723wrf.500.1655755615568; Mon, 20 Jun 2022 13:06:55 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id w5-20020a7bc105000000b003976fbfbf00sm15528084wmi.30.2022.06.20.13.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:54 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 26/49] mfd: rn5t618: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:21 +0100 Message-Id: <20220620200644.1961936-27-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/rn5t618.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/rn5t618.c b/drivers/mfd/rn5t618.c index 384acb459427..7ed002d090bd 100644 --- a/drivers/mfd/rn5t618.c +++ b/drivers/mfd/rn5t618.c @@ -80,8 +80,7 @@ static const struct regmap_irq_chip rc5t619_irq_chip = { .num_irqs = ARRAY_SIZE(rc5t619_irqs), .num_regs = 1, .status_base = RN5T618_INTMON, - .mask_base = RN5T618_INTEN, - .mask_invert = true, + .unmask_base = RN5T618_INTEN, }; static struct i2c_client *rn5t618_pm_power_off; From patchwork Mon Jun 20 20:06:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92FB3C43334 for ; Mon, 20 Jun 2022 20:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344049AbiFTUIW (ORCPT ); Mon, 20 Jun 2022 16:08:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344056AbiFTUHU (ORCPT ); Mon, 20 Jun 2022 16:07:20 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC67219C2E; Mon, 20 Jun 2022 13:06:58 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id q9so16080258wrd.8; Mon, 20 Jun 2022 13:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dZq4DXS5hfuZufkfinYetDi/sPSwHy1FNwiaqhpssa4=; b=bpjyLwVivcFSW5QVbgosK/o2QuZHms1vCc6tC1sGza+OT1YZWe465cW4jNRW7fx4ks msy9Ia4HJKGcKj1u1StthDIoGNe0jPNNRCwfixCCbhsIu8kl5EdbhBkaAOJGTjzxLAZf Bv9bbx8NKTphmbx8bemLzrtymECuH5WWFEStWDPJlp6dqluOf0EOgjov5G1nTwcbn/99 6V1IcwQ/cUBFnAQ+UHfvGn1YssCCtL98+3EotWIqSk0wFS+MMtuhmD5WuWOcv9MXK3SK oL+O91AqJHe+kT2bNOas/VelkJQaxBD6di93/z4nY9iPMcMc3LCgHQ1sLEmd+cWZ+9Od WH6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dZq4DXS5hfuZufkfinYetDi/sPSwHy1FNwiaqhpssa4=; b=HdmHxVTPTBR7cIEVo6Vb8PiCouXmbAa0QOv83Ej3FHtQLHAurBx4VvlfU1YRJtKrMh ahzbeU0vpYeqJav+L9XmL/plcl7Oa7R7vHUCc3nOzmdu4MiOZ8IXxP81PMxPkjYpYoNc rJ5qPv0eozy/VfxbmSMJ+L1Y5A4zkPfz7gXvwkkdT8MZShSGp/EVQvDfnmw4VT4OOM+2 hj7r+a1oceWVExJ4WXc2Gc+lyOlQYM8G8cNXyzMtbViHC46R/UXTj7tCo0mY2jllLZLd y+fdkyo5EDwGhJmLVsgK1XaU0bE7WgNrnN7eI8LNWFaGIb2IkMzquzbs/kgidc/2LOWE IPVA== X-Gm-Message-State: AJIora9GbpKrc8k/Zr8ttGv2m3brVc44NASogY3cOgWEhHakgt8bxCHZ L0+f96IEHDiWrjLoeEEtW08= X-Google-Smtp-Source: AGRyM1uUe+TJYcYrAuoAsTQoql0GG3zgxE4cm70M4L11J/HjtjuiCzoxQPxyTkB4HBjRJYR8SssVEQ== X-Received: by 2002:adf:fb06:0:b0:21a:3dc9:f12d with SMTP id c6-20020adffb06000000b0021a3dc9f12dmr19252192wrr.204.1655755617100; Mon, 20 Jun 2022 13:06:57 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id x1-20020adff0c1000000b002103cfd2fbasm14315943wro.65.2022.06.20.13.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:56 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 27/49] mfd: gateworks-gsc: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:22 +0100 Message-Id: <20220620200644.1961936-28-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/gateworks-gsc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/gateworks-gsc.c b/drivers/mfd/gateworks-gsc.c index d87876747b91..28ec167a9861 100644 --- a/drivers/mfd/gateworks-gsc.c +++ b/drivers/mfd/gateworks-gsc.c @@ -189,8 +189,7 @@ static const struct regmap_irq_chip gsc_irq_chip = { .num_irqs = ARRAY_SIZE(gsc_irqs), .num_regs = 1, .status_base = GSC_IRQ_STATUS, - .mask_base = GSC_IRQ_ENABLE, - .mask_invert = true, + .unmask_base = GSC_IRQ_ENABLE, .ack_base = GSC_IRQ_STATUS, .ack_invert = true, }; From patchwork Mon Jun 20 20:06:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583334 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18FDDC43334 for ; Mon, 20 Jun 2022 20:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243685AbiFTUIo (ORCPT ); Mon, 20 Jun 2022 16:08:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343894AbiFTUHj (ORCPT ); Mon, 20 Jun 2022 16:07:39 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0682E20190; Mon, 20 Jun 2022 13:07:00 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id g4so16059750wrh.11; Mon, 20 Jun 2022 13:07:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RL0fwUpj3N31VObGflnvTdc3SYbFvbOFJTIucbQixBw=; b=Mlv4ZVoHQKH/diZ7wxwIL4K/NMJzc8U94Vgk4Cv6mLqtv2zUYMSW25mN9q0aL0QiaD ypWyVxkxCSP8wGvJCokCsjQ6tDA09v/ytF7zvcl648K7FlONHBR2wfNK3QShVbur16Ms Etfs+ATYrdsjBlliM9yYPEfiDP24lw5E53L/DQ+aFBEaoSuyH0FKKVlxJgKMAVEDu74C qNbf8xDFV/CcJqFhatQhPeGSPTWRTO55xPy2YKxC6vO/a5lLkP3E2xpOBkHescTgDCGf 6sV5K6mdGgz67dpXL7CLkkp/9x203Hye1oIstypDYQK4gwAVULEnVqIxaa7ZmZAes0sL 9TIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RL0fwUpj3N31VObGflnvTdc3SYbFvbOFJTIucbQixBw=; b=h0r3xXI6j04VogwBtKVWLaKEuk1b4XOAgtqfOx4xU1VuZyvpE5yXOhiuoK5O3sQFI6 e12W6HHVoBI0pdY42iYM73sqsaXvNb+v2BuAhRPaZh0SnHHWMQVoKitX4pu8L2/ojVp6 v3gOEC8rXaM5xPl0lAK3PFxZBhaoU6XPoLphXz5Xu64P9RktVmGr/V3pcPSwTLHRCKBu 3OgII15zxeMHU7AvZq3YewGsIm/Moh97XXY0Aydiwo5R7EQ58epzEXW0MFOWDCyNa78g bpfGK6mQpWl2e42JvGl0QjiU++Bst9McLQo/NxIqsrpbDqq3NK+/6Bte/L6W4n2DpAEB nuUg== X-Gm-Message-State: AJIora8MKZCQQHcyJTzFtmE8J7EEB6h+yNo5MozhVLjiuPnNX/wHYxQ3 BepDW9Caa3v/iEt/iJnuNu8= X-Google-Smtp-Source: AGRyM1sc2kxmFsNd28wLHl+sBWx8EhrjSubA+8EnJdnvaG1LPBATT/Oqb8jppvaI5mcfhWVI8YU61A== X-Received: by 2002:a5d:47a8:0:b0:217:b5ea:bdfb with SMTP id 8-20020a5d47a8000000b00217b5eabdfbmr25488579wrb.492.1655755620510; Mon, 20 Jun 2022 13:07:00 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id n23-20020a05600c3b9700b0039c5224bfcbsm20985958wms.46.2022.06.20.13.06.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:00 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 29/49] mfd: atc260x: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:24 +0100 Message-Id: <20220620200644.1961936-30-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/atc260x-core.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/atc260x-core.c b/drivers/mfd/atc260x-core.c index 7148ff5b05b1..7c5de3ae776e 100644 --- a/drivers/mfd/atc260x-core.c +++ b/drivers/mfd/atc260x-core.c @@ -100,8 +100,7 @@ static const struct regmap_irq_chip atc2603c_regmap_irq_chip = { .num_irqs = ARRAY_SIZE(atc2603c_regmap_irqs), .num_regs = 1, .status_base = ATC2603C_INTS_PD, - .mask_base = ATC2603C_INTS_MSK, - .mask_invert = true, + .unmask_base = ATC2603C_INTS_MSK, }; static const struct regmap_irq_chip atc2609a_regmap_irq_chip = { @@ -110,8 +109,7 @@ static const struct regmap_irq_chip atc2609a_regmap_irq_chip = { .num_irqs = ARRAY_SIZE(atc2609a_regmap_irqs), .num_regs = 1, .status_base = ATC2609A_INTS_PD, - .mask_base = ATC2609A_INTS_MSK, - .mask_invert = true, + .unmask_base = ATC2609A_INTS_MSK, }; static const struct resource atc2603c_onkey_resources[] = { From patchwork Mon Jun 20 20:06:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF1EFCCA482 for ; Mon, 20 Jun 2022 20:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343895AbiFTUIs (ORCPT ); Mon, 20 Jun 2022 16:08:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344097AbiFTUIW (ORCPT ); Mon, 20 Jun 2022 16:08:22 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAF4F21249; Mon, 20 Jun 2022 13:07:11 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id l126-20020a1c2584000000b0039c1a10507fso6197188wml.1; Mon, 20 Jun 2022 13:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rzfzyKEVoJaKFIv88YU1vTCrVQJBpK7ii1ptmDvGvSE=; b=qBJcC0LrxQSAdxyKj5Dt7HUFUmjMISoYgjBHUUClNbIz3vAp9h4I6Lqto2o/8nRZZx +mUtIMCKQ+xDXPL3Fzv7A9LsfxQhVJy+J3jisVRnKW/heO0ptBVZJfGA10gsSJrLxZO+ MObbJW6hGStsGnZRd48uGh/4qGcgNShaBsFXlaMlKP83cLUJ5mnOfQscQbtReaFC3JVv djWshs0XGTygSwTV7AEfyGWiz4kJ7raOzjYloQWDqDDB2Jm1I+3fzts9p4jEUGs+ylCU BlkyfP5HaSiXqAYXZ7zggOUoAuRHWYspwGWZ2TzWqacHn9MVYPY2Vzt3RKPNhtN644ir H1Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rzfzyKEVoJaKFIv88YU1vTCrVQJBpK7ii1ptmDvGvSE=; b=AXBLqiyJ0uqNIm7UWWbRALy7woyYwMVrW29TZ2C56HzZ1+H9jEnU1EDQAlzdQbA9hv U9xymh5oJzy5efgoe4uiMLfQH+mzs+ZlFgf5YkmQewVBFpujhlwhWZxw6nBGo3KVr0w6 pf85W9Zn4AGJ/qFPGqwxW8klC7lJlkKAjY+aLTHgEvQzg51/AsyA/MD+dzbXPjbsi6DP mMqXL+K65eWydj7cWSSCEvWmsveJv1gQG/Fq7zy/YfI+faa6f/UPzePXs9QRm/qgokbg W+qUqAFzJo7WssJHt9wA9ZoSJ/vqXByrljl7G8G7Iy1hY9m4/9bmgFm1H8y9UKNXQGQS 7sLQ== X-Gm-Message-State: AOAM533OefxMhXvocSFrVLin1zJg6Gfg9t/jbWTUS+fd/KdV+mYSClKO oxD5QZjldw0Tci5yQQ96yvI= X-Google-Smtp-Source: ABdhPJyInyenW+OvDrbjpJKIaFUgNOigofr86k1OtUqbh4EqGuM90WNh58WAi7KJRkr+4OM3pXCRPQ== X-Received: by 2002:a1c:4c13:0:b0:39c:5a6b:8540 with SMTP id z19-20020a1c4c13000000b0039c5a6b8540mr36262410wmf.106.1655755624155; Mon, 20 Jun 2022 13:07:04 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b0039c5645c60fsm28045293wms.3.2022.06.20.13.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:03 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 31/49] mfd: max14577: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:26 +0100 Message-Id: <20220620200644.1961936-32-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org An inverted mask register can be described more directly as an unmask register. Also drop useless mask_invert flag from the pmic irq chip. Signed-off-by: Aidan MacDonald --- drivers/mfd/max14577.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/max14577.c b/drivers/mfd/max14577.c index 6c487fa14e9c..7a501dcc48f6 100644 --- a/drivers/mfd/max14577.c +++ b/drivers/mfd/max14577.c @@ -209,8 +209,7 @@ static const struct regmap_irq max14577_irqs[] = { static const struct regmap_irq_chip max14577_irq_chip = { .name = "max14577", .status_base = MAX14577_REG_INT1, - .mask_base = MAX14577_REG_INTMASK1, - .mask_invert = true, + .unmask_base = MAX14577_REG_INTMASK1, .num_regs = 3, .irqs = max14577_irqs, .num_irqs = ARRAY_SIZE(max14577_irqs), @@ -239,8 +238,7 @@ static const struct regmap_irq max77836_muic_irqs[] = { static const struct regmap_irq_chip max77836_muic_irq_chip = { .name = "max77836-muic", .status_base = MAX14577_REG_INT1, - .mask_base = MAX14577_REG_INTMASK1, - .mask_invert = true, + .unmask_base = MAX14577_REG_INTMASK1, .num_regs = 3, .irqs = max77836_muic_irqs, .num_irqs = ARRAY_SIZE(max77836_muic_irqs), @@ -255,7 +253,6 @@ static const struct regmap_irq_chip max77836_pmic_irq_chip = { .name = "max77836-pmic", .status_base = MAX77836_PMIC_REG_TOPSYS_INT, .mask_base = MAX77836_PMIC_REG_TOPSYS_INT_MASK, - .mask_invert = false, .num_regs = 1, .irqs = max77836_pmic_irqs, .num_irqs = ARRAY_SIZE(max77836_pmic_irqs), From patchwork Mon Jun 20 20:06:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3106CCA488 for ; Mon, 20 Jun 2022 20:08:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343981AbiFTUIu (ORCPT ); Mon, 20 Jun 2022 16:08:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344467AbiFTUI0 (ORCPT ); Mon, 20 Jun 2022 16:08:26 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D2B321266; Mon, 20 Jun 2022 13:07:17 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id q15so6375291wmj.2; Mon, 20 Jun 2022 13:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ioRXJqRjZqDXf4uhS+zPl4sLu26/rBgrPA3q0xnI1Pk=; b=bnHiwq/OClrzuqi/qkl++cxkoDtbanVKeopfnQWVzhU6b4gvB+73xPfwfecrFvG0fg c94hGekA8YHpGAXe9zm4qRYYRU0MygrSlEa2zYIu7XgB36o7uYhJEoYrROKQmUBSIY4o GC/IaRLTd6YmBywt5HAzxlmtbcVviB558rpnzU3IVr9JxhUY6/cumMLeOBejkhO41DwT DsEaO5ReO1eTDEIa8hszhVJBZB5Hbw7MzANj+u8x+/yO6D10YAQ3WQUnywEkt8FEYgLt +TQ57DgXgy4ZTyDpkcfoqzaf3zEuCixQ6UraTBXfq3S+ppuoQQgmhycH0ATq77SlYom2 h4rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ioRXJqRjZqDXf4uhS+zPl4sLu26/rBgrPA3q0xnI1Pk=; b=hLb1KtD6u9DGyN8WI8k9lvm92CxwGF4OhhDQ3TjnCdq2xiqibiSv009z84m3H+RIAD 1Z9E8fzR9DUvbazaFYlhIqX9Wg9wb4b1xnB1WYszm2r7iw49Zzwe40PjZssgJIwy0ANK Wn/5CVMOSYczWOD2EBodHFYeXZzIAva8JEuFXTucBmMdcpH0s7+YSH5BFuFscz0LRDzU m9cjtIiH9K+rVEbrNtGaYeqNaHrh5dknNBVTS3oJHnQOuqJ2q85+PfufffNjbkrX8pWS WqGXIBy9EG0MxWvr6jHit/xIO0P49wcMlO7EzRH6O/kk3c7rbE7Mm1LzmNtEKxNZUGhm DXgw== X-Gm-Message-State: AOAM5329m+jt+flJsb++aMnce5/nfaBuUbDlkxDCHGoKJQlzPFt60XZe z/97j11chR+wQHbmgCtbZ5E= X-Google-Smtp-Source: ABdhPJyk2pG0lVa2PXgg+IL73pDXXybyl784/0CAFzghroiptrtMxz7E7l4unjYw5iEqpwxxNZmr7A== X-Received: by 2002:a1c:4c0d:0:b0:39c:5233:1873 with SMTP id z13-20020a1c4c0d000000b0039c52331873mr37323556wmf.28.1655755627588; Mon, 20 Jun 2022 13:07:07 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id o10-20020a1c4d0a000000b003942a244ee6sm15738587wmh.43.2022.06.20.13.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:07 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 33/49] mfd: rohm-bd718x7: drop useless mask_invert flag on irqchip Date: Mon, 20 Jun 2022 21:06:28 +0100 Message-Id: <20220620200644.1961936-34-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There's no need to set the flag explicitly to false, since that is the default value from zero initialization. Signed-off-by: Aidan MacDonald Reviewed-by: Matti Vaittinen --- drivers/mfd/rohm-bd718x7.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c index bfd81f78beae..ad6c0971a997 100644 --- a/drivers/mfd/rohm-bd718x7.c +++ b/drivers/mfd/rohm-bd718x7.c @@ -70,7 +70,6 @@ static struct regmap_irq_chip bd718xx_irq_chip = { .mask_base = BD718XX_REG_MIRQ, .ack_base = BD718XX_REG_IRQ, .init_ack_masked = true, - .mask_invert = false, }; static const struct regmap_range pmic_status_range = { From patchwork Mon Jun 20 20:06:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B322DCCA482 for ; Mon, 20 Jun 2022 20:08:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344047AbiFTUIw (ORCPT ); Mon, 20 Jun 2022 16:08:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344480AbiFTUI0 (ORCPT ); Mon, 20 Jun 2022 16:08:26 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55B7B1EEEE; Mon, 20 Jun 2022 13:07:17 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id h14-20020a1ccc0e000000b0039eff745c53so2062728wmb.5; Mon, 20 Jun 2022 13:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FJAftx/p0C7OJqXldJ+ksCvuM2Jz1/dLJXnCMlN2VIw=; b=SqSwnGBcriuBOSFplaryTgzwQV9etoBhh79kFYweRlmDdxQeRvrcZhZxeGzYrNQvjK 69NE66snB8AAFxosGQi32hwg8wAh/0UlVrRlylnlYpF3UP2foQigCMMdDJ2hf1VoUcQw IGJhoucIfU9bShmNTRIW7SeERFLMl9SzWwa/gkuyhaNnZGAegN5/b8AD7xgZbr+q96V3 wIZE74xoK0opWS9DO77kd+xhhjv05vYGMC2P4dGUBy6pWp5QiJg6JRI3NjoqvsL5Fuv7 /rYrzhVG+vkyLBPngH5EcdERxjCI3qHqaUK8MI70z8mDb7VK4k5Utxh9mIEOvpvvGk/6 VkjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FJAftx/p0C7OJqXldJ+ksCvuM2Jz1/dLJXnCMlN2VIw=; b=Otq8M6+42b71o3G3Q3Rvo1ZkViaqyr87cDw5mRcyeKX9Zn1ocRW+PwqfCWBJkoz8L4 4msQqfgoswgV95LK7YxozpRgdak4Aj/HKG9fp+xmljeLZMQ90oJ9hWOwAJULE8Cz22eU MMhSTXW9WK4rG28vgefhJutuZkl7pbYJtgCAJwCSHQrCLTICtZ6iP42VsVNLLHhAfyDX TrKbmWufV6RP9UmIMauBDJ1Bn1z8Q2SshaLw8hDbjQ7392/VQbgR2gtMwWjaxGnjI7bO /5av8+TMwaLlvKCml0BVSJ09aezcrbeeCguMZlhQuxSvbBzhTmtTOfSqm2n0LjcFjHM1 t+ZQ== X-Gm-Message-State: AJIora/XUR513u3XzLqCQxbWKHr1gAzUzISEhfknHGY3r8Jx0l9/E6uC XI/Mc926bbZngZlSvHWeLGkAahpGYH4= X-Google-Smtp-Source: AGRyM1uYqQE7GmYoWseO34ZpgDLrPdxmQJYvkYR87njx8ZglDl7MI8oKPbgMJxyF1RluTFoj9tUheA== X-Received: by 2002:a1c:c909:0:b0:3a0:1725:619d with SMTP id f9-20020a1cc909000000b003a01725619dmr5451578wmb.19.1655755629537; Mon, 20 Jun 2022 13:07:09 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id q7-20020adf9dc7000000b0020cdcb0efa2sm7500229wre.34.2022.06.20.13.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:09 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 34/49] mfd: max77843: drop useless mask_invert flag on irqchip Date: Mon, 20 Jun 2022 21:06:29 +0100 Message-Id: <20220620200644.1961936-35-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There's no need to set the flag explicitly to false, since that is the default value from zero initialization. Signed-off-by: Aidan MacDonald --- drivers/mfd/max77843.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mfd/max77843.c b/drivers/mfd/max77843.c index 209ee24d9ce1..4da58eab1603 100644 --- a/drivers/mfd/max77843.c +++ b/drivers/mfd/max77843.c @@ -59,7 +59,6 @@ static const struct regmap_irq_chip max77843_irq_chip = { .name = "max77843", .status_base = MAX77843_SYS_REG_SYSINTSRC, .mask_base = MAX77843_SYS_REG_SYSINTMASK, - .mask_invert = false, .num_regs = 1, .irqs = max77843_irqs, .num_irqs = ARRAY_SIZE(max77843_irqs), From patchwork Mon Jun 20 20:06:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 841B9CCA481 for ; Mon, 20 Jun 2022 20:09:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344291AbiFTUJA (ORCPT ); Mon, 20 Jun 2022 16:09:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344555AbiFTUI2 (ORCPT ); Mon, 20 Jun 2022 16:08:28 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49B7D1F2DD; Mon, 20 Jun 2022 13:07:21 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id v14so16099105wra.5; Mon, 20 Jun 2022 13:07:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dbyvlkbY4sJOjh3UQdGyOPNGXQQ/y7Irc+C1CWkw+ak=; b=O31tT53sO/Sz1zUUmz4+b7clogfECSiQb9wF145zFCWeos95kyFGhyMNr0ihPdqpqx bJc50KM0wIrtRqZCqzGADVF4M3k1QjGTHVo1VYjGwT74JLbT3B4kvTSheNe818VtY8DZ HDqJJzSXulU9aA8Q7p64IRscmVk+LyazVQczqtnvFpnAbVUfczXyJXpSX6rv84tpA2ID Fp6mzmh7R3C0ofGj++M07N5Nk1RQvkOi9t24WmMCnaJkp1Xa/s9Jij2cEafhCNNYBn56 seJUbVNIALw9YCjjSnuje4l/jDR/w2Hi2qVNJRlUiL9Bqsun5VReJR/qIIMDhEg6iASO mm4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dbyvlkbY4sJOjh3UQdGyOPNGXQQ/y7Irc+C1CWkw+ak=; b=ueJpNm8kGLEYqGRXiP8xtnT+hNrVY2HDtZkGZRR9kN3lTrBfoXV36T2G8JbsgenLH5 mDgAHzvaUPNy7UPXI56YRLxImw3xoqIrNMkL+2b31bAsE0IDuDWU+RJR9XUCm6Lku/WI u8VBc1HH2b2wEPu/kaHfY9cXsQW/tcaE/kQmtdbtoGo2MIYYHqoKvvuz0WUqGmFfAiJd JvYSqd2EnxsVdjsF5demI5+LOOL324CRp1V0mV34ug+OK5XsbSQS0xpNVfqG2itZZrF+ +Cjzw7mvnp6k2/3Qjk6rOEoxUBp/yVCqimiTJzNbPeB6mDKlFtS4NSa+qGDS9fryN2Xx Jm7A== X-Gm-Message-State: AJIora+X+ElLgW3WNtcgVEoM7mUsZC2/usR3KRdSVrNe9B0Jqzw+oxW5 SdeYNG6dM5hxhoTh3wP8c4o= X-Google-Smtp-Source: AGRyM1txLq4Tx5IKJyl2yL+hQwHqEppU3pzgOBeDxgV9FsOmPyXZOlr03TOSB7o38hDoIT4MKowqhA== X-Received: by 2002:a5d:588d:0:b0:218:4d0e:b89 with SMTP id n13-20020a5d588d000000b002184d0e0b89mr24292034wrf.58.1655755634413; Mon, 20 Jun 2022 13:07:14 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id n68-20020a1c2747000000b0039c5a765388sm15705645wmn.28.2022.06.20.13.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:14 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 37/49] extcon: rt8973a: drop useless mask_invert flag on irqchip Date: Mon, 20 Jun 2022 21:06:32 +0100 Message-Id: <20220620200644.1961936-38-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There's no need to set the flag explicitly to false, since that is the default value from zero initialization. Signed-off-by: Aidan MacDonald --- drivers/extcon/extcon-rt8973a.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/extcon/extcon-rt8973a.c b/drivers/extcon/extcon-rt8973a.c index 40c07f4d656e..02ba770acb27 100644 --- a/drivers/extcon/extcon-rt8973a.c +++ b/drivers/extcon/extcon-rt8973a.c @@ -192,7 +192,6 @@ static const struct regmap_irq_chip rt8973a_muic_irq_chip = { .name = "rt8973a", .status_base = RT8973A_REG_INT1, .mask_base = RT8973A_REG_INTM1, - .mask_invert = false, .num_regs = 2, .irqs = rt8973a_irqs, .num_irqs = ARRAY_SIZE(rt8973a_irqs), From patchwork Mon Jun 20 20:06:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5C98C43334 for ; Mon, 20 Jun 2022 20:09:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344584AbiFTUJT (ORCPT ); Mon, 20 Jun 2022 16:09:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344687AbiFTUIi (ORCPT ); Mon, 20 Jun 2022 16:08:38 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E6B521829; Mon, 20 Jun 2022 13:07:27 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id v14so16099319wra.5; Mon, 20 Jun 2022 13:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=drtbL6Ol3nSvJosEWn6BWyNAP++5ZasjbOfmzop3MZQ=; b=QjvV+I2LY/VPVY45eWYJLbt7si9DgUbUdBiK1tnDmgIOAGcJlPEfPEbz0xPv6PFG6C fqwpwN657JaXPxJXBP5AOwcKcjfbM0nFCo3ly+/TCctIcxL8Ez9srZzj3C6ZbVZaRiqz JbpxIf/a/wjakAyd7TsXsc3ArAii392QnIxa2RXb5I35fEt59JdMD+jqhaGkdRCDDnM/ pAKKZGaQWk1j3re/9CnNYt5bHRviVWNWQz6tjo3Kf2EI4KjNuph2+cI7M7xbk0fkDW+c fBjVbekqWUfyD7IfdeqH1QuljKLVCEXC/+72mhEJsa01pPfOg9ygPXXe7cysaPnB7z2q C0NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=drtbL6Ol3nSvJosEWn6BWyNAP++5ZasjbOfmzop3MZQ=; b=5WqnUZTXB1ng2Vx9usv3Kqhf37etv0qY0djhqOVi5EKFsO+d2FGs4VYQjbDo6hxqgw TKMCFxmFk8TQLz+EIu8cYjPfG4oyYOzi6OPm86kLpkp/JLzro2bcWdyw5n/58QzZ85Py MHpXJnf1XxM2pIpFTclWD6OWm+SYaM5UbH8QYvAjIFU3zWE59QlV7/mUIOEvN2V8ctJ7 g9ZNSi6CXtXaethagrGKx9e3Tkcq+VMJNLjzmr3g4Psud4QqPBsqznD41YvspYNh0Y5M N0QOHKhci8LkW4hgd3LuVnmmCjuawF1TvOcVAq27a/vsLOf3lDxSoCFbiKHqr+X+xzxS /o6Q== X-Gm-Message-State: AJIora97VzCDT9OE7PjTKnyW0bjD85uhZ8v8rSK6C5Po1cTM83zX2qbm MVzY/VsZWoOV0mmfj3Qk0ZA= X-Google-Smtp-Source: AGRyM1upACNZTooDfHG9XrmiWJXxBNAesYYQbcORquUwOuEJ3OJEEk57wgHnkZp1ZcThb45MTPunjw== X-Received: by 2002:a05:6000:1788:b0:219:e28f:dc98 with SMTP id e8-20020a056000178800b00219e28fdc98mr24527156wrg.144.1655755639378; Mon, 20 Jun 2022 13:07:19 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id c130-20020a1c3588000000b0039c798b2dc5sm19765399wma.8.2022.06.20.13.07.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:18 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 40/49] mfd: stpmic1: Fix broken mask/unmask in irq chip Date: Mon, 20 Jun 2022 21:06:35 +0100 Message-Id: <20220620200644.1961936-41-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Swap mask_base and unmask_base, and drop the broken_mask_unmask flag since we're now expecting the registers to have their usual behavior. Signed-off-by: Aidan MacDonald --- drivers/mfd/stpmic1.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c index 2307d1b0269d..11f3d92acbc0 100644 --- a/drivers/mfd/stpmic1.c +++ b/drivers/mfd/stpmic1.c @@ -108,9 +108,8 @@ static const struct regmap_irq stpmic1_irqs[] = { static const struct regmap_irq_chip stpmic1_regmap_irq_chip = { .name = "pmic_irq", .status_base = INT_PENDING_R1, - .mask_base = INT_CLEAR_MASK_R1, - .unmask_base = INT_SET_MASK_R1, - .broken_mask_unmask = true, + .mask_base = INT_SET_MASK_R1, + .unmask_base = INT_CLEAR_MASK_R1, .ack_base = INT_CLEAR_R1, .num_regs = STPMIC1_PMIC_NUM_IRQ_REGS, .irqs = stpmic1_irqs, From patchwork Mon Jun 20 20:06:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9535ECCA485 for ; Mon, 20 Jun 2022 20:11:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344311AbiFTULf (ORCPT ); Mon, 20 Jun 2022 16:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344418AbiFTUJI (ORCPT ); Mon, 20 Jun 2022 16:09:08 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A778621E2A; Mon, 20 Jun 2022 13:07:35 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id g27so9434454wrb.10; Mon, 20 Jun 2022 13:07:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rE0XsHvuQMGHkh+DWN4I0u4Mry72SZTz94U/AwkKe64=; b=R2nM9gpViD7RpxZufBEYDf0sqKPJn+Vqc0jUeZDkwV0e+SnITT7LfK/9yzWVU5IQhu aA8WUpzc6J0Qf7iIoRilFZEWo0nV5HsEN4NblRAipOFGBlQ/fSulqH247JQGB+Vbnmz6 u+j2et5Rf+Emw9sgGoIp8Ua1g6/wgIJuStK0XWLJu64d2gAGwoDQCdtaVYypYAWvkfQX jXux0apgjHCpI8qq2XpRhrhdyFsE0YxHMLP8R6wnnvs9dQt5nl7aqrNMv0hrLaXmrugZ kyh9aob6sQAuWXwqPokSAhhl/C8pUOash7nUyLmMzRyTrdLb7ZhEwWLRjTGZ/E7DshAW tGSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rE0XsHvuQMGHkh+DWN4I0u4Mry72SZTz94U/AwkKe64=; b=q/bEHTx3Op31ZBRV/k+Dwc3qGgd/xit2ItPgI42C880l/Dt88ZQLPkTTRQt9wF3VoB OeWe1CLg1CudSqxmXle/rq0ueoDAoA9B7k2TY4EZdE/4ng1VR3TGDN5aEhZqVoZRV4LB CkQVYMKWchkg31TegEkUl0BZsRbO5NFzkCLWhi08EGaRAHDyNMVSj+FEDJf/Bxgq5cWd rbiC78udmTNxJ4AYLgtU+NJWNMznonSJBPOJQ7qNGgor0QXAV+7rzA4AMu38Yahjd7U5 yHH363qHRwvGVppAGXm7S0iCuHfFtcynXFMNheUGnS1tEBlcJ+OcJNrJEYZUCiuP1QO3 Vg6A== X-Gm-Message-State: AJIora/jm0SvaIAdrXIEkfNbzN0Jxq7i4oIdOaITPFeIbEkThtvoO/Ej 3MsWzSfX13m+ZqQSy0fX160= X-Google-Smtp-Source: AGRyM1utPBE8XYxoB7U0xnTciGPQVtQTgTqRZ99c6POU/yfZ+JPXfl21N1f7SnJeHKblgblpcXVNWQ== X-Received: by 2002:a5d:5481:0:b0:21a:3573:def0 with SMTP id h1-20020a5d5481000000b0021a3573def0mr23413256wrv.28.1655755646148; Mon, 20 Jun 2022 13:07:26 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id p14-20020a5d48ce000000b0021020517639sm14095785wrs.102.2022.06.20.13.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:25 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 44/49] regmap-irq: Remove broken_mask_unmask flag Date: Mon, 20 Jun 2022 21:06:39 +0100 Message-Id: <20220620200644.1961936-45-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop broken_mask_unmask flag; no drivers are relying on it anymore. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 9 +-------- include/linux/regmap.h | 1 - 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 082a2981120c..8a718615fd09 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -723,15 +723,8 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, /* * Swap role of mask_base and unmask_base if mask bits are inverted. - * - * Historically, chips that specify both mask_base and unmask_base - * got inverted mask behavior; this was arguably a bug in regmap-irq - * and there was no way to get the normal, non-inverted behavior. - * Those chips will set the broken_mask_unmask flag. They don't set - * mask_invert so there is no need to worry about interactions with - * that flag. */ - if (chip->mask_invert || chip->broken_mask_unmask) { + if (chip->mask_invert) { d->mask_base = chip->unmask_base; d->unmask_base = chip->mask_base; } else { diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 0cf3c4a66946..a3103c88e936 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1524,7 +1524,6 @@ struct regmap_irq_chip { bool clear_on_unmask:1; bool not_fixed_stride:1; bool status_invert:1; - bool broken_mask_unmask:1; int num_regs; From patchwork Mon Jun 20 20:06:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD49DCCA480 for ; Mon, 20 Jun 2022 20:09:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344682AbiFTUJi (ORCPT ); Mon, 20 Jun 2022 16:09:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344741AbiFTUIm (ORCPT ); Mon, 20 Jun 2022 16:08:42 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15EA02183A; Mon, 20 Jun 2022 13:07:29 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id q15so6375291wmj.2; Mon, 20 Jun 2022 13:07:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E0jLkqilWpvnbTcSo4wfjkJhQqF1reP5Ib9ezCHoYWc=; b=U/u1eI8XG0RLSewZC9yH0TEBjAQ2QVQeFgi9rzCUa/S/IXH9PHYw0gdakIKNDT90kV hMuwVJCliXAFt+/OKjfOJGf07gA2TRZWRFVa9nvnR7w8MWysPG76mxgNw9ukyrADHZ5N ALr37IiaH9saP7DoyArHAIbUsX5KFRzx8Uw6meqm+M15MdeUmVUAWTmMi15JWu+Wq07m itZyiVgoqQZkvIT6ra3IIfQvQJZJo5C0Y+CD2t4yxMPenkkULdYZFq6Wwj6TJ4CoenZF dRCH3mEbVAzCd1YjOvUgfQGm1TEKpTWU8WSRmJwdw9G0Be/ybY4XqRUVEJ0I0EIJYNRr FSCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E0jLkqilWpvnbTcSo4wfjkJhQqF1reP5Ib9ezCHoYWc=; b=1Xy+1tjkZ1GV5lQ3g5DPuBw+io2/y9ZSIc3csHyFPVeuwB8XJFyNr0bk8ZokQqWcqa VvD6pPC8zwznOfMxWggTwpc/kV/BXu0hO9jSALm118Espc+HOSUlVbD3bEI7inWuZJfR d6lTYRc36wcXxL1BtNae54LHdyTYJWNTuLucJom3i0Oad55VIh3MeRMJL9uTwQT1+mH0 noEwZ9atXshX1uxArroPJOsd5SVgJCnKYwsmpndP1PsFTrjiLQSDDbZSd41VZ8/E2AZ+ JdaBggyI7jWQrq1OIzHuEaGJRn1XzPuPhztae+rEYBwtPlGLq95HCHhyw1RIuMnWSeeH Ccuw== X-Gm-Message-State: AJIora+O9GpFtnQAQUSgoNUf39qKFl0p2sbc44E2ep9dcr2qe0ypkRQg Uzwk7M5Jt6OVTmAwWtu1heA= X-Google-Smtp-Source: AGRyM1uhXBLM2mCEhpF1oCgYeIG722Adlji+SZHE2C7bZquQV7GS0wP1KfS6UMHZPFYNwRmyV3niBQ== X-Received: by 2002:a05:600c:1c10:b0:39c:4708:648d with SMTP id j16-20020a05600c1c1000b0039c4708648dmr26590108wms.85.1655755649580; Mon, 20 Jun 2022 13:07:29 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id j11-20020a05600c190b00b0039c5328ad92sm22754411wmq.41.2022.06.20.13.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:29 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 46/49] regmap-irq: Refactor checks for status bulk read support Date: Mon, 20 Jun 2022 21:06:41 +0100 Message-Id: <20220620200644.1961936-47-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There are several conditions that must be satisfied to support bulk read of status registers. Move the check into a function to avoid duplicating it in two places. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 0a8edaee064a..7b5bd1d45fc0 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -72,6 +72,14 @@ struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, return &data->chip->irqs[irq]; } +static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data) +{ + struct regmap *map = data->map; + + return !map->use_single_read && map->reg_stride == 1 && + data->irq_reg_stride == 1; +} + static void regmap_irq_lock(struct irq_data *data) { struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); @@ -413,8 +421,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } } - } else if (!map->use_single_read && map->reg_stride == 1 && - data->irq_reg_stride == 1) { + } else if (regmap_irq_can_bulk_read_status(data)) { u8 *buf8 = data->status_reg_buf; u16 *buf16 = data->status_reg_buf; @@ -723,8 +730,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; - if (!map->use_single_read && map->reg_stride == 1 && - d->irq_reg_stride == 1) { + if (regmap_irq_can_bulk_read_status(d)) { d->status_reg_buf = kmalloc_array(chip->num_regs, map->format.val_bytes, GFP_KERNEL); From patchwork Mon Jun 20 20:06:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5921ECCA481 for ; Mon, 20 Jun 2022 20:11:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234157AbiFTULb (ORCPT ); Mon, 20 Jun 2022 16:11:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344186AbiFTUI7 (ORCPT ); Mon, 20 Jun 2022 16:08:59 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2F6C21E0B; Mon, 20 Jun 2022 13:07:31 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id o8so16103423wro.3; Mon, 20 Jun 2022 13:07:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XaILMaaUfjKKrrd1BT5yUC0wzaqueGQvAdQj7TQ0vLM=; b=imip7dzGE8pif//iZiBwRPgT0Zy30AicR52p+YSjODyhTVrRZ2lor3isprtfe5BvRf 6g0qehbR9h2oP87ubh9puaYqDZ7h0g3Qr9cE+rFnZyOveR2FPmH15B6/0Pb9aqj9zL2t 1WdH5LJC+mlljGPaehp7prMgTu/wr2dyHT4f+0DWYEPU53OC4k7EcUfjdBa8Y0jLKd7f jOCRN3c+t45IpipXCIFg8ljs4JDcpiwga1eEgM8TL6lytc62RYsXd2Xi9hxEDHg2Johr jswOtD5N2Zu8rtBWb5ETbrZRPG5UV6rhvYOpjg7uu/p7IFU2L64Kf3biwJJ9dht9BHHs DmLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XaILMaaUfjKKrrd1BT5yUC0wzaqueGQvAdQj7TQ0vLM=; b=1jY2Zm7jWJnct7XK5OoDqT3+6bP2e24S3lCIkBaHJOEkPucZIDqtoMez9KkvMoITVA JkK6S4UmDCj3JwkvhEtP1qJE4y8ZpVGjuvrFmtDoJoTmBCqUOFGngFMLNKMEO8jkHEW1 yfzvoDVtM52VkcaSxKplPPZfay0+quVt/JrH8gI0VA50RLGPhPPrkOtQC0Ic9T7VgBCg DV9SR289GY+qR63qjvhNSH+FCl/Gw6bqUVq/eg3kVe6SuthhtpS5EMhOEBji8ccUBedZ fkvocDDYiZjPbKWpgZUHuXsB0CwEolHJl9IxVMBGLq2h3r7F3qO0aWe8WWg9bj5/bjha SqeQ== X-Gm-Message-State: AJIora8grWWqN41HQmDJ/iJrBKj2twX6iLowN8vHp+3T3mttC2ccU0XO UR17BoXA04bln6+PyCJ+PE0= X-Google-Smtp-Source: AGRyM1t9IFcsSmUxm6NbAdug13RNQx5axNz4NGatMxkirYwyQ+EAH80iv3Me1JZp6GMwiYGFFjPvjg== X-Received: by 2002:a5d:4cc4:0:b0:21b:8a19:b8a6 with SMTP id c4-20020a5d4cc4000000b0021b8a19b8a6mr10152154wrt.590.1655755651340; Mon, 20 Jun 2022 13:07:31 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id e1-20020a5d5941000000b0020c5253d907sm14219807wri.83.2022.06.20.13.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:30 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 47/49] regmap-irq: Add get_irq_reg() callback Date: Mon, 20 Jun 2022 21:06:42 +0100 Message-Id: <20220620200644.1961936-48-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace the internal sub_irq_reg() function with a public callback that drivers can use when they have more complex register layouts. The default implementation is regmap_irq_get_irq_reg_linear(), used if the chip doesn't provide its own callback. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 122 ++++++++++++++++++++----------- include/linux/regmap.h | 15 +++- 2 files changed, 92 insertions(+), 45 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 7b5bd1d45fc0..acbd6e22b0cd 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -41,30 +41,12 @@ struct regmap_irq_chip_data { unsigned int irq_reg_stride; + unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, + unsigned int base, int index); + bool clear_status:1; }; -static int sub_irq_reg(struct regmap_irq_chip_data *data, - unsigned int base_reg, int i) -{ - const struct regmap_irq_chip *chip = data->chip; - struct regmap *map = data->map; - struct regmap_irq_sub_irq_map *subreg; - unsigned int offset; - int reg = 0; - - if (!chip->sub_reg_offsets || !chip->not_fixed_stride) { - /* Assume linear mapping */ - reg = base_reg + (i * map->reg_stride * data->irq_reg_stride); - } else { - subreg = &chip->sub_reg_offsets[i]; - offset = subreg->offset[0]; - reg = base_reg + offset; - } - - return reg; -} - static inline const struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, int irq) @@ -76,8 +58,14 @@ static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data) { struct regmap *map = data->map; + /* + * While possible that a user-defined get_irq_reg callback might be + * linear enough to support bulk reads, most of the time it won't. + * Therefore only allow them if the default callback is being used. + */ return !map->use_single_read && map->reg_stride == 1 && - data->irq_reg_stride == 1; + data->irq_reg_stride == 1 && + data->get_irq_reg == regmap_irq_get_irq_reg_linear; } static void regmap_irq_lock(struct irq_data *data) @@ -114,7 +102,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) if (d->clear_status) { for (i = 0; i < d->chip->num_regs; i++) { - reg = sub_irq_reg(d, d->chip->status_base, i); + reg = d->get_irq_reg(d, d->chip->status_base, i); ret = regmap_read(map, reg, &val); if (ret) @@ -132,7 +120,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) */ for (i = 0; i < d->chip->num_regs; i++) { if (d->chip->mask_base) { - reg = sub_irq_reg(d, d->chip->mask_base, i); + reg = d->get_irq_reg(d, d->chip->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret != 0) @@ -141,7 +129,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } if (d->chip->unmask_base) { - reg = sub_irq_reg(d, d->chip->unmask_base, i); + reg = d->get_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret != 0) @@ -149,7 +137,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg); } - reg = sub_irq_reg(d, d->chip->wake_base, i); + reg = d->get_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { if (d->chip->wake_invert) ret = regmap_update_bits(d->map, reg, @@ -173,7 +161,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) * it'll be ignored in irq handler, then may introduce irq storm */ if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { - reg = sub_irq_reg(d, d->chip->ack_base, i); + reg = d->get_irq_reg(d, d->chip->ack_base, i); /* some chips ack by write 0 */ if (d->chip->ack_invert) @@ -194,7 +182,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) for (i = 0; i < d->chip->num_config_bases; i++) { for (j = 0; j < d->chip->num_config_regs; j++) { - reg = sub_irq_reg(d, d->chip->config_base[i], j); + reg = d->get_irq_reg(d, d->chip->config_base[i], j); ret = regmap_write(map, reg, d->config_buf[i][j]); if (ret != 0) dev_err(d->map->dev, @@ -316,14 +304,17 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, const struct regmap_irq_chip *chip = data->chip; struct regmap *map = data->map; struct regmap_irq_sub_irq_map *subreg; + unsigned int reg; int i, ret = 0; if (!chip->sub_reg_offsets) { - /* Assume linear mapping */ - ret = regmap_read(map, chip->status_base + - (b * map->reg_stride * data->irq_reg_stride), - &data->status_buf[b]); + reg = data->get_irq_reg(data, chip->status_base, b); + ret = regmap_read(map, reg, &data->status_buf[b]); } else { + /* + * Note we can't use get_irq_reg() here because the offsets + * in 'subreg' are *not* interchangeable with indices. + */ subreg = &chip->sub_reg_offsets[b]; for (i = 0; i < subreg->num_regs; i++) { unsigned int offset = subreg->offset[i]; @@ -389,10 +380,19 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) * sake of simplicity. and add bulk reads only if needed */ for (i = 0; i < chip->num_main_regs; i++) { - ret = regmap_read(map, chip->main_status + - (i * map->reg_stride - * data->irq_reg_stride), - &data->main_status_buf[i]); + /* + * For not_fixed_stride, don't use get_irq_reg(). + * It would produce an incorrect result. + */ + if (data->chip->not_fixed_stride) + reg = chip->main_status + + (i * map->reg_stride * + data->irq_reg_stride); + else + reg = data->get_irq_reg(data, + chip->main_status, i); + + ret = regmap_read(map, reg, &data->main_status_buf[i]); if (ret) { dev_err(map->dev, "Failed to read IRQ status %d\n", @@ -457,7 +457,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } else { for (i = 0; i < data->chip->num_regs; i++) { - unsigned int reg = sub_irq_reg(data, + unsigned int reg = data->get_irq_reg(data, data->chip->status_base, i); ret = regmap_read(map, reg, &data->status_buf[i]); @@ -485,7 +485,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) data->status_buf[i] &= ~data->mask_buf[i]; if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { - reg = sub_irq_reg(data, data->chip->ack_base, i); + reg = data->get_irq_reg(data, data->chip->ack_base, i); if (chip->ack_invert) ret = regmap_write(map, reg, @@ -545,6 +545,37 @@ static const struct irq_domain_ops regmap_domain_ops = { .xlate = irq_domain_xlate_onetwocell, }; +/** + * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback. + * + * @data: Data for the &struct regmap_irq_chip + * @base: Base register + * @index: Register index + * + * Returns the register address corresponding to the given @base and @index + * by the formula ``base + index * regmap_stride * irq_reg_stride``. + */ +unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + const struct regmap_irq_chip *chip = data->chip; + struct regmap *map = data->map; + + /* + * NOTE: This is for backward compatibility only and will be removed + * when not_fixed_stride is dropped (it's only used by qcom-pm8008). + */ + if (chip->not_fixed_stride && chip->sub_reg_offsets) { + struct regmap_irq_sub_irq_map *subreg; + + subreg = &chip->sub_reg_offsets[0]; + return base + subreg->offset[0]; + } + + return base + index * (map->reg_stride * chip->irq_reg_stride); +} +EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear); + /** * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. * @@ -730,6 +761,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; + if (chip->get_irq_reg) + d->get_irq_reg = chip->get_irq_reg; + else + d->get_irq_reg = regmap_irq_get_irq_reg_linear; + if (regmap_irq_can_bulk_read_status(d)) { d->status_reg_buf = kmalloc_array(chip->num_regs, map->format.val_bytes, @@ -749,7 +785,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->mask_buf[i] = d->mask_buf_def[i]; if (d->chip->mask_base) { - reg = sub_irq_reg(d, d->chip->mask_base, i); + reg = d->get_irq_reg(d, d->chip->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret != 0) { @@ -760,7 +796,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } if (d->chip->unmask_base) { - reg = sub_irq_reg(d, d->chip->unmask_base, i); + reg = d->get_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret != 0) { @@ -774,7 +810,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, continue; /* Ack masked but set interrupts */ - reg = sub_irq_reg(d, d->chip->status_base, i); + reg = d->get_irq_reg(d, d->chip->status_base, i); ret = regmap_read(map, reg, &d->status_buf[i]); if (ret != 0) { dev_err(map->dev, "Failed to read IRQ status: %d\n", @@ -786,7 +822,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->status_buf[i] = ~d->status_buf[i]; if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { - reg = sub_irq_reg(d, d->chip->ack_base, i); + reg = d->get_irq_reg(d, d->chip->ack_base, i); if (chip->ack_invert) ret = regmap_write(map, reg, ~(d->status_buf[i] & d->mask_buf[i])); @@ -811,7 +847,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, if (d->wake_buf) { for (i = 0; i < chip->num_regs; i++) { d->wake_buf[i] = d->mask_buf_def[i]; - reg = sub_irq_reg(d, d->chip->wake_base, i); + reg = d->get_irq_reg(d, d->chip->wake_base, i); if (chip->wake_invert) ret = regmap_update_bits(d->map, reg, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index bb625a1edef9..be51af0a2425 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1424,6 +1424,8 @@ struct regmap_irq_sub_irq_map { unsigned int *offset; }; +struct regmap_irq_chip_data; + /** * struct regmap_irq_chip - Description of a generic regmap irq_chip. * @@ -1489,6 +1491,13 @@ struct regmap_irq_sub_irq_map { * @handle_post_irq: Driver specific callback to handle interrupt from device * after handling the interrupts in regmap_irq_handler(). * @set_type_config: Callback used for configuring irq types. + * @get_irq_reg: Callback for mapping (base register, index) pairs to register + * addresses. The base register will be one of @status_base, + * @mask_base, etc., @main_status, or any of @config_base. + * The index will be in the range [0, num_main_regs[ for the + * main status base, [0, num_type_settings[ for any config + * register base, and [0, num_regs[ for any other base. + * If unspecified then regmap_irq_get_irq_reg_linear() is used. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. * @@ -1535,11 +1544,13 @@ struct regmap_irq_chip { int (*handle_post_irq)(void *irq_drv_data); int (*set_type_config)(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); + unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, + unsigned int base, int index); void *irq_drv_data; }; -struct regmap_irq_chip_data; - +unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, + unsigned int base, int index); int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); From patchwork Mon Jun 20 20:06:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 583324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E511FC43334 for ; Mon, 20 Jun 2022 20:11:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344328AbiFTULg (ORCPT ); Mon, 20 Jun 2022 16:11:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344570AbiFTUJS (ORCPT ); Mon, 20 Jun 2022 16:09:18 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC012220CB; Mon, 20 Jun 2022 13:07:39 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id o37-20020a05600c512500b0039c4ba4c64dso8276740wms.2; Mon, 20 Jun 2022 13:07:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gGGGI5LNQd5QfFmuY5vVwQrtUD8WBKwvWjL6Bicr/nE=; b=S/EtAgiYih2o97vzKZ46FuXvAcLZH4aZSRqS9u2yBKGwrnkXOKPCMGGLd7i9ZmxQaG BnBbK63aSq4v1vSjGAPc164mZGaSk3LPHtRt8daUl8xMv0xp20Wh0ybrxjQLqHXLqdDy yhDIj9t6XfrHHFv3whu+IVZQrWETjZ1AesrYnf54NJGg7Cy+3sRgTPv9faAKYSFooPY0 45O48rrjzHJTrXu/6XULoJep5LjaBkkIDGdtmMKtfzD41Z5IcTn0ruAikZetXvnqo0Tl Zdz1vCizcAGpaQKPTcGKQxbHlaaCG3L3c003lP0kS60LBM2I8ti3fkUMC/+0uVt3nR1g Y3+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gGGGI5LNQd5QfFmuY5vVwQrtUD8WBKwvWjL6Bicr/nE=; b=V6mYZhraa+r19xr65iPPGyVil2wGL6CdM0InYTMK0U5V0tiQUDLhP3mcWeVHzP1eug VO5SV4J31vdxfBypf5MFWUTo3eTCH92eUZPcdm+OhyWxPeXuqlogzE6Y8P8raTPYEhAd cIZBDldTRIKE2/krY4YVbTPdbMBGZCBUNHl9IGIlJv7PXgW6Lx33vRuznbgHSv9S6s0y oVOl+OEo2+MkIu1t3FMu+UfnvzP4J47inWvj/a/CXKY9VPMQGXc0L4bJR7i+jyh9pZo+ R/PgP8F07msI4UuxO1ed5bLiqpvlNzZMOP7KswxFR9ue+tpgG72YKQxQIBHlGy94tkQH 4uVw== X-Gm-Message-State: AJIora87Bt3QwjtkbXzFR9sHtCOvi4iJTb8Q8SpiqG3Sl2XrRYOIlNe4 3lc2sjbxK1fa38PyBalCY2A= X-Google-Smtp-Source: AGRyM1t7nmjsnyP7qTIA/w/988Wjv4MiUTlTDpMZzgOJTqyM5/Li8wCJHVRxnaV0tBlHxN/JpqOs4g== X-Received: by 2002:a05:600c:4ec7:b0:39c:84a7:3762 with SMTP id g7-20020a05600c4ec700b0039c84a73762mr25749060wmq.153.1655755653087; Mon, 20 Jun 2022 13:07:33 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id s7-20020a5d6a87000000b0021b8c99860asm5606007wru.115.2022.06.20.13.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:32 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 48/49] mfd: qcom-pm8008: Use get_irq_reg() for irq chip Date: Mon, 20 Jun 2022 21:06:43 +0100 Message-Id: <20220620200644.1961936-49-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace the not_fixed_stride flag with a get_irq_reg() callback, which expresses what we want to do here more directly instead of relying on a convoluted hierarchy of offsets. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 56 +++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 31 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index c778f2f87a17..f6407aa0bcfc 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -44,16 +44,6 @@ enum { #define PM8008_GPIO1_ADDR PM8008_PERIPH_2_BASE #define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE -#define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET) -#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET) -#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET) -#define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET) -#define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET) -#define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSET) -#define PM8008_POLARITY_LO_BASE (PM8008_PERIPH_0_BASE | INT_POL_LOW_OFFSET) - -#define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE) - struct pm8008_data { struct device *dev; struct regmap *regmap; @@ -61,22 +51,10 @@ struct pm8008_data { struct regmap_irq_chip_data *irq_data; }; -static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)}; -static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)}; -static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)}; -static unsigned int p3_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_3_BASE)}; - -static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] = { - REGMAP_IRQ_MAIN_REG_OFFSET(p0_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p1_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p2_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs), -}; - static unsigned int pm8008_config_regs[] = { - PM8008_TYPE_BASE, - PM8008_POLARITY_HI_BASE, - PM8008_POLARITY_LO_BASE, + INT_SET_TYPE_OFFSET, + INT_POL_HIGH_OFFSET, + INT_POL_LOW_OFFSET, }; enum { @@ -96,6 +74,23 @@ static struct regmap_irq pm8008_irqs[] = { REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)), }; +static const unsigned int pm8008_periph_base[] = { + PM8008_PERIPH_0_BASE, + PM8008_PERIPH_1_BASE, + PM8008_PERIPH_2_BASE, + PM8008_PERIPH_3_BASE, +}; + +static unsigned int pm8008_get_irq_reg(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + /* Simple linear addressing for the main status register */ + if (base == I2C_INTR_STATUS_BASE) + return base + index; + + return pm8008_periph_base[index] + base; +} + static int pm8008_set_type_config(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx) { @@ -136,17 +131,16 @@ static struct regmap_irq_chip pm8008_irq_chip = { .irqs = pm8008_irqs, .num_irqs = ARRAY_SIZE(pm8008_irqs), .num_regs = PM8008_NUM_PERIPHS, - .not_fixed_stride = true, - .sub_reg_offsets = pm8008_sub_reg_offsets, - .status_base = PM8008_STATUS_BASE, - .mask_base = PM8008_MASK_BASE, - .unmask_base = PM8008_UNMASK_BASE, + .status_base = INT_LATCHED_STS_OFFSET, + .mask_base = INT_EN_CLR_OFFSET, + .unmask_base = INT_EN_SET_OFFSET, .mask_writeonly = true, - .ack_base = PM8008_ACK_BASE, + .ack_base = INT_LATCHED_CLR_OFFSET, .config_base = pm8008_config_regs, .num_config_bases = ARRAY_SIZE(pm8008_config_regs), .num_config_regs = PM8008_NUM_PERIPHS, .set_type_config = pm8008_set_type_config, + .get_irq_reg = pm8008_get_irq_reg, }; static struct regmap_config qcom_mfd_regmap_cfg = {