From patchwork Sat Jun 25 23:25:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0606ACCA47E for ; Sat, 25 Jun 2022 23:25:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233565AbiFYXZW (ORCPT ); Sat, 25 Jun 2022 19:25:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233628AbiFYXZT (ORCPT ); Sat, 25 Jun 2022 19:25:19 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 387F51146E for ; Sat, 25 Jun 2022 16:25:18 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id g4so10476677lfv.9 for ; Sat, 25 Jun 2022 16:25:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=We8zETCg3s+wlW3UWKU0rVY6ytryKW3aFPktzPMnEnU=; b=yE/SGklntMwHucgz4nZ2LdmogceUYZfGPEZizsKT5eEuehbtlumuOUhc3qzp+nUhsF UtwtVz1ptJnYBN8ypsn2InH8xzQ+M/dijR/vL4sZprjAKElyQh/DEobSz6UMEIl7iyAz l4tuWSBuxhYk7DHb8gAAVLyG6LTjiEpr6IapS8I7rTtpyz44h6k2QlrQDRfFjJvDh3i8 eTWGarLO2BTEC33VAKl8NUnyqzmEHPSTzMQV3WyPeGC+uH40taEorsUb40eMiFpB8oru nkRXMI+fFLiEnl+rS47WWMBbFYdxtJ+10YalbKrpaDWjk1hmj/ph1/yyGFEnXn045cge Ai3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=We8zETCg3s+wlW3UWKU0rVY6ytryKW3aFPktzPMnEnU=; b=2zLNdduEz579mzrkcUYwD/wIM3E/0qjjahxdn6qwUP+FZHmcOOrj8gfApweDlAY+m2 KSy1oBM9hz8Z3RLwQd9WLYpoEzhJvJ2/aUG5NqC3PwnAwl+8YTxRopnxHz8xiboZfkUB lynMT4yqFZB/Ufr991rqgdjO2rhRfGGTGtdqVglES/Bn55l9Gfro9wIBXqnp1k1/jZ9M chCXgE4xco6bfbQOgOxdd827jIixPZoCh/q8TF7AnrhcuqlCa1Tyh5pNrl14SWTyBI1P Ebzp0Ax+Bhmzelz/kjs3Hm9WdPpzYzB53vJRXngkkZ86PbTHYg0Mx7Sb1mBl3NaodXgw e2Tg== X-Gm-Message-State: AJIora9w71Gtn+ZVVdWTeBVbtKszP9GbRina8l+kKJcbDQH5T+/aj3xj I4DIAvAFmF0pmBfm7Go5VXPrOg== X-Google-Smtp-Source: AGRyM1tLra7TyfJhvoCVF8F53ffqHZzAxS9vwq9d6puS4k2/N2odYAgJVWceZe9HR4B4tpG9m9iZ/g== X-Received: by 2002:a05:6512:6d4:b0:47f:7940:f70 with SMTP id u20-20020a05651206d400b0047f79400f70mr3559564lff.47.1656199516526; Sat, 25 Jun 2022 16:25:16 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:16 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 01/11] dt-bindings: display/msm: split qcom, mdss bindings Date: Sun, 26 Jun 2022 02:25:03 +0300 Message-Id: <20220625232513.522599-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split Mobile Display SubSystem (MDSS) root node bindings to the separate yaml file. Changes to the existing (txt) schema: - Add optional "vbif_nrt_phys" region used by msm8996 - Make "bus" and "vsync" clocks optional (they are not used by some platforms) - Add (optional) "core" clock added recently to the mdss driver - Add optional resets property referencing MDSS reset - Define child nodes together with compatibles Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/mdp5.txt | 30 +-- .../devicetree/bindings/display/msm/mdss.yaml | 173 ++++++++++++++++++ 2 files changed, 174 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt index 43d11279c925..65d03c58dee6 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt @@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller Description: -This is the bindings documentation for the Mobile Display Subsytem(MDSS) that -encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display +This is the bindings documentation for the MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. -MDSS: -Required properties: -- compatible: - * "qcom,mdss" - MDSS -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdss_phys" - * "vbif_phys" -- interrupts: The interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - * "iface" - * "bus" - * "vsync" -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - MDP5: Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml new file mode 100644 index 000000000000..55c70922361d --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Mobile Display SubSystem (MDSS) dt properties + +maintainers: + - Dmitry Baryshkov + - Rob Clark + +description: | + This is the bindings documentation for the Mobile Display Subsytem(MDSS) that + encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. + +properties: + compatible: + enum: + - qcom,mdss + + reg: + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + + interrupts: + maxItems: 1 + + interrupt-controller: + true + + "#interrupt-cells": + const: 1 + + power-domains: + maxItems: 1 + description: | + The MDSS power domain provided by GCC + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + items: + - const: iface + - const: bus + - const: vsync + - const: core + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + true + + resets: + items: + - description: MDSS_CORE reset + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - "#interrupt-cells" + - power-domains + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^mdp@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,mdp5 + + "^dsi@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,mdss-dsi-ctrl + + "^dsi-phy@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-7nm + - qcom,dsi-phy-7nm-8150 + - qcom,dsi-phy-10nm + - qcom,dsi-phy-10nm-8998 + - qcom,dsi-phy-14nm + - qcom,dsi-phy-14nm-660 + - qcom,dsi-phy-14nm-8953 + - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-8960 + - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-lp + - qcom,sc7280-dsi-phy-7nm + + "^hdmi-phy@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + - qcom,hdmi-phy-8974 + - qcom,hdmi-phy-8084 + - qcom,hdmi-phy-8996 + + "^hdmi-tx@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8660 + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + +additionalProperties: false + +examples: + - | + #include + #include + mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, + <0x1ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + }; +... 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While we are at it, rename display-controller node to mdp to reflect actual node name in the sdm845.dtsi file. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sdm845.yaml | 137 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 112 ++++++++++++-- 2 files changed, 135 insertions(+), 114 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 2bb8896beffc..9253e0ca9fca 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -10,139 +10,74 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SDM845 target. + Device tree bindings for the DPU display controller for SDM845 target. properties: compatible: items: - - const: qcom,sdm845-mdss + - const: qcom,sdm845-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc + - description: Display ahb clock + - description: Display axi clock - description: Display core clock + - description: Display vsync clock clock-names: items: - const: iface + - const: bus - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - resets: - items: - - description: MDSS_CORE reset + power-domains: + maxItems: 1 -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,sdm845-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display ahb clock - - description: Display axi clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 + - port@1 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false @@ -173,7 +108,7 @@ examples: <&apps_smmu 0xc80 0x8>; ranges; - display-controller@ae01000 { + mdp@ae01000 { compatible = "qcom,sdm845-dpu"; reg = <0x0ae01000 0x8f000>, <0x0aeb0000 0x2008>; diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index 55c70922361d..1cfdec9e349b 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -8,6 +8,7 @@ title: Qualcomm Mobile Display SubSystem (MDSS) dt properties maintainers: - Dmitry Baryshkov + - Krishna Manikandan - Rob Clark description: | @@ -17,18 +18,16 @@ description: | properties: compatible: enum: + - qcom,sdm845-mdss - qcom,mdss reg: - minItems: 2 + minItems: 1 maxItems: 3 reg-names: - minItems: 2 - items: - - const: mdss_phys - - const: vbif_phys - - const: vbif_nrt_phys + minItems: 1 + maxItems: 3 interrupts: maxItems: 1 @@ -50,17 +49,13 @@ properties: clock-names: minItems: 1 - items: - - const: iface - - const: bus - - const: vsync - - const: core + maxItems: 4 "#address-cells": - const: 1 + enum: [1, 2] "#size-cells": - const: 1 + enum: [1, 2] ranges: true @@ -69,6 +64,96 @@ properties: items: - description: MDSS_CORE reset + interconnects: + minItems: 2 + items: + - description: MDP port 0 + - description: MDP port 1 + - description: Rotator + + interconnect-names: + minItems: 2 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: rotator-mem + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,mdss + then: + properties: + reg-names: + minItems: 2 + items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + else: + properties: + regs: + maxItems: 1 + + reg-names: + items: + - const: mdss + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + + required: + - iommus + + - if: + properties: + compatible: + contains: + enum: + - qcom,mdss + then: + properties: + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + items: + - const: iface + - const: bus + - const: vsync + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + required: - compatible - reg @@ -90,6 +175,7 @@ patternProperties: compatible: enum: - qcom,mdp5 + - qcom,sdm845-dpu "^dsi@(0|[1-9a-f][0-9a-f]*)$": type: object From patchwork Sat Jun 25 23:25:05 2022 Content-Type: text/plain; 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Sat, 25 Jun 2022 16:25:18 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:18 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 03/11] dt-bindings: display/msm: move qcom, sc7180-mdss schema to mdss.yaml Date: Sun, 26 Jun 2022 02:25:05 +0300 Message-Id: <20220625232513.522599-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move schema for qcom,sc7180-mdss from dpu-sc7180.yaml to mdss.yaml so that the dpu file describes only the DPU schema. While we are at it, rename display-controller node to mdp to reflect actual node name in the sc7180.dtsi file. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sc7180.yaml | 151 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 45 +++++- 2 files changed, 82 insertions(+), 114 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index d3c3e4b07897..f9f22ec56a21 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -10,151 +10,78 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7180 target. + Device tree bindings for the DPU display controller for SC7180 target. properties: compatible: items: - - const: qcom,sc7180-mdss + - const: qcom,sc7180-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc + - description: Display hf axi clock + - description: Display ahb clock + - description: Display rotator clock + - description: Display lut clock - description: Display core clock + - description: Display vsync clock clock-names: items: + - const: bus - const: iface - - const: ahb + - const: rot + - const: lut - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem + power-domains: + maxItems: 1 - resets: - items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,sc7180-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display ahb clock - - description: Display rotator clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: iface - - const: rot - - const: lut - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@2: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF0 (DP) - - required: - - port@0 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF0 (DP) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false @@ -188,7 +115,7 @@ examples: iommus = <&apps_smmu 0x800 0x2>; ranges; - display-controller@ae01000 { + mdp@ae01000 { compatible = "qcom,sc7180-dpu"; reg = <0x0ae01000 0x8f000>, <0x0aeb0000 0x2008>; diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index 1cfdec9e349b..244ec36e74a4 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -18,6 +18,7 @@ description: | properties: compatible: enum: + - qcom,sc7180-mdss - qcom,sdm845-mdss - qcom,mdss @@ -65,20 +66,21 @@ properties: - description: MDSS_CORE reset interconnects: - minItems: 2 + minItems: 1 items: - description: MDP port 0 - description: MDP port 1 - description: Rotator interconnect-names: - minItems: 2 + minItems: 1 items: - const: mdp0-mem - const: mdp1-mem - const: rotator-mem iommus: + minItems: 1 items: - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 @@ -108,9 +110,11 @@ allOf: - const: mdss interconnects: + minItems: 1 maxItems: 2 interconnect-names: + minItems: 1 maxItems: 2 required: @@ -154,6 +158,32 @@ allOf: - const: iface - const: core + iommus: + minItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + required: - compatible - reg @@ -175,8 +205,19 @@ patternProperties: compatible: enum: - qcom,mdp5 + - qcom,sc7180-dpu - qcom,sdm845-dpu + "^displayport-controller@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,sc7180-dp + - qcom,sc7280-dp + - qcom,sc8180x-dp + - qcom,sm8350-dp + "^dsi@(0|[1-9a-f][0-9a-f]*)$": type: object properties: From patchwork Sat Jun 25 23:25:06 2022 Content-Type: text/plain; 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Sat, 25 Jun 2022 16:25:19 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:18 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 04/11] dt-bindings: display/msm: move qcom, sc7280-mdss schema to mdss.yaml Date: Sun, 26 Jun 2022 02:25:06 +0300 Message-Id: <20220625232513.522599-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move schema for qcom,sc7280-mdss from dpu-sc7280.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sc7280.yaml | 148 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 25 +++ 2 files changed, 63 insertions(+), 110 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml index f427eec3d3a4..349a454099ad 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -10,149 +10,77 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7280. + Device tree bindings for the DPU display controller for SC7280 target. properties: compatible: - const: qcom,sc7280-mdss + const: qcom,sc7280-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock - description: Display core clock + - description: Display vsync clock clock-names: items: + - const: bus + - const: nrt_bus - const: iface - - const: ahb + - const: lut - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem + power-domains: + maxItems: 1 - resets: - items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - const: qcom,sc7280-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF5 (EDP) - - required: - - port@0 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF5 (EDP) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index 244ec36e74a4..6221356b3003 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - qcom,sc7180-mdss + - qcom,sc7280-mdss - qcom,sdm845-mdss - qcom,mdss @@ -167,6 +168,7 @@ allOf: contains: enum: - qcom,sc7180-mdss + - qcom,sc7280-mdss then: properties: clocks: @@ -208,6 +210,13 @@ patternProperties: - qcom,sc7180-dpu - qcom,sdm845-dpu + "^display-controller@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,sc7280-dpu + "^displayport-controller@(0|[1-9a-f][0-9a-f]*)$": type: object properties: @@ -243,6 +252,14 @@ patternProperties: - qcom,dsi-phy-28nm-lp - qcom,sc7280-dsi-phy-7nm + "^edp@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,sc7280-edp + - qcom,sc8180x-edp + "^hdmi-phy@(0|[1-9a-f][0-9a-f]*)$": type: object properties: @@ -266,6 +283,14 @@ patternProperties: - qcom,hdmi-tx-8994 - qcom,hdmi-tx-8996 + "^phy@(0|[1-9a-f][0-9a-f]*)$": + type: object + properties: + compatible: + enum: + - qcom,sc7280-dsi-phy-7nm + - qcom,sc7280-edp-phy + additionalProperties: false examples: From patchwork Sat Jun 25 23:25:07 2022 Content-Type: text/plain; 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Sat, 25 Jun 2022 16:25:20 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:19 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 05/11] dt-bindings: display/msm: move qcom, qcm2290-mdss schema to mdss.yaml Date: Sun, 26 Jun 2022 02:25:07 +0300 Message-Id: <20220625232513.522599-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move schema for qcom,qcm2290-mdss from dpu-qcm2290.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-qcm2290.yaml | 140 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 25 ++++ 2 files changed, 58 insertions(+), 107 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index 734d14de966d..8027319b1aad 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -10,146 +10,72 @@ maintainers: - Loic Poulain description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS - and DPU are mentioned for QCM2290 target. + Device tree bindings for the DPU display controller for QCM2290 target. properties: compatible: items: - - const: qcom,qcm2290-mdss + - const: qcom,qcm2290-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AXI clock - - description: Display core clock + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display vsync clock from dispcc clock-names: items: - - const: iface - const: bus + - const: iface - const: core + - const: lut + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem + power-domains: + maxItems: 1 - resets: - items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,qcm2290-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display AXI clock from gcc - - description: Display AHB clock from dispcc - - description: Display core clock from dispcc - - description: Display lut clock from dispcc - - description: Display vsync clock from dispcc - - clock-names: - items: - - const: bus - - const: iface - - const: core - - const: lut - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - required: - - port@0 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index 6221356b3003..c84e0c984e27 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -18,6 +18,7 @@ description: | properties: compatible: enum: + - qcom,qcm2290-mdss - qcom,sc7180-mdss - qcom,sc7280-mdss - qcom,sdm845-mdss @@ -141,6 +142,29 @@ allOf: - const: vsync - const: core + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + minItems: 2 + - if: properties: compatible: @@ -215,6 +239,7 @@ patternProperties: properties: compatible: enum: + - qcom,qcm2290-dpu - qcom,sc7280-dpu "^displayport-controller@(0|[1-9a-f][0-9a-f]*)$": From patchwork Sat Jun 25 23:25:08 2022 Content-Type: text/plain; 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Sat, 25 Jun 2022 16:25:21 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:21 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 06/11] dt-bindings: display/msm: move qcom, msm8998-mdss schema to mdss.yaml Date: Sun, 26 Jun 2022 02:25:08 +0300 Message-Id: <20220625232513.522599-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move schema for qcom,msm8998-mdss from dpu-msm8998.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-msm8998.yaml | 142 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 25 +++ 2 files changed, 65 insertions(+), 102 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 2df64afb76e6..5caf46a1dd88 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -10,142 +10,80 @@ maintainers: - AngeloGioacchino Del Regno description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for MSM8998 target. + Device tree bindings for the DPU display controller for MSM8998 target. properties: compatible: items: - - const: qcom,msm8998-mdss + - const: qcom,msm8998-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for regdma register set + - description: Address offset and size for vbif register set + - description: Address offset and size for non-realtime vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: regdma + - const: vbif + - const: vbif_nrt clocks: items: - - description: Display AHB clock - - description: Display AXI clock + - description: Display ahb clock + - description: Display axi clock + - description: Display mem-noc clock - description: Display core clock + - description: Display vsync clock clock-names: items: - const: iface - const: bus + - const: mnoc - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true + power-domains: + maxItems: 1 -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,msm8998-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for regdma register set - - description: Address offset and size for vbif register set - - description: Address offset and size for non-realtime vbif register set - - reg-names: - items: - - const: mdp - - const: regdma - - const: vbif - - const: vbif_nrt - - clocks: - items: - - description: Display ahb clock - - description: Display axi clock - - description: Display mem-noc clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: mnoc - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 + - port@1 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index c84e0c984e27..cce60d100bb1 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -18,6 +18,7 @@ description: | properties: compatible: enum: + - qcom,msm8998-mdss - qcom,qcm2290-mdss - qcom,sc7180-mdss - qcom,sc7280-mdss @@ -142,6 +143,29 @@ allOf: - const: vsync - const: core + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + - if: properties: compatible: @@ -239,6 +263,7 @@ patternProperties: properties: compatible: enum: + - qcom,msm8998-dpu - qcom,qcm2290-dpu - qcom,sc7280-dpu From patchwork Sat Jun 25 23:25:09 2022 Content-Type: text/plain; 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Sat, 25 Jun 2022 16:25:22 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:22 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 07/11] dt-bindings: display/mdm: add gcc-bus clock to dpu-smd845 Date: Sun, 26 Jun 2022 02:25:09 +0300 Message-Id: <20220625232513.522599-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add gcc-bus clock required for the SDM845 DPU device tree node. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 9253e0ca9fca..0dc16326bf8e 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -29,6 +29,7 @@ properties: clocks: items: + - description: Display GCC bus clock - description: Display ahb clock - description: Display axi clock - description: Display core clock @@ -36,6 +37,7 @@ properties: clock-names: items: + - const: gcc-bus - const: iface - const: bus - const: core From patchwork Sat Jun 25 23:25:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 585644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5020CCCA482 for ; Sat, 25 Jun 2022 23:25:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233675AbiFYXZa (ORCPT ); Sat, 25 Jun 2022 19:25:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233686AbiFYXZ0 (ORCPT ); Sat, 25 Jun 2022 19:25:26 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46CAC12636 for ; Sat, 25 Jun 2022 16:25:25 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id bn8so6830719ljb.2 for ; Sat, 25 Jun 2022 16:25:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sEhrVNP4ho0a6wzg1hnkprZhy63vathkG01hxy93+fM=; b=r+tBaIp3OCvknjpU5NF+TwgdnsAdEC+S/LB7683mI9TdRtWb4hAhq0rlfgzriG4m2G QKIaPDgn9EgR4PmMQxJuuYFMYn8NbR1xvHstmWCCE+L1KnOnh15tgt7QxvZXnGsPYQY3 Rs42BNwARr//kfVoWUf9EdQaQuLuq6GC/vJTNJIP2LY9v+BHlz+YO6dpRmvsjUfiGm6E h3lFuC0VYlPbbEv3HExuJBRCPKuq8AYR3A7gcO1FZ9fWWtOSLG4LXmvWwjZhW3YZ/7n1 HZYZQwCPq9rcLP8etglqfiXk4panH+J+tHhQ6iSrxHWgZCn5r17i5ytLXkxlFxOpc7le T8ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sEhrVNP4ho0a6wzg1hnkprZhy63vathkG01hxy93+fM=; b=PVrPVuBI7TX8Roc8sU99CvKFrMyQeQzPyZeUj0QQoGgMt/V2LnyIiTSlDZHtaPJsDa DOOL9E/tDNnM4FBh5Hct7Ojv8r+DNu27LdXBb7RMbwMKBwxWy1Z/VkCdHN5ec3BVyODp 2XhL9vpbabAAi142pi26MITRr0wyY9xLSk05FMmU1qb/hG0tG2ZpIxfaVIwih/FjP27S dsi3DRpu6dV5g79JRnho/twNzejkzZ1Qs924U2UK9E2Xo6CmajGHUQzK84ytVElgev+D 11am4UwnsGWjLliwGizbNoDNc7jsnVvsmO+xXCwDEiVNd171ptn6E+e/VOEvxflrHPDz 56YA== X-Gm-Message-State: AJIora8YL0VRm2+HzFwfzLMFx5dycV82Ffuz365LoVb1qsNz/INXA0RP 8WwbfGS/tcuNtVk3qAW1gWAlfEZBdHL/aHQo X-Google-Smtp-Source: AGRyM1scWr55DMLw7LMTumP/EB6qyNN54qt7LcCEaF2EEiEPYp2TeJ0HLcQV5tAbVY71hlW4fobTXg== X-Received: by 2002:a2e:bf14:0:b0:255:b789:576b with SMTP id c20-20020a2ebf14000000b00255b789576bmr3141976ljr.47.1656199523688; Sat, 25 Jun 2022 16:25:23 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:23 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 08/11] dt-bindings: display/msm: add mdp-opp-table to dpu-sdm845 Date: Sun, 26 Jun 2022 02:25:10 +0300 Message-Id: <20220625232513.522599-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SDM845 platforms DPU device tree node contains child object mdp-opp-table providing OPP table for the DPU. Add it to the list of properties to let sdm845.dtsi to validate. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dpu-sdm845.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 0dc16326bf8e..cc95adcf8f11 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -50,6 +50,10 @@ properties: maxItems: 1 operating-points-v2: true + + mdp-opp-table: + $ref: /schemas/opp/opp-v2.yaml# + ports: $ref: /schemas/graph.yaml#/properties/ports description: | @@ -116,11 +120,12 @@ examples: <0x0aeb0000 0x2008>; reg-names = "mdp", "vbif"; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; interrupt-parent = <&mdss>; interrupts = <0>; From patchwork Sat Jun 25 23:25:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DF93CCA485 for ; Sat, 25 Jun 2022 23:25:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233682AbiFYXZb (ORCPT ); Sat, 25 Jun 2022 19:25:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233688AbiFYXZ0 (ORCPT ); Sat, 25 Jun 2022 19:25:26 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36B0812608 for ; Sat, 25 Jun 2022 16:25:25 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id s14so6834515ljs.3 for ; Sat, 25 Jun 2022 16:25:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5a0O/lj86Odcfyvh0NdSDgZ9jbHY6A/CPF6H0Yb17DU=; b=yyS+mK6cduXZl+Iio56UbZ9nIzgB7J9VTE5oBCeuG36DrMimAJnDNCcyPNSL6IY9Hi DmIfDi3GCFyTSZFxHzFaY9pg9VUpEPELZlnOI1VHdLepjK/w2Jw2RyOyOUrnKKWQ0Dma N0J1boKXkOHjgy85RO43Vq9zUQ/6GCj1CNSr7hqTmZuHmFCJxxKGIX0/ViE5e8BkZL0s Sasy74vzxwNp47+iP/TUhvMQU7fgZMC7VA+9cx/FxX5+glD/4VDngTwxmd+BqwW/IxNF uX1FTTKOlwq17ruCio29geXApyDSYRUtXfClxF6icvfmWyV/mOlmNindca1mAuK5rcU8 0mFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5a0O/lj86Odcfyvh0NdSDgZ9jbHY6A/CPF6H0Yb17DU=; b=ctpn6TiKJnonhP5ofbVIWhRcdN4iGJZsOLkxNb9j6TWZXNXyw6RzNl4ZttkWUOZvn/ 0FkBQ/C3XZeDgPuXipEZdJD/P3jD0JSthZs0n2vwC38g+7W2I4bXcBpdw9xJGMm3pW5w GQJ5YN+9jdAkc8cb2tPBe7sY0JjEZ2gqynGBeK4mbL41CcxS8nQXdpO/A47IPzxjnkCy pz0gv7C2T9AwdCQIr1+vqzVJ49wC3LN/zVjZfOeG5SUQ9ctcRuIy56WebNWIzljmnV+p xa5xb0FmlGKvH9EbY/Jn1EQP0wBX5Jz5KqCVUIhqvj6bCJ8dEwYuKIBZKQ5ljLRRWuTV fTOA== X-Gm-Message-State: AJIora+IwWzAEZExzKFdWQ/TVfnqVc1QxUWoWq9+T0zVfyN8pBv08U9q kPykNz1Mn7ZTCX8WKYrOk37CIA== X-Google-Smtp-Source: AGRyM1t6fjYd7x9i+9ve9cC+C7UdG5/nZz5n8gJgxMQwmJE8Hg2DzAUEOn+9issMRrXYXdqKdaf/DQ== X-Received: by 2002:a05:651c:b09:b0:25a:44fd:41f with SMTP id b9-20020a05651c0b0900b0025a44fd041fmr3183870ljr.366.1656199524796; Sat, 25 Jun 2022 16:25:24 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:23 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 09/11] dt-bindings: display/msm: add mdp-opp-table to dpu-sc7180 Date: Sun, 26 Jun 2022 02:25:11 +0300 Message-Id: <20220625232513.522599-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sc7180 platforms DPU device tree node contains child object mdp-opp-table providing OPP table for the DPU. Add it to the list of properties to let sc7180.dtsi to validate. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index f9f22ec56a21..42921f25baa4 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -53,6 +53,9 @@ properties: operating-points-v2: true + mdp-opp-table: + $ref: /schemas/opp/opp-v2.yaml# + ports: $ref: /schemas/graph.yaml#/properties/ports description: | From patchwork Sat Jun 25 23:25:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 585642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00958CCA481 for ; Sat, 25 Jun 2022 23:25:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233683AbiFYXZc (ORCPT ); Sat, 25 Jun 2022 19:25:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233660AbiFYXZ3 (ORCPT ); Sat, 25 Jun 2022 19:25:29 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A9FF10FC2 for ; Sat, 25 Jun 2022 16:25:27 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id x3so10548536lfd.2 for ; Sat, 25 Jun 2022 16:25:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gWoCshJx0eeQE7NK0wwwD4EVL2o2EaUzdaBgH0PNhgU=; b=xiIlYQAOx+RgUAtiTCwtujWmIyV74Mji6guPVZQ+UInM7d8t7OvmG8yJeSrPNcAl5/ 9Bn4FVzxZCgHY8VGLwQkH2Wmf3Hpr4SQlWFNYDADUxsC7nyOonKnPejvWwgdjLyanzyx XCKQ1t7dLvzEMTJ6o7CM27in+0tnofafgwJb5GormAof6lQX1dXuh/jMTMQxX0uZI2L3 qzAWsGdEmUhWm8aqNTTOjjXTCk4/qQF30zfoPGdncCuRVSw4jDml9UMMqnSoTDiEsGpb Yr9WevejJcPE3yg6oM7/hLI1ktqTQs0KyltPB+cJT6dMghI+KXolhOicavWSsKZocltj 7zpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gWoCshJx0eeQE7NK0wwwD4EVL2o2EaUzdaBgH0PNhgU=; b=qiT3UgARn+iOVQdrWxgdqq13WynOLAPZXy0E0pXRxDf2DZCsLPvoICM/CpOGZwo0lK 90qjwE+zdR4tq1iEJTaqhNd24w+lBFIafJeEHJQaGThN2Zkr+hpHbArqTzp5dVreRHzh F82jc/ge3ygnIRtjkqCvbTthMKs9VF9JxLR4gXvrXlCODQyWR7gWEIURdc45aOneT+Uw DYPEqJq6Lgdpg+26qZhwGV98KUkuly3V7gJoDdKQGQNZhP2An7JJ3p/nCb6dqEZvX3I4 mMiQvFrPoy2BR78XjOo9vB9XusT7mDWwEXctiFa+caT5guNKs80Pany4CIgsh1bBTgX9 9XxQ== X-Gm-Message-State: AJIora97CkffmAUbUH/z4TYprCnVAhGxpTHF3Wg9ewnTWT0h2p+9lpwM dQkA5pBez6Y6mVV9Wtbc7pEqpQ== X-Google-Smtp-Source: AGRyM1uBQymWy56WzAi98/GXSYCFD92Wwdpc+HEM+cxh8zQxjZCvbxqmM9XWuImdkH+dosLTGIxjyA== X-Received: by 2002:a05:6512:114d:b0:481:1332:c83f with SMTP id m13-20020a056512114d00b004811332c83fmr335281lfg.205.1656199525732; Sat, 25 Jun 2022 16:25:25 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s8-20020a056512202800b0047f750ecd8csm1093694lfs.67.2022.06.25.16.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 16:25:25 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 10/11] dt-bindings: display/msm: add opp-table to dpu-sc7280 Date: Sun, 26 Jun 2022 02:25:12 +0300 Message-Id: <20220625232513.522599-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sc7280 platforms DPU device tree node contains child object opp-table providing OPP table for the DPU. Add it to the list of properties to let sc7280.dtsi to validate. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring --- Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml index 349a454099ad..49c4a055d20f 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -52,6 +52,9 @@ properties: operating-points-v2: true + opp-table: + $ref: /schemas/opp/opp-v2.yaml# + ports: $ref: /schemas/graph.yaml#/properties/ports description: | From patchwork Sat Jun 25 23:25:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32FDCC43334 for ; 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Sat, 25 Jun 2022 16:25:26 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krishna Manikandan , AngeloGioacchino Del Regno Subject: [PATCH 11/11] dt-bindings: display/msm: move common DPU properties to dpu-common.yaml Date: Sun, 26 Jun 2022 02:25:13 +0300 Message-Id: <20220625232513.522599-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> References: <20220625232513.522599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move properties common to all DPU DT nodes to the dpu-common.yaml Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-common.yaml | 47 +++++++++++++++++++ .../bindings/display/msm/dpu-msm8998.yaml | 28 ++--------- .../bindings/display/msm/dpu-qcm2290.yaml | 29 ++---------- .../bindings/display/msm/dpu-sc7180.yaml | 32 ++----------- .../bindings/display/msm/dpu-sc7280.yaml | 32 ++----------- .../bindings/display/msm/dpu-sdm845.yaml | 32 ++----------- 6 files changed, 67 insertions(+), 133 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-common.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml new file mode 100644 index 000000000000..f3465ee3a4ab --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml @@ -0,0 +1,47 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties (common properties) + +maintainers: + - Dmitry Baryshkov + - Krishna Manikandan + - Rob Clark + +description: | + Device tree bindings for the DPU display controller, common properties. + +properties: + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + +patternProperties: + (mdp-)?opp-table: + $ref: /schemas/opp/opp-v2.yaml# + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 5caf46a1dd88..2207601c83df 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -47,21 +47,8 @@ properties: - const: core - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true ports: $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - properties: port@0: $ref: /schemas/graph.yaml#/properties/port @@ -75,17 +62,10 @@ properties: - port@0 - port@1 -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index 8027319b1aad..8a0d6eda6e7c 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -43,22 +43,8 @@ properties: - const: lut - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI. Each output port contains an endpoint that - describes how it is connected to an external interface. - properties: port@0: $ref: /schemas/graph.yaml#/properties/port @@ -67,17 +53,10 @@ properties: required: - port@0 -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index 42921f25baa4..1047192b5b36 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -45,25 +45,8 @@ properties: - const: core - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - mdp-opp-table: - $ref: /schemas/opp/opp-v2.yaml# - ports: $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - properties: port@0: $ref: /schemas/graph.yaml#/properties/port @@ -76,17 +59,10 @@ properties: required: - port@0 -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml index 49c4a055d20f..543d90a84853 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -44,25 +44,8 @@ properties: - const: core - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - opp-table: - $ref: /schemas/opp/opp-v2.yaml# - ports: $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - properties: port@0: $ref: /schemas/graph.yaml#/properties/port @@ -75,17 +58,10 @@ properties: required: - port@0 -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index cc95adcf8f11..796c13d73ea3 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -43,25 +43,8 @@ properties: - const: core - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - mdp-opp-table: - $ref: /schemas/opp/opp-v2.yaml# - ports: $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - properties: port@0: $ref: /schemas/graph.yaml#/properties/port @@ -75,17 +58,10 @@ properties: - port@0 - port@1 -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - |