From patchwork Sun Jun 26 02:11:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 585219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC048C433EF for ; Sun, 26 Jun 2022 02:11:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233800AbiFZCL5 (ORCPT ); Sat, 25 Jun 2022 22:11:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233617AbiFZCL4 (ORCPT ); Sat, 25 Jun 2022 22:11:56 -0400 Received: from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com [64.147.123.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35B1313E85; Sat, 25 Jun 2022 19:11:56 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 90DC432008FD; Sat, 25 Jun 2022 22:11:54 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Sat, 25 Jun 2022 22:11:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm3; t=1656209514; x=1656295914; bh=wy eR3lxXOmCAQeS8Gi1vPaFAP1UPTolRFL1liomH1uY=; b=UMRYy2VZTfJXilwIFX yXRA+QsmMl+TpKJZvAL/jt6lF6b2R96RXr4NW21RZT7dJCRPxiXmUuSUrbea8mMc qJfGRl7brmjm2IJ2oQNpCYqG5wu+kLzpY5GCCR0GX9P5YwIy3mHe3tsjky1gGvTM MS7Y9kQ57fH6LyikbdPWZC01AWovdwtIJsPAqhpy9fqEZ+a+nEe9YTFMLDB6MnMi jo76U63erM+QPAUr4kEGXqYFY9wRnncTQD73j5OmZfNcHBcdfcywibVHB7XwEk7x D6bTGjY5HGUVahcPit/BH8SmQ6F+GgNyibsACVEg/Yx3CpMrmuYBCJp3lXNBcHVk 3y0A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; t=1656209514; x=1656295914; bh=wyeR3lxXOmCAQ eS8Gi1vPaFAP1UPTolRFL1liomH1uY=; b=tZr2yA54Oo+Gvr0yxaoyy9Re09KuI 06XV/Z6CCc8+VGRfg48y21eGZzZcpDxNiNK4swBTeiA+smgxgZoZdrG81JscVu4t hR5+gJgkUW5u3auoiEqt7yp/Z/4SOTziUYPX3xH4buiSn0TqrQuhJrFOQcM5nkzP BVL+goApqpRho5WVvzsLeeS4he6GYx3QCEXlHvLfg3IYbMxmYYIsM82N2HgZJW4K RGNAAzevFowaN4apvqlmK84YCg0sRnYnJq1gesMZ2+k6ykHulA05p3NhZjCmPNdm g/WUb5JOO6CYfNyu9cauG5LIaLyiAxd/LsbeW4NRjN0nmj9PVYNArtxiw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrudegvddgheehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 25 Jun 2022 22:11:52 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Linus Walleij Cc: Samuel Holland , Krzysztof Kozlowski , Maxime Ripard , Ondrej Jirman , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 1/6] dt-bindings: pinctrl: Add compatibles for Allwinner D1/D1s Date: Sat, 25 Jun 2022 21:11:42 -0500 Message-Id: <20220626021148.56740-2-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220626021148.56740-1-samuel@sholland.org> References: <20220626021148.56740-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org D1 contains a pin controller similar to previous SoCs, but with some register layout changes. It includes 6 interrupt-capable pin banks. D1s is a low pin count version of the D1 SoC, with some pins omitted. The remaining pins have the same function assignments as D1. Signed-off-by: Samuel Holland Tested-by: Heiko Stuebner --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index bfce850c2035..3da52814f151 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -46,6 +46,8 @@ properties: - allwinner,sun8i-v3s-pinctrl - allwinner,sun9i-a80-pinctrl - allwinner,sun9i-a80-r-pinctrl + - allwinner,sun20i-d1-pinctrl + - allwinner,sun20i-d1s-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-a64-r-pinctrl - allwinner,sun50i-a100-pinctrl @@ -171,6 +173,19 @@ allOf: minItems: 7 maxItems: 7 + - if: + properties: + compatible: + enum: + - allwinner,sun20i-d1-pinctrl + - allwinner,sun20i-d1s-pinctrl + + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + - if: properties: compatible: From patchwork Sun Jun 26 02:11:44 2022 Content-Type: text/plain; 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Sat, 25 Jun 2022 22:11:59 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Linus Walleij Cc: Samuel Holland , Krzysztof Kozlowski , Maxime Ripard , Ondrej Jirman , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 3/6] pinctrl: sunxi: Support the 2.5V I/O bias mode Date: Sat, 25 Jun 2022 21:11:44 -0500 Message-Id: <20220626021148.56740-4-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220626021148.56740-1-samuel@sholland.org> References: <20220626021148.56740-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the 1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level and disabling the "withstand function". H616 supports this capability on its main PIO only. A100 supports this capability on both its PIO and R-PIO. Signed-off-by: Samuel Holland Tested-by: Heiko Stuebner Reviewed-by: Jernej Skrabec --- drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 10 ++++++++++ drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 +++++++ 5 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c index 21054fcacd34..afc1f5df7545 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c @@ -82,6 +82,7 @@ static const struct sunxi_pinctrl_desc a100_r_pinctrl_data = { .npins = ARRAY_SIZE(a100_r_pins), .pin_base = PL_BASE, .irq_banks = 1, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL, }; static int a100_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c index e69f6da40dc0..f682e0e4244d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -684,7 +684,7 @@ static const struct sunxi_pinctrl_desc a100_pinctrl_data = { .npins = ARRAY_SIZE(a100_pins), .irq_banks = 7, .irq_bank_map = a100_irq_bank_map, - .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL, }; static int a100_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c index 152b71226a80..d6ca720ee8d8 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c @@ -525,7 +525,7 @@ static const struct sunxi_pinctrl_desc h616_pinctrl_data = { .irq_banks = ARRAY_SIZE(h616_irq_bank_map), .irq_bank_map = h616_irq_bank_map, .irq_read_needs_mux = true, - .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL, }; static int h616_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 3c5e71359ca8..eb3d595f816a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -662,6 +662,16 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, reg &= ~IO_BIAS_MASK; writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); return 0; + case BIAS_VOLTAGE_PIO_POW_MODE_CTL: + val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0; + + raw_spin_lock_irqsave(&pctl->lock, flags); + reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG); + reg &= ~BIT(bank); + writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG); + raw_spin_unlock_irqrestore(&pctl->lock, flags); + + fallthrough; case BIAS_VOLTAGE_PIO_POW_MODE_SEL: val = uV <= 1800000 ? 1 : 0; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index a32bb5bcb754..0f1aab58650c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -98,6 +98,7 @@ #define PINCTRL_SUN8I_V3S BIT(10) #define PIO_POW_MOD_SEL_REG 0x340 +#define PIO_POW_MOD_CTL_REG 0x344 enum sunxi_desc_bias_voltage { BIAS_VOLTAGE_NONE, @@ -111,6 +112,12 @@ enum sunxi_desc_bias_voltage { * register, as seen on H6 SoC, for example. */ BIAS_VOLTAGE_PIO_POW_MODE_SEL, + /* + * Bias voltage is set through PIO_POW_MOD_SEL_REG + * and PIO_POW_MOD_CTL_REG register, as seen on + * A100 and D1 SoC, for example. + */ + BIAS_VOLTAGE_PIO_POW_MODE_CTL, }; struct sunxi_desc_function { From patchwork Sun Jun 26 02:11:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 585217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A4B8C433EF for ; Sun, 26 Jun 2022 02:12:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233855AbiFZCMM (ORCPT ); Sat, 25 Jun 2022 22:12:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233779AbiFZCMJ (ORCPT ); Sat, 25 Jun 2022 22:12:09 -0400 Received: from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com [64.147.123.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B91113E8A; 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Sat, 25 Jun 2022 22:12:05 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Linus Walleij Cc: Samuel Holland , Krzysztof Kozlowski , Maxime Ripard , Ondrej Jirman , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 5/6] pinctrl: sunxi: Make some layout parameters dynamic Date: Sat, 25 Jun 2022 21:11:46 -0500 Message-Id: <20220626021148.56740-6-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220626021148.56740-1-samuel@sholland.org> References: <20220626021148.56740-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. In order to support multiple register layouts, some of the layout parameters need to be set based on the pinctrl variant. This requires passing the pinctrl struct pointer to the register/offset calculation functions. Signed-off-by: Samuel Holland Tested-by: Heiko Stuebner Reviewed-by: Heiko Stuebner Reviewed-by: Jernej Skrabec --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 44 ++++++++++++++++----------- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 ++ 2 files changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 78b7ab69d7a5..ec7daaa5666b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -59,45 +59,49 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip; * The following functions calculate the register and the bit offset to access. * They take a pin number which is relative to the start of the current device. */ -static void sunxi_mux_reg(u32 pin, u32 *reg, u32 *shift, u32 *mask) +static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl, + u32 pin, u32 *reg, u32 *shift, u32 *mask) { u32 bank = pin / PINS_PER_BANK; u32 offset = pin % PINS_PER_BANK * MUX_FIELD_WIDTH; - *reg = bank * BANK_MEM_SIZE + MUX_REGS_OFFSET + + *reg = bank * pctl->bank_mem_size + MUX_REGS_OFFSET + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(MUX_FIELD_WIDTH) - 1) << *shift; } -static void sunxi_data_reg(u32 pin, u32 *reg, u32 *shift, u32 *mask) +static void sunxi_data_reg(const struct sunxi_pinctrl *pctl, + u32 pin, u32 *reg, u32 *shift, u32 *mask) { u32 bank = pin / PINS_PER_BANK; u32 offset = pin % PINS_PER_BANK * DATA_FIELD_WIDTH; - *reg = bank * BANK_MEM_SIZE + DATA_REGS_OFFSET + + *reg = bank * pctl->bank_mem_size + DATA_REGS_OFFSET + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(DATA_FIELD_WIDTH) - 1) << *shift; } -static void sunxi_dlevel_reg(u32 pin, u32 *reg, u32 *shift, u32 *mask) +static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl, + u32 pin, u32 *reg, u32 *shift, u32 *mask) { u32 bank = pin / PINS_PER_BANK; - u32 offset = pin % PINS_PER_BANK * DLEVEL_FIELD_WIDTH; + u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width; - *reg = bank * BANK_MEM_SIZE + DLEVEL_REGS_OFFSET + + *reg = bank * pctl->bank_mem_size + DLEVEL_REGS_OFFSET + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); - *mask = (BIT(DLEVEL_FIELD_WIDTH) - 1) << *shift; + *mask = (BIT(pctl->dlevel_field_width) - 1) << *shift; } -static void sunxi_pull_reg(u32 pin, u32 *reg, u32 *shift, u32 *mask) +static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl, + u32 pin, u32 *reg, u32 *shift, u32 *mask) { u32 bank = pin / PINS_PER_BANK; u32 offset = pin % PINS_PER_BANK * PULL_FIELD_WIDTH; - *reg = bank * BANK_MEM_SIZE + PULL_REGS_OFFSET + + *reg = bank * pctl->bank_mem_size + pctl->pull_regs_offset + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(PULL_FIELD_WIDTH) - 1) << *shift; @@ -508,18 +512,19 @@ static const struct pinctrl_ops sunxi_pctrl_ops = { .get_group_pins = sunxi_pctrl_get_group_pins, }; -static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, +static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl, + u32 pin, enum pin_config_param param, u32 *reg, u32 *shift, u32 *mask) { switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: - sunxi_dlevel_reg(pin, reg, shift, mask); + sunxi_dlevel_reg(pctl, pin, reg, shift, mask); break; case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: case PIN_CONFIG_BIAS_DISABLE: - sunxi_pull_reg(pin, reg, shift, mask); + sunxi_pull_reg(pctl, pin, reg, shift, mask); break; default: @@ -540,7 +545,7 @@ static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, pin -= pctl->desc->pin_base; - ret = sunxi_pconf_reg(pin, param, ®, &shift, &mask); + ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask); if (ret < 0) return ret; @@ -606,7 +611,7 @@ static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); - ret = sunxi_pconf_reg(pin, param, ®, &shift, &mask); + ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask); if (ret < 0) return ret; @@ -774,7 +779,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev, unsigned long flags; pin -= pctl->desc->pin_base; - sunxi_mux_reg(pin, ®, &shift, &mask); + sunxi_mux_reg(pctl, pin, ®, &shift, &mask); raw_spin_lock_irqsave(&pctl->lock, flags); @@ -917,7 +922,7 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) u32 pin = offset + chip->base; u32 reg, shift, mask, val; - sunxi_data_reg(offset, ®, &shift, &mask); + sunxi_data_reg(pctl, offset, ®, &shift, &mask); if (set_mux) sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); @@ -937,7 +942,7 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, u32 reg, shift, mask, val; unsigned long flags; - sunxi_data_reg(offset, ®, &shift, &mask); + sunxi_data_reg(pctl, offset, ®, &shift, &mask); raw_spin_lock_irqsave(&pctl->lock, flags); @@ -1489,6 +1494,9 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, pctl->dev = &pdev->dev; pctl->desc = desc; pctl->variant = variant; + pctl->bank_mem_size = BANK_MEM_SIZE; + pctl->pull_regs_offset = PULL_REGS_OFFSET; + pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH; pctl->irq_array = devm_kcalloc(&pdev->dev, IRQ_PER_BANK * pctl->desc->irq_banks, diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index efaa97457e08..c705828add73 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -169,6 +169,9 @@ struct sunxi_pinctrl { raw_spinlock_t lock; struct pinctrl_dev *pctl_dev; unsigned long variant; + u32 bank_mem_size; + u32 pull_regs_offset; + u32 dlevel_field_width; }; #define SUNXI_PIN(_pin, ...) \