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Wysocki" , Artem Bityutskiy , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jon Kohler Subject: [PATCH] intel_idle: add CPUIDLE_FLAG_IRQ_ENABLE to SPR C1 and C1E Date: Thu, 30 Jun 2022 15:43:09 -0400 Message-Id: <20220630194309.40465-1-jon@nutanix.com> X-Mailer: git-send-email 2.30.1 (Apple Git-130) X-ClientProxiedBy: BYAPR03CA0009.namprd03.prod.outlook.com (2603:10b6:a02:a8::22) To BL0PR02MB4579.namprd02.prod.outlook.com (2603:10b6:208:4b::10) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 604a03ef-b4e9-466d-4847-08da5ad0d495 X-MS-TrafficTypeDiagnostic: SJ0PR02MB7567:EE_ x-proofpoint-crosstenant: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fCyORe5Laq7sIWNZlVCGoFXQsW1tTr/EZVBquhUpcjT+YVLM35bK5ztUb8GkjOXy4ZVUWTrTOU5WHOhATj3ADV9m9NKzt0h10X2H/id5FfALUjNxTIM6hZSmA5f52pJiQgGEi5M8GyWAhrtzJmZbc3TsWLMHETUZTmGSSqm4XWDxK8E/zJRiqIiQZgIVrFqB4sJ28JWXjhnUW9w6yA9QuyxHpe87gtwP/V3/Vz0efzyvRaT5U4+qviyk9X0sBT3C8asiOlUMEV/WIvLxyxVa7BMU18aN3RZNpO5GQP8oSvwMb/CGL3nEYu7BexQkzk9YPQopywfHo0Y+BtGMPBZu6oipQypGBGd/rcePorHVmK/Ei/nqUUf1VWWDxyPWou3s/M0+iRhRXV94N9MV43EWVKzsl4vNuO5dOxauADGD7VTH/9/aGEo6Cvf20fMcJKy2uplS2dwjZ5xVwiGgr4Uim/b42yI5VHTNwUCM4yfcvdDxJHA7qvqLh+3hVqb876+YjepEopYRpyxnlvV49e1zMPceYZuv1v26vcg4TAPRKq2uF+S/Ed9XRNo54+texL+Wgxe9b8lRlfRPOXrlecqOQGBhNEcGwQOEBFzGkB2dYl0PLeQslrlP2F4sJZpq71t+vHjES46Kw+U6V+ASgXNCQ9CzLU15idNLotaZFBg0MvMHfGRt/4nT2Q17UBBV4yCYbw2BZ+R/oic0j7cKqOSg38LNVxTgVFcH8jSYxhjVw3PZRFJ2ioniuqjncmFZD+dE8L6njuc4f/TgtErEmmDMeA== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Note: Enabling this for both C1 and C1E is slightly different than the approach for SKX/ICX, where CPUIDLE_FLAG_IRQ_ENABLE is only enabled on C1; however, given that SPR target/exit latency is 1/1 for c1 and 2/4 for C1E, respectively, which is slower than C1 for SKX, it seems prudent to now enable it on both states. This is also important as on SPR it is possible for only C1 or only C1E to be enabled (i.e. one of them would be disabled), so only enabling C1 would short change C1E-only configurations. Fixes: 9edf3c0ffef0 ("intel_idle: add SPR support") Signed-off-by: Jon Kohler --- drivers/idle/intel_idle.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 424ef470223d..f51857cddf2b 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -893,7 +893,7 @@ static struct cpuidle_state spr_cstates[] __initdata = { { .name = "C1", .desc = "MWAIT 0x00", - .flags = MWAIT2flg(0x00), + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE, .exit_latency = 1, .target_residency = 1, .enter = &intel_idle, @@ -902,7 +902,8 @@ static struct cpuidle_state spr_cstates[] __initdata = { .name = "C1E", .desc = "MWAIT 0x01", .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE | - CPUIDLE_FLAG_UNUSABLE, + CPUIDLE_FLAG_UNUSABLE | + CPUIDLE_FLAG_IRQ_ENABLE, .exit_latency = 2, .target_residency = 4, .enter = &intel_idle,