From patchwork Fri Jul 1 08:20:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 586556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E703ECCA482 for ; Fri, 1 Jul 2022 08:21:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234596AbiGAIVD (ORCPT ); Fri, 1 Jul 2022 04:21:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232650AbiGAIVB (ORCPT ); Fri, 1 Jul 2022 04:21:01 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23C6070E54 for ; Fri, 1 Jul 2022 01:20:59 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id s206so1779295pgs.3 for ; Fri, 01 Jul 2022 01:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xl1HN34mhSotDnvkt8tXbixjNJQAdLGe7tUjPgb4h/M=; b=i7M5+MWQM/Wqyk1fA5iuLZE9bqsbrbc3WDWPOdi3fxmV/AJTwIEE7Si1xPTx5n2Xhn LOSApbAqXS878yYMItr7z4UBSPclNrnv36g5iFVV6jM84cVz4aZ1MCOHvI4E9Lw5JF2u u6SeJygVMbhOGlHlVjNyuv/RcUvYRGwMFWpcpNQJVYbNsAPnd79yR7+c9NJ8IMookw+U MkTEgtPVhXcuZ7cijPlnKYk0euz/zP2qHiPxelFniNIa1bjPNnBOqMx6nTor+cFORIbK HEQ2dTbvlms6brsUkKvwNKNz+C+cX7Ful6WWCTold3g5lPNYADIzEr2fTSm+w6C5shAJ Wrbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xl1HN34mhSotDnvkt8tXbixjNJQAdLGe7tUjPgb4h/M=; b=ycuNQKtnGjvCH6uM+TG6wlK8K1wtUI4zaeSIQLYZ829i5+HFuh8QuOTE08ZGLTw3bN zVLUuEDgAvEYbmNpASDmCb1NOdQebs6YhRVhZjz428GQSlk45n7nfWiqjxsO52C+EbPA hEXCJDq8YAXDqkejLU864Uqz1I9FW+9KIWTaVYWrxXT30X+qc61GkwP87RALUH+YQX6H I/TuVbsqlcOcFJl7TRsA3QLrJ88CApcSWONaQuiCtq06gp5qlTDepJN1sSA0HHyOEzvb PmjGt0SKKQ75EM4vcgeeHPntgSnXchogY14HqHt3FPXNTcCm/3FK9iFoVE/bA1T6AeYG mdpg== X-Gm-Message-State: AJIora8xGtAZ5Isno7Qem6e3qH6sXX7nATRh9GThs+BzpLnWVnUX2uUR fNxGNXFSdwMRcqfpVqzbqJaAFw== X-Google-Smtp-Source: AGRyM1uXWoz/xWc2GMqHOJsNXnU5IHLjBXiEnxQDiL/VVRBiBKY0HSQeRbsyqOL4jGI0ag21bGXGrQ== X-Received: by 2002:a05:6a00:c91:b0:525:8c3f:269 with SMTP id a17-20020a056a000c9100b005258c3f0269mr20249956pfv.66.1656663658830; Fri, 01 Jul 2022 01:20:58 -0700 (PDT) Received: from localhost ([122.172.201.58]) by smtp.gmail.com with ESMTPSA id n1-20020a170902dc8100b00163c6ac211fsm14910383pld.111.2022.07.01.01.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 01:20:58 -0700 (PDT) From: Viresh Kumar To: Ilia Lin , Andy Gross , Bjorn Andersson , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, Vincent Guittot , Stephen Boyd , Nishanth Menon , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 05/30] cpufreq: qcom-nvmem: Migrate to dev_pm_opp_set_config() Date: Fri, 1 Jul 2022 13:50:00 +0530 Message-Id: X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Signed-off-by: Viresh Kumar --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 109 +++++++-------------------- 1 file changed, 28 insertions(+), 81 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 6dfa86971a75..863548f59c3e 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -55,9 +55,7 @@ struct qcom_cpufreq_match_data { }; struct qcom_cpufreq_drv { - struct opp_table **names_opp_tables; - struct opp_table **hw_opp_tables; - struct opp_table **genpd_opp_tables; + int *opp_tokens; u32 versions; const struct qcom_cpufreq_match_data *data; }; @@ -315,72 +313,43 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) } of_node_put(np); - drv->names_opp_tables = kcalloc(num_possible_cpus(), - sizeof(*drv->names_opp_tables), + drv->opp_tokens = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tokens), GFP_KERNEL); - if (!drv->names_opp_tables) { + if (!drv->opp_tokens) { ret = -ENOMEM; goto free_drv; } - drv->hw_opp_tables = kcalloc(num_possible_cpus(), - sizeof(*drv->hw_opp_tables), - GFP_KERNEL); - if (!drv->hw_opp_tables) { - ret = -ENOMEM; - goto free_opp_names; - } - - drv->genpd_opp_tables = kcalloc(num_possible_cpus(), - sizeof(*drv->genpd_opp_tables), - GFP_KERNEL); - if (!drv->genpd_opp_tables) { - ret = -ENOMEM; - goto free_opp; - } for_each_possible_cpu(cpu) { + struct dev_pm_opp_config config = { + .supported_hw = NULL, + }; + cpu_dev = get_cpu_device(cpu); if (NULL == cpu_dev) { ret = -ENODEV; - goto free_genpd_opp; + goto free_opp; } if (drv->data->get_version) { + config.supported_hw = &drv->versions; + config.supported_hw_count = 1; - if (pvs_name) { - drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name( - cpu_dev, - pvs_name); - if (IS_ERR(drv->names_opp_tables[cpu])) { - ret = PTR_ERR(drv->names_opp_tables[cpu]); - dev_err(cpu_dev, "Failed to add OPP name %s\n", - pvs_name); - goto free_opp; - } - } - - drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw( - cpu_dev, &drv->versions, 1); - if (IS_ERR(drv->hw_opp_tables[cpu])) { - ret = PTR_ERR(drv->hw_opp_tables[cpu]); - dev_err(cpu_dev, - "Failed to set supported hardware\n"); - goto free_genpd_opp; - } + if (pvs_name) + config.prop_name = pvs_name; } if (drv->data->genpd_names) { - drv->genpd_opp_tables[cpu] = - dev_pm_opp_attach_genpd(cpu_dev, - drv->data->genpd_names, - NULL); - if (IS_ERR(drv->genpd_opp_tables[cpu])) { - ret = PTR_ERR(drv->genpd_opp_tables[cpu]); - if (ret != -EPROBE_DEFER) - dev_err(cpu_dev, - "Could not attach to pm_domain: %d\n", - ret); - goto free_genpd_opp; + config.genpd_names = drv->data->genpd_names; + config.virt_devs = NULL; + } + + if (config.supported_hw || config.genpd_names) { + drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config); + if (drv->opp_tokens[cpu] < 0) { + ret = drv->opp_tokens[cpu]; + dev_err(cpu_dev, "Failed to set OPP config\n"); + goto free_opp; } } } @@ -395,27 +364,10 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) ret = PTR_ERR(cpufreq_dt_pdev); dev_err(cpu_dev, "Failed to register platform device\n"); -free_genpd_opp: - for_each_possible_cpu(cpu) { - if (IS_ERR(drv->genpd_opp_tables[cpu])) - break; - dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); - } - kfree(drv->genpd_opp_tables); free_opp: - for_each_possible_cpu(cpu) { - if (IS_ERR(drv->names_opp_tables[cpu])) - break; - dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]); - } - for_each_possible_cpu(cpu) { - if (IS_ERR(drv->hw_opp_tables[cpu])) - break; - dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]); - } - kfree(drv->hw_opp_tables); -free_opp_names: - kfree(drv->names_opp_tables); + for_each_possible_cpu(cpu) + dev_pm_opp_clear_config(drv->opp_tokens[cpu]); + kfree(drv->opp_tokens); free_drv: kfree(drv); @@ -429,15 +381,10 @@ static int qcom_cpufreq_remove(struct platform_device *pdev) platform_device_unregister(cpufreq_dt_pdev); - for_each_possible_cpu(cpu) { - dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]); - dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]); - dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); - } + for_each_possible_cpu(cpu) + dev_pm_opp_clear_config(drv->opp_tokens[cpu]); - kfree(drv->names_opp_tables); - kfree(drv->hw_opp_tables); - kfree(drv->genpd_opp_tables); + kfree(drv->opp_tokens); kfree(drv); return 0; From patchwork Fri Jul 1 08:20:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 586361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D198CCA47F for ; Fri, 1 Jul 2022 08:22:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232503AbiGAIWo (ORCPT ); Fri, 1 Jul 2022 04:22:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236285AbiGAIVi (ORCPT ); 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Fri, 01 Jul 2022 01:21:23 -0700 (PDT) From: Viresh Kumar To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul Cc: Viresh Kumar , linux-pm@vger.kernel.org, Vincent Guittot , "Rafael J. Wysocki" , Stephen Boyd , Nishanth Menon , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 14/30] drm/msm: Migrate to dev_pm_opp_set_config() Date: Fri, 1 Jul 2022 13:50:09 +0530 Message-Id: <31b74e43d3af263e1b943bca1dd3debe885521d8.1656660185.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Signed-off-by: Viresh Kumar --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 ++++++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 +++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 +++++- drivers/gpu/drm/msm/dp/dp_ctrl.c | 6 +++++- drivers/gpu/drm/msm/dsi/dsi_host.c | 6 +++++- 5 files changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index c424e9a37669..6ebb5a28c501 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1723,10 +1723,14 @@ static void check_speed_bin(struct device *dev) { struct nvmem_cell *cell; u32 val; + struct dev_pm_opp_config config = { + .supported_hw = &val, + .supported_hw_count = 1, + }; /* * If the OPP table specifies a opp-supported-hw property then we have - * to set something with dev_pm_opp_set_supported_hw() or the table + * to set something with dev_pm_opp_set_config() or the table * doesn't get populated so pick an arbitrary value that should * ensure the default frequencies are selected but not conflict with any * actual bins @@ -1748,7 +1752,7 @@ static void check_speed_bin(struct device *dev) nvmem_cell_put(cell); } - devm_pm_opp_set_supported_hw(dev, &val, 1); + devm_pm_opp_set_config(dev, &config); } struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 42ed9a3c4905..82801311f7d4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1800,6 +1800,10 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) u32 supp_hw = UINT_MAX; u32 speedbin; int ret; + struct dev_pm_opp_config config = { + .supported_hw = &supp_hw, + .supported_hw_count = 1, + }; ret = adreno_read_speedbin(dev, &speedbin); /* @@ -1818,11 +1822,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) supp_hw = fuse_to_supp_hw(dev, rev, speedbin); done: - ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); - if (ret) - return ret; - - return 0; + return devm_pm_opp_set_config(dev, &config); } static const struct adreno_gpu_funcs funcs = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e23e2552e802..2213ce52d2fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1215,12 +1215,16 @@ static int dpu_kms_init(struct drm_device *ddev) struct dev_pm_opp *opp; int ret = 0; unsigned long max_freq = ULONG_MAX; + struct dev_pm_opp_config config = { + .clk_names = (const char *[]){ "core" }, + .clk_count = 1, + }; dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); if (!dpu_kms) return -ENOMEM; - ret = devm_pm_opp_set_clkname(dev, "core"); + ret = devm_pm_opp_set_config(dev, &config); if (ret) return ret; /* OPP table is optional */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index b7f5b8d3bbd6..0c8fc151b4be 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2022,6 +2022,10 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, { struct dp_ctrl_private *ctrl; int ret; + struct dev_pm_opp_config config = { + .clk_names = (const char *[]){ "ctrl_link" }, + .clk_count = 1, + }; if (!dev || !panel || !aux || !link || !catalog) { @@ -2035,7 +2039,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, return ERR_PTR(-ENOMEM); } - ret = devm_pm_opp_set_clkname(dev, "ctrl_link"); + ret = devm_pm_opp_set_config(dev, &config); if (ret) { dev_err(dev, "invalid DP OPP table in device tree\n"); /* caller do PTR_ERR(opp_table) */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index a95d5df52653..35b6722d1cf9 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2034,6 +2034,10 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) struct msm_dsi_host *msm_host = NULL; struct platform_device *pdev = msm_dsi->pdev; int ret; + struct dev_pm_opp_config config = { + .clk_names = (const char *[]){ "byte" }, + .clk_count = 1, + }; msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); if (!msm_host) { @@ -2095,7 +2099,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) goto fail; } - ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); + ret = devm_pm_opp_set_config(&pdev->dev, &config); if (ret) return ret; /* OPP table is optional */ From patchwork Fri Jul 1 08:20:12 2022 Content-Type: text/plain; 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Fri, 01 Jul 2022 01:21:32 -0700 (PDT) Received: from localhost ([122.172.201.58]) by smtp.gmail.com with ESMTPSA id g29-20020aa79f1d000000b0051c4f6d2d95sm15033596pfr.106.2022.07.01.01.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 01:21:32 -0700 (PDT) From: Viresh Kumar To: Stanimir Varbanov , Andy Gross , Bjorn Andersson Cc: Viresh Kumar , linux-pm@vger.kernel.org, Vincent Guittot , "Rafael J. Wysocki" , Stephen Boyd , Nishanth Menon , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 17/30] media: venus: Migrate to dev_pm_opp_set_config() Date: Fri, 1 Jul 2022 13:50:12 +0530 Message-Id: <989d085e6ff7ca6196e7076bba3aad8ac8851b00.1656660185.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Signed-off-by: Viresh Kumar --- drivers/media/platform/qcom/venus/pm_helpers.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index cb48c5ff3dee..f68cc938ebff 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -294,12 +294,16 @@ static int load_scale_v1(struct venus_inst *inst) static int core_get_v1(struct venus_core *core) { int ret; + struct dev_pm_opp_config config = { + .clk_names = (const char *[]){ "core" }, + .clk_count = 1, + }; ret = core_clks_get(core); if (ret) return ret; - ret = devm_pm_opp_set_clkname(core->dev, "core"); + ret = devm_pm_opp_set_config(core->dev, &config); if (ret) return ret; @@ -862,6 +866,10 @@ static int vcodec_domains_get(struct venus_core *core) const struct venus_resources *res = core->res; struct device *pd; unsigned int i; + struct dev_pm_opp_config config = { + .genpd_names = res->opp_pmdomain, + .virt_devs = &opp_virt_dev, + }; if (!res->vcodec_pmdomains_num) goto skip_pmdomains; @@ -879,7 +887,7 @@ static int vcodec_domains_get(struct venus_core *core) return 0; /* Attach the power domain for setting performance state */ - ret = devm_pm_opp_attach_genpd(dev, res->opp_pmdomain, &opp_virt_dev); + ret = devm_pm_opp_set_config(dev, &config); if (ret) goto opp_attach_err; @@ -978,6 +986,10 @@ static int core_get_v4(struct venus_core *core) struct device *dev = core->dev; const struct venus_resources *res = core->res; int ret; + struct dev_pm_opp_config config = { + .clk_names = (const char *[]){ "core" }, + .clk_count = 1, + }; ret = core_clks_get(core); if (ret) @@ -1003,7 +1015,7 @@ static int core_get_v4(struct venus_core *core) if (legacy_binding) return 0; - ret = devm_pm_opp_set_clkname(dev, "core"); + ret = devm_pm_opp_set_config(dev, &config); if (ret) return ret; From patchwork Fri Jul 1 08:20:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 586360 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F72CCCA479 for ; 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Fri, 01 Jul 2022 01:21:37 -0700 (PDT) From: Viresh Kumar To: Andy Gross , Bjorn Andersson , Adrian Hunter , Ulf Hansson Cc: Viresh Kumar , linux-pm@vger.kernel.org, Vincent Guittot , "Rafael J. Wysocki" , Stephen Boyd , Nishanth Menon , linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 19/30] mmc: sdhci-msm: Migrate to dev_pm_opp_set_config() Date: Fri, 1 Jul 2022 13:50:14 +0530 Message-Id: <9c63b2dd7990e8215105774cf977231a841a5a31.1656660185.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Acked-by: Ulf Hansson Signed-off-by: Viresh Kumar --- Ulf, I have kept your Ack as the diff is really small, clk_names is an array now. drivers/mmc/host/sdhci-msm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index e395411fb6fd..a018b45c5a9a 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2559,6 +2559,10 @@ static int sdhci_msm_probe(struct platform_device *pdev) const struct sdhci_msm_offset *msm_offset; const struct sdhci_msm_variant_info *var_info; struct device_node *node = pdev->dev.of_node; + struct dev_pm_opp_config opp_config = { + .clk_names = (const char *[]){ "core" }, + .clk_count = 1, + }; host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); if (IS_ERR(host)) @@ -2631,7 +2635,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) if (ret) goto bus_clk_disable; - ret = devm_pm_opp_set_clkname(&pdev->dev, "core"); + ret = devm_pm_opp_set_config(&pdev->dev, &opp_config); if (ret) goto bus_clk_disable; From patchwork Fri Jul 1 08:20:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 586554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD1C5C433EF for ; Fri, 1 Jul 2022 08:23:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233112AbiGAIXK (ORCPT ); Fri, 1 Jul 2022 04:23:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236366AbiGAIWf (ORCPT ); Fri, 1 Jul 2022 04:22:35 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94ABC72EF6 for ; Fri, 1 Jul 2022 01:21:49 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id e132so1771406pgc.5 for ; Fri, 01 Jul 2022 01:21:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RyxNHb/WQ8LrNXSqNKNJKWjupHwbyKneSV+LOjKKPXE=; b=uOVQ4n4h08T7IuN6KoAE+gQY7eWAHlRu5SCNDJLjFwYc5drt5YI6uQaz8KcufNiKYo ReQ9iDTSUK6OYYym6wlYwFFWXMXQKoYXLa9JzGzdGN4LHUeN2bllMjQZpGGOR0IdPaBT CkMH1PSTSlpDWIM4FG5C8nfWbqI4yKAr9TPy8mQnKY2wwRXaFEUoDegc5dj+8B13E4YE tS1IUkWYhr8gJdRQnSiunLrXqtLhEyhOTNyf/Bv2kdZ/POyi8Rvi3s8EJ6RfPR754XoE IqUMnYlSo+xUHUVmR4/7HTK4HJWHUCfWXWxk4CktXB42mQit+a8gjc2yWOqogvALGr90 4yuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RyxNHb/WQ8LrNXSqNKNJKWjupHwbyKneSV+LOjKKPXE=; b=K2VHdVNa4zSIjm7vmhl1fnco2R8ZddngzOfiRO0dbv9K/yeyOQpgH6t7bgYbbIq+yN 2BQ60TTpn5X/JH1k44rGV0Add8Y31vhr7o7NH0mgogBNWH65cjqiiE6gvkwtXq6CocIw cHlM6YhGDsbHGzWia8yY3QOvCeX8CkzLJi0sl96P3YE611vyL1KO8I4vDvCojmx4Ri/Z VsyrjlwQpEo1LFPJj0XdAv1u5qJanXzL4MTQNabJzXgIRVsCkdhpHtAstoNyTN+iM5HR yJpYHctYoXMHQl01AOSpE5aqizwbMwGJ49lP5Ldk1lRzzMGRIxUlmw6Vc1B35GYJxABX IcPg== X-Gm-Message-State: AJIora/mwgbWRAGtDuLWHFSR7Ro/LKrwGoOsGluVYULyVEy1oVdqdNeF ZSVRJPzJgRX/RtX8qJz0GnYtUw== X-Google-Smtp-Source: AGRyM1uSv2NbtHLEM0xY2pfQz10qfkB5qmBDotngIRAO8ceMzGxHfOY0DUW/Ub5fB+AniWRE/Wqv6w== X-Received: by 2002:a63:7448:0:b0:40c:7d4b:e7c6 with SMTP id e8-20020a637448000000b0040c7d4be7c6mr11292239pgn.140.1656663709116; Fri, 01 Jul 2022 01:21:49 -0700 (PDT) Received: from localhost ([122.172.201.58]) by smtp.gmail.com with ESMTPSA id j4-20020a170902c3c400b00163f5028fd6sm14979185plj.5.2022.07.01.01.21.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 01:21:48 -0700 (PDT) From: Viresh Kumar To: Andy Gross , Bjorn Andersson , Mark Brown Cc: Viresh Kumar , linux-pm@vger.kernel.org, Vincent Guittot , "Rafael J. Wysocki" , Stephen Boyd , Nishanth Menon , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 23/30] spi: qcom: Migrate to dev_pm_opp_set_config() Date: Fri, 1 Jul 2022 13:50:18 +0530 Message-Id: X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Acked-by: Mark Brown Signed-off-by: Viresh Kumar --- Mark, I have kept your Ack as the diff is really small, clk_names is an array now. drivers/spi/spi-geni-qcom.c | 6 +++++- drivers/spi/spi-qcom-qspi.c | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 4e83cc5b445d..428585bae6a8 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -892,6 +892,10 @@ static int spi_geni_probe(struct platform_device *pdev) void __iomem *base; struct clk *clk; struct device *dev = &pdev->dev; + struct dev_pm_opp_config config = { + .clk_names = (const char *[]){ "se" }, + .clk_count = 1, + }; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -922,7 +926,7 @@ static int spi_geni_probe(struct platform_device *pdev) mas->se.base = base; mas->se.clk = clk; - ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); + ret = devm_pm_opp_set_config(&pdev->dev, &config); if (ret) return ret; /* OPP table is optional */ diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index c334dfec4117..7e7732d61b25 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -458,6 +458,10 @@ static int qcom_qspi_probe(struct platform_device *pdev) struct device *dev; struct spi_master *master; struct qcom_qspi *ctrl; + struct dev_pm_opp_config config = { + .clk_names = (const char *[]){ "core" }, + .clk_count = 1, + }; dev = &pdev->dev; @@ -529,7 +533,7 @@ static int qcom_qspi_probe(struct platform_device *pdev) master->handle_err = qcom_qspi_handle_err; master->auto_runtime_pm = true; - ret = devm_pm_opp_set_clkname(&pdev->dev, "core"); + ret = devm_pm_opp_set_config(&pdev->dev, &config); if (ret) return ret; /* OPP table is optional */ From patchwork Fri Jul 1 08:20:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 586359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F08ACCA479 for ; Fri, 1 Jul 2022 08:23:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234894AbiGAIXj (ORCPT ); Fri, 1 Jul 2022 04:23:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236425AbiGAIWi (ORCPT ); Fri, 1 Jul 2022 04:22:38 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 907E873590 for ; Fri, 1 Jul 2022 01:21:52 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id o18so1726987plg.2 for ; Fri, 01 Jul 2022 01:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=noUyypKftE40ROE3MTZpJWzx7cTIt4r0kQzFClbiivU=; b=anUlmuF/xY4AUURsJoVDq8a+6jE3vDG+mIzYb/pfyha56fzt1qv/ljhrQgm9o+bxve Zg0ABJUz/n+zxKw73Awhp/GQGUsZXYw7TDDlWjqgXybkdK0MERUWp/DkHyskqb5XPGe1 /rT6mYQuDi5mQB1f2FwcTxYkYRoe0c8N347t6v6kuxFQiAHypSUnhxg162GHuKs7y1dl jiXER+GymjG9CHTkKUPKi8QGEkoblsvt7ZT3NLr4WCCoDU3eNAsPSvublTsus9S+2cAD mw4DNjfGPTozwMVO1IvEyIq+Wha2nniZQBmxW7pqJJ158/L866DL+fEUU50434hmeVwP rsRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=noUyypKftE40ROE3MTZpJWzx7cTIt4r0kQzFClbiivU=; b=4SxMjL6Kk22+EcI5UCOVHCL6oGDR3u+uWhZGV7CmRBm0ILR7FJ6FEMEaoOr48JBDV/ jeWu8QzD1dOljcRdTwASKZCoPaiSgQ0eG2WhfAqm+nTXn17FRh35oV3q00PgVMbZHavC 8Ey4ZzLpB8SIi42LfBfCEoTQdZYj2ml+9GrjHlYnpuB90J8dUUOOHnnMXRQ+CiopF32/ kCSTlyHAmBeET0qeNU802Kgl+q0sgp8yWp5TTXDDMw1rCYKEMpxiLZHZowcRiph7pqHs n1I1Mb0tCJDC6UlHc+6n+yzTxUWNNwLcd3pmAvSotJW0cctskK+IEMOk5KFGDeYJfFHQ qW9Q== X-Gm-Message-State: AJIora9Ua82FaHmQfSZQXE6KIWqS6nUy/D956fSUpaIENuz3Px9FJrPC XObwciKQsSGQsIAEmSpcKy598A== X-Google-Smtp-Source: AGRyM1vPBHYPyEmnR6pJN+h8oaoYat/QQyCYYbGDGAZ6ThwRx3949kCJYsfczawiYp2t+ZlbH+644w== X-Received: by 2002:a17:90a:f8d2:b0:1ec:b55b:2fdc with SMTP id l18-20020a17090af8d200b001ecb55b2fdcmr15087951pjd.115.1656663712055; Fri, 01 Jul 2022 01:21:52 -0700 (PDT) Received: from localhost ([122.172.201.58]) by smtp.gmail.com with ESMTPSA id y41-20020a056a001ca900b00518d06efbc8sm15099135pfw.98.2022.07.01.01.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 01:21:51 -0700 (PDT) From: Viresh Kumar To: Andy Gross , Bjorn Andersson , Greg Kroah-Hartman , Jiri Slaby Cc: Viresh Kumar , linux-pm@vger.kernel.org, Vincent Guittot , "Rafael J. Wysocki" , Stephen Boyd , Nishanth Menon , linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 24/30] serial: qcom: Migrate to dev_pm_opp_set_config() Date: Fri, 1 Jul 2022 13:50:19 +0530 Message-Id: <1f3328dafaf9e2944fba8ec9e55e3072a63a4192.1656660185.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Signed-off-by: Viresh Kumar --- drivers/tty/serial/qcom_geni_serial.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 4733a233bd0c..ab667838d082 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1347,6 +1347,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) int irq; bool console = false; struct uart_driver *drv; + struct dev_pm_opp_config config = { + .clk_names = (const char *[]){ "se" }, + .clk_count = 1, + }; if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) console = true; @@ -1430,7 +1434,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) port->cts_rts_swap = true; - ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); + ret = devm_pm_opp_set_config(&pdev->dev, &config); if (ret) return ret; /* OPP table is optional */