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Sat, 2 Jul 2022 17:12:43 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.167.123]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Lb8XB2zbRz1Rwnm; Sat, 2 Jul 2022 17:12:42 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis Subject: [PULL v2 02/19] target/riscv: Set env->bins in gen_exception_illegal Date: Sun, 3 Jul 2022 10:12:17 +1000 Message-Id: <20220703001234.439716-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220703001234.439716-1-alistair.francis@opensource.wdc.com> References: <20220703001234.439716-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=176813b30=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson While we set env->bins when unwinding for ILLEGAL_INST, from e.g. csrrw, we weren't setting it for immediately illegal instructions. Add a testcase for mtval via both exception paths. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 2 + tests/tcg/riscv64/Makefile.softmmu-target | 21 +++++++++ tests/tcg/riscv64/issue1060.S | 53 +++++++++++++++++++++++ tests/tcg/riscv64/semihost.ld | 21 +++++++++ 4 files changed, 97 insertions(+) create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target create mode 100644 tests/tcg/riscv64/issue1060.S create mode 100644 tests/tcg/riscv64/semihost.ld diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b151c20674..a10f3f939c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -240,6 +240,8 @@ static void generate_exception_mtval(DisasContext *ctx, int excp) static void gen_exception_illegal(DisasContext *ctx) { + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + offsetof(CPURISCVState, bins)); generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target new file mode 100644 index 0000000000..e22cdb34c5 --- /dev/null +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -0,0 +1,21 @@ +# +# RISC-V system tests +# + +TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64 +VPATH += $(TEST_SRC) + +LINK_SCRIPT = $(TEST_SRC)/semihost.ld +LDFLAGS = -T $(LINK_SCRIPT) +CFLAGS += -g -Og + +%.o: %.S + $(CC) $(CFLAGS) $< -c -o $@ +%: %.o $(LINK_SCRIPT) + $(LD) $(LDFLAGS) $< -o $@ + +QEMU_OPTS += -M virt -display none -semihosting -device loader,file= + +EXTRA_RUNS += run-issue1060 +run-issue1060: issue1060 + $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<) diff --git a/tests/tcg/riscv64/issue1060.S b/tests/tcg/riscv64/issue1060.S new file mode 100644 index 0000000000..17b7fe1be2 --- /dev/null +++ b/tests/tcg/riscv64/issue1060.S @@ -0,0 +1,53 @@ + .option norvc + + .text + .global _start +_start: + lla t0, trap + csrw mtvec, t0 + + # These are all illegal instructions + csrw time, x0 + .insn i CUSTOM_0, 0, x0, x0, 0x321 + csrw time, x0 + .insn i CUSTOM_0, 0, x0, x0, 0x123 + csrw cycle, x0 + + # Success! + li a0, 0 + j _exit + +trap: + # When an instruction traps, compare it to the insn in memory. + csrr t0, mepc + csrr t1, mtval + lwu t2, 0(t0) + bne t1, t2, fail + + # Skip the insn and continue. + addi t0, t0, 4 + csrw mepc, t0 + mret + +fail: + li a0, 1 + +# Exit code in a0 +_exit: + lla a1, semiargs + li t0, 0x20026 # ADP_Stopped_ApplicationExit + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED + + # Semihosting call sequence + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 16 +semiargs: + .space 16 diff --git a/tests/tcg/riscv64/semihost.ld b/tests/tcg/riscv64/semihost.ld new file mode 100644 index 0000000000..a59cc56b28 --- /dev/null +++ b/tests/tcg/riscv64/semihost.ld @@ -0,0 +1,21 @@ +ENTRY(_start) + +SECTIONS +{ + /* virt machine, RAM starts at 2gb */ + . = 0x80000000; + .text : { + *(.text) + } + .rodata : { + *(.rodata) + } + /* align r/w section to next 2mb */ + . = ALIGN(1 << 21); + .data : { + *(.data) + } + .bss : { + *(.bss) + } +} From patchwork Sun Jul 3 00:12:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 586791 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2703044mab; Sat, 2 Jul 2022 17:19:25 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sOoXADdFYlLUhTpeP6CxKt0H3mYv2WR2EzHWuQrQmemHYOzW3hrQOEbrFWOU1ms4MaijJH X-Received: by 2002:a81:909:0:b0:317:684a:3f83 with SMTP id 9-20020a810909000000b00317684a3f83mr25903223ywj.139.1656807565485; Sat, 02 Jul 2022 17:19:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656807565; cv=none; d=google.com; s=arc-20160816; b=M4Wo9T5V3Lxoi8FUR+7knv4Tv/VN9A4bgIJ9uRS+kyhFsvTUNmJ24ktw/f72ntzvG+ Cw3CTmNCQYW1IVhZyQkKPDDY7zXR1TET0DA1MKK9HlEvqWyLRNgI602s4W79KDQtiV8x AqehgGxv4Fv2ohXKMR5MkY91q4PUfdE7T94gsl/mip/xPaSeDNb2ZeTBC8HFHS/QIDHG lKifT/fSisahZ7k6nof3RNgMTVIncHfpyktuCy/gAAj9OCrGxyQs3tSjVvstUzQxoUYp t3etPx2JEDjbdj0rW6UkjHP/6+A7BKBywX3ItmfYksHbkXVn7BJDvLA6HbgTFGqiNvxj Or7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=foxXdZusDryFqwMtXUjdPue7AebkEcQobI56aA4EfhM=; b=B1lzW+LCkJn7r4yVOX/O6VfDGCLTcSc6IFsXEWhf9HWzIKZAyMrC6+skGvbQL26LNB b3ru0firss+mcEsyVjntCiUZej3ABpcym7PZpdJIuMo81WKPm4hNzePJedPfnU36X55R dnTXaaFpFLz4aPnTDag0cjC+aaMoRWW0oxec8xYyB9oRRNA0dkQEuXAJglHs2qnlCYgh 6b4tGl0LQY7rwS80cdKyHHoXCkLFxY1en97sYj/OyQmDkBDeC/4fOIVPTsNNoCiw4z5V gAXaWzOr0HAi8TmyQITACABvpSYEtMC4+yeFHqUF4ICoBPHceFV3xQx0UTWHrIJX5RpH ER9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=H1qVyptc; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b=sflzhH3t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Sat, 2 Jul 2022 17:12:45 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.167.123]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Lb8XD0GRWz1RtVk; Sat, 2 Jul 2022 17:12:43 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis Subject: [PULL v2 03/19] target/riscv: Remove generate_exception_mtval Date: Sun, 3 Jul 2022 10:12:18 +1000 Message-Id: <20220703001234.439716-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220703001234.439716-1-alistair.francis@opensource.wdc.com> References: <20220703001234.439716-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=176813b30=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The function doesn't set mtval, it sets badaddr. Move the set of badaddr directly into gen_exception_inst_addr_mis and use generate_exception. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a10f3f939c..7205a29603 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -230,14 +230,6 @@ static void generate_exception(DisasContext *ctx, int excp) ctx->base.is_jmp = DISAS_NORETURN; } -static void generate_exception_mtval(DisasContext *ctx, int excp) -{ - gen_set_pc_imm(ctx, ctx->base.pc_next); - tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); - gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); - ctx->base.is_jmp = DISAS_NORETURN; -} - static void gen_exception_illegal(DisasContext *ctx) { tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, @@ -247,7 +239,8 @@ static void gen_exception_illegal(DisasContext *ctx) static void gen_exception_inst_addr_mis(DisasContext *ctx) { - generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); + tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); + generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); } static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) From patchwork Sun Jul 3 00:12:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 586789 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2701486mab; Sat, 2 Jul 2022 17:16:40 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sZkpPjlYr7zdY8kFViK6XiBRy2moqQXV56Q1T6cmfbG/IogyIAGBuED2ZP+AWcCPXkRdZ2 X-Received: by 2002:a0d:cb13:0:b0:318:39b9:89fc with SMTP id n19-20020a0dcb13000000b0031839b989fcmr26580819ywd.413.1656807399912; Sat, 02 Jul 2022 17:16:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656807399; cv=none; d=google.com; s=arc-20160816; b=KeK8XencOD+e1WivCErxzowtWpiMKreHq2UO+KB5VW9qtetDE/Ipq1aB8nSkzCSCrT Vaslh63LnMR9iNHSWtDRzfrjxmB5a7ID8LYH15a/0HAJsRBPS26G/vcbvCwqlL26jIGV FlxAZV7mn8sT8bW26aOjAF3Pfr1QHHn3QfQOxPtuQBaXMG3Ubmo326EY4orwWX4MYZa+ bNW6cA4BcgBWR/qeSWNMtFVZDrS1wCbGw5TbZfZ/CbDk5QkZrbLyxjKOVaLHniDX02n7 9ThlWw2HIQE3dZMNfThs8WuxyNFiiQ0piq5Ylqg+8Ta1WMWDPiBI2op2CFe7HpAcYOS8 6wlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=LSFsAoDeoONsgsJfxHokMc3ITKSPM7S2Jw7bcRbBQRM=; b=kZS8SeRBl2AqrZoObhyQjpdwYolOkftapzLiBTUzmHSWT5yd4jEF2INxRX5F+yktou VntIQ5b0+SbN0ipNg8tRnF2KW4sKBVEhklIc6nEj57Paa2zLyZnR4ahv5Jh72Oop+OXr 6DoWGGW8SsYLqhB8iGA1R/BzGTRy2Ti1qdaHeMd86i4EyySCLyt4G4g90DuHQubG2C/M R/4mEYbC/RZMOg249orjW1zxMuwHKjvrOeSWUCNGtZJfTy7GQqMYqsRAAzTyXV8KYepG rmUt6TMorI3wbVVQfs46BjxEJHYqrpl0hGrA6zvppVLUjr8wnKaFw7uM4qVU5K4KSfal RgxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=UlYL7Uce; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b=K2qzhpYi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Sat, 2 Jul 2022 17:12:46 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.167.123]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Lb8XF3wPjz1RwqM; Sat, 2 Jul 2022 17:12:45 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis Subject: [PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc Date: Sun, 3 Jul 2022 10:12:19 +1000 Message-Id: <20220703001234.439716-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220703001234.439716-1-alistair.francis@opensource.wdc.com> References: <20220703001234.439716-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=176813b30=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The set of instructions that require decode_save_opc for unwinding is really fairly small -- only insns that can raise ILLEGAL_INSN at runtime. This includes CSR, anything that uses a *new* fp rounding mode, and many privileged insns. Since unwind info is stored as the difference from the previous insn, storing a 0 for most insns minimizes the size of the unwind info. Booting a debian kernel image to the missing rootfs panic yields - gen code size 22226819/1026886656 + gen code size 21601907/1026886656 on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 18 +++++++++--------- target/riscv/insn_trans/trans_privileged.c.inc | 4 ++++ target/riscv/insn_trans/trans_rvh.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7205a29603..63b04e8a94 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -206,6 +206,13 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } +static void decode_save_opc(DisasContext *ctx) +{ + assert(ctx->insn_start != NULL); + tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); + ctx->insn_start = NULL; +} + static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) { if (get_xl(ctx) == MXL_RV32) { @@ -635,6 +642,8 @@ static void gen_set_rm(DisasContext *ctx, int rm) return; } + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ + decode_save_opc(ctx); gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); } @@ -1013,13 +1022,6 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) /* Include decoders for factored-out extensions */ #include "decode-XVentanaCondOps.c.inc" -static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) -{ - assert(ctx->insn_start != NULL); - tcg_set_insn_start_param(ctx->insn_start, 1, opc); - ctx->insn_start = NULL; -} - static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { /* @@ -1036,7 +1038,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) /* Check for compressed insn */ if (extract16(opcode, 0, 2) != 3) { - decode_save_opc(ctx, opcode); if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { @@ -1051,7 +1052,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) opcode32 = deposit32(opcode32, 16, 16, translator_lduw(env, &ctx->base, ctx->base.pc_next + 2)); - decode_save_opc(ctx, opcode32); ctx->opcode = opcode32; ctx->pc_succ_insn = ctx->base.pc_next + 4; diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 53613682e8..46f96ad74d 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -75,6 +75,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { + decode_save_opc(ctx); gen_helper_sret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; @@ -90,6 +91,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_mret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; @@ -102,6 +104,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_set_pc_imm(ctx, ctx->pc_succ_insn); gen_helper_wfi(cpu_env); return true; @@ -113,6 +116,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_tlb_flush(cpu_env); return true; #endif diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index cebcb3f8f6..4f8aecddc7 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -169,6 +169,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_gvma_tlb_flush(cpu_env); return true; #endif @@ -179,6 +180,7 @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_tlb_flush(cpu_env); return true; #endif diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index c190a59f22..ca8e3d1ea1 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -818,6 +818,8 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) static bool do_csr_post(DisasContext *ctx) { + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ + decode_save_opc(ctx); /* We may have changed important cpu state -- exit to main loop. */ gen_set_pc_imm(ctx, ctx->pc_succ_insn); tcg_gen_exit_tb(NULL, 0);