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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 01/62] accel/tcg: Introduce PageEntryExtra Date: Sun, 3 Jul 2022 13:53:18 +0530 Message-Id: <20220703082419.770989-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add an optional structure, controlled by TARGET_PAGE_ENTRY_EXTRA, that allows arbitrary extra data to be saved in the TLB for a given page. Set it with tlb_set_page_with_extra() and fetch it with probe_access_extra(). Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 5 +++ include/exec/exec-all.h | 26 +++++++++++++-- include/qemu/typedefs.h | 1 + accel/tcg/cputlb.c | 73 ++++++++++++++++++++++++++++++----------- 4 files changed, 84 insertions(+), 21 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..f14586e219 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -76,6 +76,10 @@ typedef uint64_t target_ulong; #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +#ifndef TARGET_PAGE_ENTRY_EXTRA +struct PageEntryExtra { }; +#endif + /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 @@ -148,6 +152,7 @@ typedef struct CPUIOTLBEntry { */ hwaddr addr; MemTxAttrs attrs; + PageEntryExtra extra; } CPUIOTLBEntry; /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 311e5fb422..2c036de3d8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -259,11 +259,12 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, unsigned bits); /** - * tlb_set_page_with_attrs: + * tlb_set_page_with_extra: * @cpu: CPU to add this TLB entry for * @vaddr: virtual address of page to add entry for * @paddr: physical address of the page * @attrs: memory transaction attributes + * @extra: cpu specific extra information * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) * @mmu_idx: MMU index to insert TLB entry for * @size: size of the page in bytes @@ -279,11 +280,25 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, * At most one entry for a given virtual address is permitted. Only a * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only * used by tlb_flush_page. + * + * The @extra information is target-specific, and may be retrieved + * by calling probe_access_extra(). + */ +void tlb_set_page_with_extra(CPUState *cpu, target_ulong vaddr, hwaddr paddr, + MemTxAttrs attrs, PageEntryExtra extra, + int prot, int mmu_idx, target_ulong size); + +/** + * tlb_set_page_with_attrs: + * + * This function is equivalent to calling tlb_set_page_with_extra() + * with an @extra argument of all zeros. */ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, target_ulong size); -/* tlb_set_page: +/** + * tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided @@ -435,6 +450,13 @@ int probe_access_flags(CPUArchState *env, target_ulong addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); +#ifdef CONFIG_SOFTMMU +int probe_access_extra(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, MemTxAttrs *pattrs, + PageEntryExtra *pextra, uintptr_t retaddr); +#endif + #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ /* Estimated block size for TB allocation. */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 42f4ceb701..a4de3bb07c 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -82,6 +82,7 @@ typedef struct NodeInfo NodeInfo; typedef struct NumaNodeMem NumaNodeMem; typedef struct Object Object; typedef struct ObjectClass ObjectClass; +typedef struct PageEntryExtra PageEntryExtra; typedef struct PCIBridge PCIBridge; typedef struct PCIBus PCIBus; typedef struct PCIDevice PCIDevice; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f90f4312ea..05555961c9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1095,16 +1095,21 @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask; } -/* Add a new TLB entry. At most one entry for a given virtual address +/* + * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the * supplied size is only used by tlb_flush_page. * * Called from TCG-generated code, which is under an RCU read-side * critical section. + * + * Returns a pointer to the iotlb entry, with env_tlb(env)->c.lock + * still locked, for final additions to the iotlb entry. The caller + * must unlock the lock. */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_with_extra(CPUState *cpu, target_ulong vaddr, hwaddr paddr, + MemTxAttrs attrs, PageEntryExtra extra, + int prot, int mmu_idx, target_ulong size) { CPUArchState *env = cpu->env_ptr; CPUTLB *tlb = env_tlb(env); @@ -1238,6 +1243,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, */ desc->iotlb[index].addr = iotlb - vaddr_page; desc->iotlb[index].attrs = attrs; + desc->iotlb[index].extra = extra; /* Now calculate the new entry */ tn.addend = addend - vaddr_page; @@ -1272,7 +1278,23 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, qemu_spin_unlock(&tlb->c.lock); } -/* Add a new TLB entry, but without specifying the memory +/* + * Add a new TLB entry, specifying the memory transaction + * attributes to be used. + */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) +{ + PageEntryExtra extra; + + memset(&extra, 0, sizeof(extra)); + tlb_set_page_with_extra(cpu, vaddr, paddr, attrs, extra, + prot, mmu_idx, size); +} + +/* + * Add a new TLB entry, but without specifying the memory * transaction attributes to be used. */ void tlb_set_page(CPUState *cpu, target_ulong vaddr, @@ -1633,25 +1655,38 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, return flags; } +int probe_access_extra(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, MemTxAttrs *pattrs, + PageEntryExtra *pextra, uintptr_t retaddr) +{ + int flags = probe_access_internal(env, addr, 0, access_type, mmu_idx, + nonfault, phost, retaddr); + + if (likely(!(flags & TLB_INVALID_MASK))) { + uintptr_t index = tlb_index(env, mmu_idx, addr); + CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; + + /* Handle clean RAM pages. */ + if (unlikely(flags & TLB_NOTDIRTY)) { + notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + flags &= ~TLB_NOTDIRTY; + } + *pattrs = iotlbentry->attrs; + *pextra = iotlbentry->extra; + } + return flags; +} + int probe_access_flags(CPUArchState *env, target_ulong addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) { - int flags; + MemTxAttrs attrs; + PageEntryExtra extra; - flags = probe_access_internal(env, addr, 0, access_type, mmu_idx, - nonfault, phost, retaddr); - - /* Handle clean RAM pages. */ - if (unlikely(flags & TLB_NOTDIRTY)) { - uintptr_t index = tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; - - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); - flags &= ~TLB_NOTDIRTY; - } - - return flags; + return probe_access_extra(env, addr, access_type, mmu_idx, nonfault, + phost, &attrs, &extra, retaddr); } void *probe_access(CPUArchState *env, target_ulong addr, int size, From patchwork Sun Jul 3 08:23:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586796 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2911749mab; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 02/62] target/arm: Enable PageEntryExtra Date: Sun, 3 Jul 2022 13:53:19 +0530 Message-Id: <20220703082419.770989-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Copy attrs, sharability, and the NS bit into the TLB. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 8 ++++++++ target/arm/internals.h | 5 +++++ target/arm/tlb_helper.c | 14 ++++++++++++-- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb12427..a14f167d11 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -30,6 +30,14 @@ */ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 +/* + * Extra information stored in softmmu page tables. + */ +# define TARGET_PAGE_ENTRY_EXTRA +struct PageEntryExtra { + /* See PAGEENTRYEXTRA fields in cpu.h */ + uint64_t x; +}; #endif #define NB_MMU_MODES 15 diff --git a/target/arm/internals.h b/target/arm/internals.h index c66f74a0db..2b38a83574 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -74,6 +74,11 @@ FIELD(V7M_EXCRET, DCRS, 5, 1) FIELD(V7M_EXCRET, S, 6, 1) FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ +/* Bit definitions for PageEntryExtra */ +FIELD(PAGEENTRYEXTRA, ATTRS, 0, 8) +FIELD(PAGEENTRYEXTRA, SHAREABILITY, 8, 2) +FIELD(PAGEENTRYEXTRA, PA, 12, 52) + /* Minimum value which is a magic number for exception return */ #define EXC_RETURN_MIN_MAGIC 0xff000000 /* Minimum number which is a magic number for function or exception return diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7d8a86b3c4..9de3099153 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -226,21 +226,31 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, &phys_addr, &attrs, &prot, &page_size, &fi, &cacheattrs); if (likely(!ret)) { + PageEntryExtra extra = {}; + /* * Map a single [sub]page. Regions smaller than our declared * target page size are handled specially, so for those we - * pass in the exact addresses. + * pass in the exact addresses. This only happens for M-profile, + * which does not use or require PageEntryExtra. */ if (page_size >= TARGET_PAGE_SIZE) { phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; + + /* Record some particulars for later lookup. */ + extra.x = phys_addr; + extra.x = FIELD_DP64(extra.x, PAGEENTRYEXTRA, ATTRS, + cacheattrs.attrs); + extra.x = FIELD_DP64(extra.x, PAGEENTRYEXTRA, SHAREABILITY, + cacheattrs.shareability); } /* Notice and record tagged memory. */ if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) { arm_tlb_mte_tagged(&attrs) = true; } - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + tlb_set_page_with_extra(cs, address, phys_addr, attrs, extra, prot, mmu_idx, page_size); return true; } else if (probe) { From patchwork Sun Jul 3 08:23:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586801 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2914035mab; Sun, 3 Jul 2022 01:34:04 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tmShDAXvth1bwpFyGrNrREIHOqNkztNJnPQRZapMyKgn5MV9QUXkhOc/3VjguDnHD9nkBj X-Received: by 2002:a05:6902:1027:b0:66d:136e:8f with SMTP id x7-20020a056902102700b0066d136e008fmr24642175ybt.25.1656837244698; Sun, 03 Jul 2022 01:34:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837244; cv=none; d=google.com; s=arc-20160816; b=mI2/bD5ynTRN2fNIwz2KjcaGUY5iPZ7bf2AXM64ESkacQt/7hrEm3Kx3Ek0x6xxzJl amTVipKvsunWYQsoJ1KcXv+fnOah/4m5r86J8uLO+9aX9qrbvtl9lb0kDKeAXME31F3q u2hDJ9Z4BeQwv+Nqwq/so44MuuI8rKpx23fGorSxLfdBlcixEx+0E8L8yHBiVQNiUvlL d2wF2mHBt7drNn4j+JUmAP8Notb1l1ylDh/cqj7GZ/C7AAKX+Uu9U6ZVI71VEugsViwN bv6pHwClGeJmYz72pbuB4C4C+AKW959NaEF2OMs93A/qTD2Kb6FTiP+86By+9GrqMhvk 5ydQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=luVPKzasukavgin4n19Q4taZFn3j+af3jyeUe3XIhz4=; b=XIIiPl0e7Vj9Vc6ygCk0A68S5+RKRZYma27IS4DpZgxPzop4brtcG1Uh4CRY6sM3Uu 3E0ZFQd4wEIlWOnWNXRA14ymXRyWlh2et1R39pWlGWG/ZixYeVIYKxzO6YZwkdlC+6Gm Xe+HrphcDOgAsikcoZabtDLr7Qx8fA256GCHz3JfsTMliip5OB1sGzi5lmyxDAFXTrCj fl7dpSs7CUk57JB+xzaXUCywemFq95bMkMzlXBqJ8ycsj4G98TCzs6b8FpfyktDYjSuU ryiTMpQB2/Kf7+c85XJBsOutOqXZaKiUd0zgwxTTcMH2gr+J/fA/86zG9lBnpeS9qi9z C34Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="C/eAemyz"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 03/62] target/arm: Fix MTE check in sve_ldnfff1_r Date: Sun, 3 Jul 2022 13:53:20 +0530 Message-Id: <20220703082419.770989-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The comment was correct, but the test was not: disable mte if tagged is *not* set. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 1654c0bbf9..db15d03ded 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5986,7 +5986,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, * Disable MTE checking if the Tagged bit is not set. Since TBI must * be set within MTEDESC for MTE, !mtedesc => !mte_active. */ - if (arm_tlb_mte_tagged(&info.page[0].attrs)) { + if (!arm_tlb_mte_tagged(&info.page[0].attrs)) { mtedesc = 0; } From patchwork Sun Jul 3 08:23:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586794 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2910901mab; Sun, 3 Jul 2022 01:26:34 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sVQ1VqNWDUwVVINNIr+eu/Chte9DaMish97oLGCM2jXklwlR6lbLhmqEjWw/x3eFDmzFOv X-Received: by 2002:a05:6902:12c1:b0:669:8f1d:cef2 with SMTP id j1-20020a05690212c100b006698f1dcef2mr25725923ybu.75.1656836794677; Sun, 03 Jul 2022 01:26:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656836794; cv=none; d=google.com; s=arc-20160816; b=wropIYEX+EkTJhfMkwYKYxBVNcRCtdaj7gjnNxShMqXEsaUdyP3V1uJ3IARB5bY2Bk nYAvW3j3IYmJZrQy1FbFedrugz2jqahFN1kJtbUeoY2sxVwl/r+tzTSf+6MEprzOCgTJ tT0tkJ5xJxF2rmLJeh9n8V1D2ybaTFy4MiMudluPwqAxCXk2rzbCr40qEyKTaNpgH/bF 0L/sNjXF3Ibbdpe2jObvY36L8Ntzl5YR9Zu9fWcv78n3Mh9rrM7w6D/B6eQdgu/xD+qL 4RY7sCyVjyYX4N1RsVZoo9kHuA4x6g4cDUkXJRNNfwX2uodDJzTRSR4g7sH7rAELdhOb oC2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OyhgMtHZywg9GRP+8mihPGj8BuF/naRM6gs7r7z8hHQ=; b=JmIu+9d5K6O8yAc6UVjj+1sxoRG16VlybB8amfXqtABnqIin06Iq0rDwfUry8MYHwd sl2V2l4OBxio7T/wG2A9J2lBuLaVEdRpQZMJyD9ufvTZImyG/DNawnijc0j7jiLJtq7G mvcUtb/VGTMYe3zsEj11W50TwQ6JwUBUAodKKLOX4OPiM6iDstaRK5Wug8+b9D8R8klz n7CB6i2MthR6jIW9PGB/nsISEC7u/i3XhK/L8Mc1HsSBD9lwiC6b70R/6CcXfhcusdVc 6BIhOqNgjUjFxsBo4rp6crBE1pVmycnE5EcoBiuUx45bt2mJvfq/0g+QJjKYeT2O3w2E ambQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ZJa/BhCd"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 04/62] target/arm: Record tagged bit for user-only in sve_probe_page Date: Sun, 3 Jul 2022 13:53:21 +0530 Message-Id: <20220703082419.770989-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fixes a bug in that we were not honoring MTE from user-only SVE. Copy the user-only MTE logic from allocation_tag_mem into sve_probe_page. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sve_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index db15d03ded..0c6379e6e8 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5337,6 +5337,9 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, #ifdef CONFIG_USER_ONLY memset(&info->attrs, 0, sizeof(info->attrs)); + /* Require both MAP_ANON and PROT_MTE -- see allocation_tag_mem. */ + arm_tlb_mte_tagged(&info->attrs) = + (flags & PAGE_ANON) && (flags & PAGE_MTE); #else /* * Find the iotlbentry for addr and return the transaction attributes. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 05/62] target/arm: Use PageEntryExtra for MTE Date: Sun, 3 Jul 2022 13:53:22 +0530 Message-Id: <20220703082419.770989-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tagged pages are indicated by the page attributes, so we don't need to use a separate bit in MemTxAttrs. Further, we store the PA, so we don't need to recover it by walking the tree of memory regions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 - target/arm/sve_ldst_internal.h | 1 + target/arm/mte_helper.c | 52 +++++++-------------------------- target/arm/sve_helper.c | 53 +++++++++++----------------------- target/arm/tlb_helper.c | 4 --- 5 files changed, 28 insertions(+), 83 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4a4342f262..a26b9437e9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3369,7 +3369,6 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) * generic target bits directly. */ #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) -#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h index b5c473fc48..4f159ec4ad 100644 --- a/target/arm/sve_ldst_internal.h +++ b/target/arm/sve_ldst_internal.h @@ -134,6 +134,7 @@ typedef struct { void *host; int flags; MemTxAttrs attrs; + bool tagged; } SVEHostPage; bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d11a8c70d0..5327df96d9 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -105,10 +105,9 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); return tags + index; #else - uintptr_t index; - CPUIOTLBEntry *iotlbentry; + MemTxAttrs attrs; + PageEntryExtra extra; int in_page, flags; - ram_addr_t ptr_ra; hwaddr ptr_paddr, tag_paddr, xlat; MemoryRegion *mr; ARMASIdx tag_asi; @@ -124,30 +123,12 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, * valid. Indicate to probe_access_flags no-fault, then assert that * we received a valid page. */ - flags = probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, - ra == 0, &host, ra); + flags = probe_access_extra(env, ptr, ptr_access, ptr_mmu_idx, + ra == 0, &host, &attrs, &extra, ra); assert(!(flags & TLB_INVALID_MASK)); - /* - * Find the iotlbentry for ptr. This *must* be present in the TLB - * because we just found the mapping. - * TODO: Perhaps there should be a cputlb helper that returns a - * matching tlb entry + iotlb entry. - */ - index = tlb_index(env, ptr_mmu_idx, ptr); -# ifdef CONFIG_DEBUG_TCG - { - CPUTLBEntry *entry = tlb_entry(env, ptr_mmu_idx, ptr); - target_ulong comparator = (ptr_access == MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, ptr)); - } -# endif - iotlbentry = &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; - /* If the virtual page MemAttr != Tagged, access unchecked. */ - if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + if (FIELD_EX64(extra.x, PAGEENTRYEXTRA, ATTRS) != 0xf0) { return NULL; } @@ -180,33 +161,20 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, if (unlikely(flags & TLB_WATCHPOINT)) { int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE; assert(ra != 0); - cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, - iotlbentry->attrs, wp, ra); + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra); } - /* - * Find the physical address within the normal mem space. - * The memory region lookup must succeed because TLB_MMIO was - * not set in the cputlb lookup above. - */ - mr = memory_region_from_host(host, &ptr_ra); - tcg_debug_assert(mr != NULL); - tcg_debug_assert(memory_region_is_ram(mr)); - ptr_paddr = ptr_ra; - do { - ptr_paddr += mr->addr; - mr = mr->container; - } while (mr); + /* Recover the physical address from PageEntryExtra. */ + ptr_paddr = extra.x & R_PAGEENTRYEXTRA_PA_MASK; /* Convert to the physical address in tag space. */ tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1); /* Look up the address in tag space. */ - tag_asi = iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_asi = attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; tag_as = cpu_get_address_space(env_cpu(env), tag_asi); mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL, - tag_access == MMU_DATA_STORE, - iotlbentry->attrs); + tag_access == MMU_DATA_STORE, attrs); /* * Note that @mr will never be NULL. If there is nothing in the address diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 0c6379e6e8..4b853a25aa 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5323,8 +5323,18 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, */ addr = useronly_clean_ptr(addr); +#ifdef CONFIG_USER_ONLY flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault, &info->host, retaddr); + memset(&info->attrs, 0, sizeof(info->attrs)); + /* Require both ANON and MTE; see allocation_tag_mem(). */ + info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE); +#else + PageEntryExtra extra; + flags = probe_access_extra(env, addr, access_type, mmu_idx, nofault, + &info->host, &info->attrs, &extra, retaddr); + info->tagged = FIELD_EX64(extra.x, PAGEENTRYEXTRA, ATTRS) == 0xf0; +#endif info->flags = flags; if (flags & TLB_INVALID_MASK) { @@ -5334,33 +5344,6 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, /* Ensure that info->host[] is relative to addr, not addr + mem_off. */ info->host -= mem_off; - -#ifdef CONFIG_USER_ONLY - memset(&info->attrs, 0, sizeof(info->attrs)); - /* Require both MAP_ANON and PROT_MTE -- see allocation_tag_mem. */ - arm_tlb_mte_tagged(&info->attrs) = - (flags & PAGE_ANON) && (flags & PAGE_MTE); -#else - /* - * Find the iotlbentry for addr and return the transaction attributes. - * This *must* be present in the TLB because we just found the mapping. - */ - { - uintptr_t index = tlb_index(env, mmu_idx, addr); - -# ifdef CONFIG_DEBUG_TCG - CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); - target_ulong comparator = (access_type == MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, addr)); -# endif - - CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; - info->attrs = iotlbentry->attrs; - } -#endif - return true; } @@ -5589,7 +5572,7 @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, intptr_t mem_off, reg_off, reg_last; /* Process the page only if MemAttr == Tagged. */ - if (arm_tlb_mte_tagged(&info->page[0].attrs)) { + if (info->page[0].tagged) { mem_off = info->mem_off_first[0]; reg_off = info->reg_off_first[0]; reg_last = info->reg_off_split; @@ -5610,7 +5593,7 @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, } mem_off = info->mem_off_first[1]; - if (mem_off >= 0 && arm_tlb_mte_tagged(&info->page[1].attrs)) { + if (mem_off >= 0 && info->page[1].tagged) { reg_off = info->reg_off_first[1]; reg_last = info->reg_off_last[1]; @@ -5989,7 +5972,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, * Disable MTE checking if the Tagged bit is not set. Since TBI must * be set within MTEDESC for MTE, !mtedesc => !mte_active. */ - if (!arm_tlb_mte_tagged(&info.page[0].attrs)) { + if (!info.page[0].tagged) { mtedesc = 0; } @@ -6540,7 +6523,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, cpu_check_watchpoint(env_cpu(env), addr, msize, info.attrs, BP_MEM_READ, retaddr); } - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } if (unlikely(info.flags & TLB_MMIO)) { @@ -6557,7 +6540,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, msize, info.attrs, BP_MEM_READ, retaddr); } - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } tlb_fn(env, &scratch, reg_off, addr, retaddr); @@ -6758,9 +6741,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, (env_cpu(env), addr, msize) & BP_MEM_READ)) { goto fault; } - if (mtedesc && - arm_tlb_mte_tagged(&info.attrs) && - !mte_probe(env, mtedesc, addr)) { + if (mtedesc && info.tagged && !mte_probe(env, mtedesc, addr)) { goto fault; } @@ -6946,7 +6927,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, info.attrs, BP_MEM_WRITE, retaddr); } - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 9de3099153..1305b6ec7d 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -245,10 +245,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, extra.x = FIELD_DP64(extra.x, PAGEENTRYEXTRA, SHAREABILITY, cacheattrs.shareability); } - /* Notice and record tagged memory. */ - if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) { - arm_tlb_mte_tagged(&attrs) = true; - } tlb_set_page_with_extra(cs, address, phys_addr, attrs, extra, prot, mmu_idx, page_size); From patchwork Sun Jul 3 08:23:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586795 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2910910mab; Sun, 3 Jul 2022 01:26:36 -0700 (PDT) X-Google-Smtp-Source: AGRyM1v+YpFB4VM5Dxwn4O1onu5qok/Pq3mJZ5lCBFXqR+dxZ8TbS4/BNnuqROrM6Xo9FAt8Zly+ X-Received: by 2002:a81:f83:0:b0:317:dbd3:1f24 with SMTP id 125-20020a810f83000000b00317dbd31f24mr27356158ywp.386.1656836796085; Sun, 03 Jul 2022 01:26:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656836796; cv=none; d=google.com; s=arc-20160816; b=cKp/6+vWK8LYRBuStzkPhqepqOlDttdS+Mm+Uq8jonQZT0OvoTM6MT8X8RFqMWqCLA y8/Tp46u9w3pZQt/ICBfIIEZFlT7wrryOT7Or2qMc5tr1E0WHb3xx3fxrYSHl5rDsknv RNr2sJ1iWAlfg2Gc2oLcXZyB2G/x7zh71xEWjT41jS0EMXO3dovrYpYC/MZQ13Y3UN97 QQbiEoIONB9+jgL1658DIkPwmDYEgZKgOVrvRywOu0OH+BVL5oJkHRmuNCHFEM1pw0FE 1vaQugw4cA74n3KA2FYfkb6K1aLi7dibChwoG4qXsmDF/W6pwTqRQl+ZWTy7S/QCP5fz kNNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MmQAzcfABxlHx5cSzgemNY9cO4UZUm16Jrwpdca+cDs=; b=MD9tGEQdUk4uLeBhHRSRIPbvXe4X6k7pTFZdvll/9z3Cr5DPp/fPk/Hd4F8wEqagmx eTMhM70mCndm72R8KYPupDxq1NuFp7/l4uVCGcaRLyKnVFtUHXPBANeHA1eMW2mwctOY XN+HHvFdYoQzJcGolxjhM1otDi+mvQYh6tG8+0CDuHfojSBCkADJXiYPyEYDBOMCYDPg AvTk46B36SC7e6stG8oBAxno4g1ELVSQmebHrT0fD8XW1mNlkzFr+wVB+dqv8sUl1oOs 6ehgu/7rTjCoGhhC8/KS0DnX4mpKFyHT0InJasBm4KRQPQvvk4Men6UGZpjZn78DKTRy zvhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=syNrUrfq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 06/62] target/arm: Use PageEntryExtra for BTI Date: Sun, 3 Jul 2022 13:53:23 +0530 Message-Id: <20220703082419.770989-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a bit to ARMCacheAttrs to hold the guarded bit between get_phys_addr_lpae and arm_cpu_tlb_fill, then put the bit into PageEntryExtra. In is_guarded_page, use probe_access_extra instead of just guessing that the tlb entry is still present. Also handles the FIXME about executing from device memory. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 13 ------------- target/arm/internals.h | 2 ++ target/arm/ptw.c | 4 ++-- target/arm/tlb_helper.c | 2 ++ target/arm/translate-a64.c | 22 ++++++++-------------- 5 files changed, 14 insertions(+), 29 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a26b9437e9..4a41b5dcef 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3357,19 +3357,6 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; -/* Helper for the macros below, validating the argument type. */ -static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) -{ - return x; -} - -/* - * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. - * Using these should be a bit more self-documenting than using the - * generic target bits directly. - */ -#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) - /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 2b38a83574..268c3c7380 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -77,6 +77,7 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ /* Bit definitions for PageEntryExtra */ FIELD(PAGEENTRYEXTRA, ATTRS, 0, 8) FIELD(PAGEENTRYEXTRA, SHAREABILITY, 8, 2) +FIELD(PAGEENTRYEXTRA, GUARDED, 10, 1) FIELD(PAGEENTRYEXTRA, PA, 12, 52) /* Minimum value which is a magic number for exception return */ @@ -1129,6 +1130,7 @@ typedef struct ARMCacheAttrs { unsigned int attrs:8; unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ bool is_s2_format:1; + bool guarded:1; /* guarded bit of the v8-64 PTE */ } ARMCacheAttrs; bool get_phys_addr(CPUARMState *env, target_ulong address, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index da478104f0..204c820026 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1320,8 +1320,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, txattrs->secure = false; } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ - if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(txattrs) = true; + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + cacheattrs->guarded = guarded; } if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 1305b6ec7d..7476fcafeb 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -244,6 +244,8 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cacheattrs.attrs); extra.x = FIELD_DP64(extra.x, PAGEENTRYEXTRA, SHAREABILITY, cacheattrs.shareability); + extra.x = FIELD_DP64(extra.x, PAGEENTRYEXTRA, GUARDED, + cacheattrs.guarded); } tlb_set_page_with_extra(cs, address, phys_addr, attrs, extra, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c86b97b1d4..57f492ccef 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14543,22 +14543,16 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s) #ifdef CONFIG_USER_ONLY return page_get_flags(addr) & PAGE_BTI; #else + MemTxAttrs attrs; + PageEntryExtra extra; + void *host; int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); - unsigned int index = tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + int flags; - /* - * We test this immediately after reading an insn, which means - * that any normal page must be in the TLB. The only exception - * would be for executing from flash or device memory, which - * does not retain the TLB entry. - * - * FIXME: Assume false for those, for now. We could use - * arm_cpu_get_phys_page_attrs_debug to re-read the page - * table entry even for that case. - */ - return (tlb_hit(entry->addr_code, addr) && - arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); + flags = probe_access_extra(env, addr, MMU_INST_FETCH, mmu_idx, + false, &host, &attrs, &extra, 0); + assert(!(flags & TLB_INVALID_MASK)); + return FIELD_EX64(extra.x, PAGEENTRYEXTRA, GUARDED); #endif } From patchwork Sun Jul 3 08:23:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586800 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2913970mab; Sun, 3 Jul 2022 01:33:54 -0700 (PDT) X-Google-Smtp-Source: AGRyM1smVWYtcmcvGvl3ABDZpbILwWXYonVJpd4mi3E69xLcj7BUg8UeOKWHdvah5Qx9iTcmH6nq X-Received: by 2002:a25:8f82:0:b0:66d:f6e9:843a with SMTP id u2-20020a258f82000000b0066df6e9843amr11400412ybl.232.1656837233974; Sun, 03 Jul 2022 01:33:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837233; cv=none; d=google.com; s=arc-20160816; b=LTLWLkfmCsFCROQ8WspcekjVHvF2gyLR2fAJx6GLgD/M32mSgWWXkto3fYPeSH2nNN 8VQhncCir3LgZCVWEGNDpDGNHfJIPbPFIitqTm6leG+KYmyQAwyHIO3sl9TSFsbhgbk4 bS0XHze+M6qiQ5P3UmYP0hqG24ZxNNKYq3ULpEG5eTtKbo1y5oialzbcr6ffmRWHSv+2 h9lSzufHW933VF3JT7c0l2g9FE/ovyOmASsatDShN9c+70DOm4tHcxRL5jknqgXwqhYe PzX/EDruDZAy2ZiAlnIqSVowqofEtElrRQdFBd7gXXhON+8y+pc8ren2U05RDEkeXqpz 4dXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mlHd+wwiv8pBaZCez3yDRMnKt1mN27booBhwkoA66eA=; b=ggwX0fri1nCnv0BH1EQLd4AzVvL8LQPnAnot9LCyYFlgPtsEvL35mTKTKVraKWVr2b z6dE3BrPRmNo0n9FqkBMo218Q/R+twdv8Oq8EbExYjlrhXwZURPXBAwKUp7euuLHx8vq lw/GZIqP1Z9jiz3EsbEAOjXfegimSJN3W7NUE3Q3WkGHVW3JXFaxmOce4pR8Z6DRIkSz pBIkLhZMGe0BMR5rxwKRUxnPfsyZj16bRycjFp7GTixTinsk2QmKmh4omCrrj3BAngHV n4yMZyzjnCMO08ssy5q1jmXMpxds694pSiTYCgag3QnVE4E81TFhEvAH7R3FMWcHymjx ETGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y0WctPXq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 07/62] include/exec: Remove target_tlb_bitN from MemTxAttrs Date: Sun, 3 Jul 2022 13:53:24 +0530 Message-Id: <20220703082419.770989-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have now moved all uses to PageEntryExtra. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/memattrs.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..1bd7b6c5ca 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -47,16 +47,6 @@ typedef struct MemTxAttrs { unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; - /* - * The following are target-specific page-table bits. These are not - * related to actual memory transactions at all. However, this structure - * is part of the tlb_fill interface, cached in the cputlb structure, - * and has unused bits. These fields will be read by target-specific - * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. - */ - unsigned int target_tlb_bit0 : 1; - unsigned int target_tlb_bit1 : 1; - unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, From patchwork Sun Jul 3 08:23:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586798 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2912309mab; Sun, 3 Jul 2022 01:29:49 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tO6ZNthV+bd9R4f/Zo7Jd4ymWVgXP7txqxt0XiKFLzjLn6q7rAJcItdbUkgz9bxo5uMajS X-Received: by 2002:a81:6d02:0:b0:31c:80d6:ea5b with SMTP id i2-20020a816d02000000b0031c80d6ea5bmr6535768ywc.183.1656836989086; Sun, 03 Jul 2022 01:29:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656836989; cv=none; d=google.com; s=arc-20160816; b=VxIULYliQoRSSs/Q9SAaDEaDm3TIbJ5WYZ11gVmaOJ0/nqlhAooQkjU9J4FrQ9TEZQ k0TVVyH5DEkJQDUpGX/YyLA2F7oU3jts3qXvm2mZNHRP5qs4AbAuopYBJG7ajGK9Ly96 SydfsHAA8O8GWNOmiJ+YcxUz/if9Uqx7CRSk8suwks+7N1wa6xPKEISCv6xdd9kfacj4 nsCJtWve3Gejhof/loJhNiY91clLSrPKri6msKKBqCBgalSUUd9v+Z2ezLs8Fsgwc8ov jN/pL0HSNw/jNa5FWpDibwOVKxRjrBOlxAEzmCQelPcUf7P1ZyedLQsEVz2l3UHH7UEr oM6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6qru92ZuLiyvaecg4Q7plmxEBc6fVkpY5sdUgPll6PE=; b=fWhBgk42zyQmDfGbBdfoC1wfkLT2ih8J9Jr8mAzUYJPf5umevnfXqlps5jt1Zyewpt O+F0QVlNvPMG7TzVcpWR20DFuKssuDvwQCwmIo2411LdCVOrsfqDYeoIIu5QEV3IoZ82 KqpHD28Ia35KfJNb5r8o1S/MQgr8pFQ2GyZjx9idO3Vvhokq5Kem8JCO6p77d/K6lPkO RjYZALuuZNe/2uPoay65OC9cShOX1BR1zu5i8Btw6lCmz+r4khLEVeCUJAqB7z6qujbl lQTuSUAHOEp2oXwybtQevP2BebBcBCruWKw6XnoJ1mgNOjiw/TtnLFK6k3UtTqp+85i/ 1qUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q5S6vdme; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 08/62] target/arm: Create GetPhysAddrResult Date: Sun, 3 Jul 2022 13:53:25 +0530 Message-Id: <20220703082419.770989-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Combine 5 output pointer argument from get_phys_addr into a single struct. Adjust all callers. Signed-off-by: Richard Henderson --- target/arm/internals.h | 13 ++++- target/arm/helper.c | 27 ++++----- target/arm/m_helper.c | 52 +++++------------ target/arm/ptw.c | 125 +++++++++++++++++++++------------------- target/arm/tlb_helper.c | 26 ++++----- 5 files changed, 113 insertions(+), 130 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 268c3c7380..7d08917f88 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1133,11 +1133,18 @@ typedef struct ARMCacheAttrs { bool guarded:1; /* guarded bit of the v8-64 PTE */ } ARMCacheAttrs; +/* Fields that are valid upon success. */ +typedef struct GetPhysAddrResult { + hwaddr phys; + target_ulong page_size; + int prot; + MemTxAttrs attrs; + ARMCacheAttrs cacheattrs; +} GetPhysAddrResult; + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); void arm_log_exception(CPUState *cs); diff --git a/target/arm/helper.c b/target/arm/helper.c index f6dcb1a115..fb13e0f4c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3173,24 +3173,19 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx) { - hwaddr phys_addr; - target_ulong page_size; - int prot; bool ret; uint64_t par64; bool format64 = false; - MemTxAttrs attrs = {}; ARMMMUFaultInfo fi = {}; - ARMCacheAttrs cacheattrs = {}; + GetPhysAddrResult res = {}; - ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, - &prot, &page_size, &fi, &cacheattrs); + ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never * have to deal with the ARMCacheAttrs format for S2 only. */ - assert(!cacheattrs.is_s2_format); + assert(!res.cacheattrs.is_s2_format); if (ret) { /* @@ -3296,12 +3291,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, /* Create a 64-bit PAR */ par64 = (1 << 11); /* LPAE bit always set */ if (!ret) { - par64 |= phys_addr & ~0xfffULL; - if (!attrs.secure) { + par64 |= res.phys & ~0xfffULL; + if (!res.attrs.secure) { par64 |= (1 << 9); /* NS */ } - par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ - par64 |= cacheattrs.shareability << 7; /* SH */ + par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ + par64 |= res.cacheattrs.shareability << 7; /* SH */ } else { uint32_t fsr = arm_fi_to_lfsc(&fi); @@ -3321,13 +3316,13 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, */ if (!ret) { /* We do not set any attribute bits in the PAR */ - if (page_size == (1 << 24) + if (res.page_size == (1 << 24) && arm_feature(env, ARM_FEATURE_V7)) { - par64 = (phys_addr & 0xff000000) | (1 << 1); + par64 = (res.phys & 0xff000000) | (1 << 1); } else { - par64 = phys_addr & 0xfffff000; + par64 = res.phys & 0xfffff000; } - if (!attrs.secure) { + if (!res.attrs.secure) { par64 |= (1 << 9); /* NS */ } } else { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 308610f6b4..84c6796b8d 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -183,19 +183,14 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, { CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; - MemTxAttrs attrs = {}; MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; + GetPhysAddrResult res = {}; ARMMMUFaultInfo fi = {}; - ARMCacheAttrs cacheattrs = {}; bool secure = mmu_idx & ARM_MMU_IDX_M_S; int exc; bool exc_secure; - if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { + if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { if (mode == STACK_LAZYFP) { @@ -228,8 +223,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, } goto pend_fault; } - address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value, - attrs, &txres); + address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value, + res.attrs, &txres); if (txres != MEMTX_OK) { /* BusFault trying to write the data */ if (mode == STACK_LAZYFP) { @@ -276,20 +271,15 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, { CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; - MemTxAttrs attrs = {}; MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; + GetPhysAddrResult res = {}; ARMMMUFaultInfo fi = {}; - ARMCacheAttrs cacheattrs = {}; bool secure = mmu_idx & ARM_MMU_IDX_M_S; int exc; bool exc_secure; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -308,8 +298,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, goto pend_fault; } - value = address_space_ldl(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); + value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, + res.attrs, &txres); if (txres != MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); @@ -2008,13 +1998,9 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; V8M_SAttributes sattrs = {}; - MemTxAttrs attrs = {}; + GetPhysAddrResult res = {}; ARMMMUFaultInfo fi = {}; - ARMCacheAttrs cacheattrs = {}; MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); if (!sattrs.nsc || sattrs.ns) { @@ -2028,16 +2014,15 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, "...really SecureFault with SFSR.INVEP\n"); return false; } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { + if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n"); return false; } - *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); + *insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys, + res.attrs, &txres); if (txres != MEMTX_OK) { env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); @@ -2060,17 +2045,12 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, */ CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; - MemTxAttrs attrs = {}; MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; + GetPhysAddrResult res = {}; ARMMMUFaultInfo fi = {}; - ARMCacheAttrs cacheattrs = {}; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -2088,8 +2068,8 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, } return false; } - value = address_space_ldl(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); + value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, + res.attrs, &txres); if (txres != MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 204c820026..1a946f3757 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2296,18 +2296,12 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime - * @phys_ptr: set to the physical address corresponding to the virtual address - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size: set to the size of the page containing phys_ptr + * @result: set on translation success. * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes */ bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); @@ -2318,43 +2312,53 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, */ if (arm_feature(env, ARM_FEATURE_EL2)) { hwaddr ipa; - int s2_prot; + int s1_prot; int ret; bool ipa_secure; - ARMCacheAttrs cacheattrs2 = {}; + ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; - ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa, - attrs, prot, page_size, fi, cacheattrs); + ret = get_phys_addr(env, address, access_type, s1_mmu_idx, + result, fi); /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - *phys_ptr = ipa; return ret; } - ipa_secure = attrs->secure; + ipa = result->phys; + ipa_secure = result->attrs.secure; if (arm_is_secure_below_el3(env)) { - if (ipa_secure) { - attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); - } else { - attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); - } + result->attrs.secure = + (ipa_secure + ? !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW) + : !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW)); } else { assert(!ipa_secure); } - s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + s2_mmu_idx = (result->attrs.secure + ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; - /* S1 is done. Now do S2 translation. */ + /* + * S1 is done, now do S2 translation. + * Save the stage1 results so that we may merge + * prot and cacheattrs later. + */ + s1_prot = result->prot; + cacheattrs1 = result->cacheattrs; + memset(result, 0, sizeof(*result)); + ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0, - phys_ptr, attrs, &s2_prot, - page_size, fi, &cacheattrs2); + &result->phys, &result->attrs, + &result->prot, &result->page_size, + fi, &result->cacheattrs); fi->s2addr = ipa; + /* Combine the S1 and S2 perms. */ - *prot &= s2_prot; + result->prot &= s1_prot; /* If S2 fails, return early. */ if (ret) { @@ -2370,20 +2374,21 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, * Outer Write-Back Read-Allocate Write-Allocate. * Do not overwrite Tagged within attrs. */ - if (cacheattrs->attrs != 0xf0) { - cacheattrs->attrs = 0xff; + if (cacheattrs1.attrs != 0xf0) { + cacheattrs1.attrs = 0xff; } - cacheattrs->shareability = 0; + cacheattrs1.shareability = 0; } - *cacheattrs = combine_cacheattrs(env, *cacheattrs, cacheattrs2); + result->cacheattrs = combine_cacheattrs(env, cacheattrs1, + result->cacheattrs); /* Check if IPA translates to secure or non-secure PA space. */ if (arm_is_secure_below_el3(env)) { if (ipa_secure) { - attrs->secure = + result->attrs.secure = !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); } else { - attrs->secure = + result->attrs.secure = !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); } @@ -2402,8 +2407,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, * cannot upgrade an non-secure translation regime's attributes * to secure. */ - attrs->secure = regime_is_secure(env, mmu_idx); - attrs->user = regime_is_user(env, mmu_idx); + result->attrs.secure = regime_is_secure(env, mmu_idx); + result->attrs.user = regime_is_user(env, mmu_idx); /* * Fast Context Switch Extension. This doesn't exist at all in v8. @@ -2420,20 +2425,22 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; - *page_size = TARGET_PAGE_SIZE; + result->page_size = TARGET_PAGE_SIZE; if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); + &result->phys, &result->attrs, + &result->prot, &result->page_size, fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, page_size, fi); + &result->phys, &result->prot, + &result->page_size, fi); } else { /* Pre-v7 MPU */ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - phys_ptr, prot, fi); + &result->phys, &result->prot, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", @@ -2441,9 +2448,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, (access_type == MMU_DATA_STORE ? "writing" : "execute"), (uint32_t)address, mmu_idx, ret ? "Miss" : "Hit", - *prot & PAGE_READ ? 'r' : '-', - *prot & PAGE_WRITE ? 'w' : '-', - *prot & PAGE_EXEC ? 'x' : '-'); + result->prot & PAGE_READ ? 'r' : '-', + result->prot & PAGE_WRITE ? 'w' : '-', + result->prot & PAGE_EXEC ? 'x' : '-'); return ret; } @@ -2488,14 +2495,14 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, address = extract64(address, 0, 52); } } - *phys_ptr = address; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - *page_size = TARGET_PAGE_SIZE; + result->phys = address; + result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->page_size = TARGET_PAGE_SIZE; /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ hcr = arm_hcr_el2_eff(env); - cacheattrs->shareability = 0; - cacheattrs->is_s2_format = false; + result->cacheattrs.shareability = 0; + result->cacheattrs.is_s2_format = false; if (hcr & HCR_DC) { if (hcr & HCR_DCT) { memattr = 0xf0; /* Tagged, Normal, WB, RWA */ @@ -2508,24 +2515,27 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } else { memattr = 0x44; /* Normal, NC, No */ } - cacheattrs->shareability = 2; /* outer sharable */ + result->cacheattrs.shareability = 2; /* outer sharable */ } else { memattr = 0x00; /* Device, nGnRnE */ } - cacheattrs->attrs = memattr; + result->cacheattrs.attrs = memattr; return 0; } if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, false, - phys_ptr, attrs, prot, page_size, - fi, cacheattrs); + &result->phys, &result->attrs, + &result->prot, &result->page_size, + fi, &result->cacheattrs); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); + &result->phys, &result->attrs, + &result->prot, &result->page_size, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - phys_ptr, prot, page_size, fi); + &result->phys, &result->prot, + &result->page_size, fi); } } @@ -2534,21 +2544,16 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - hwaddr phys_addr; - target_ulong page_size; - int prot; - bool ret; + GetPhysAddrResult res = {}; ARMMMUFaultInfo fi = {}; ARMMMUIdx mmu_idx = arm_mmu_idx(env); - ARMCacheAttrs cacheattrs = {}; + bool ret; - *attrs = (MemTxAttrs) {}; - - ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fi, &cacheattrs); + ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi); + *attrs = res.attrs; if (ret) { return -1; } - return phys_addr; + return res.phys; } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7476fcafeb..28495ff525 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -209,11 +209,8 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { ARMCPU *cpu = ARM_CPU(cs); ARMMMUFaultInfo fi = {}; - hwaddr phys_addr; - target_ulong page_size; - int prot, ret; - MemTxAttrs attrs = {}; - ARMCacheAttrs cacheattrs = {}; + GetPhysAddrResult res = {}; + int ret; /* * Walk the page table and (if the mapping exists) add the page @@ -223,8 +220,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, */ ret = get_phys_addr(&cpu->env, address, access_type, core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &phys_addr, &attrs, &prot, &page_size, - &fi, &cacheattrs); + &res, &fi); if (likely(!ret)) { PageEntryExtra extra = {}; @@ -234,22 +230,22 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * pass in the exact addresses. This only happens for M-profile, * which does not use or require PageEntryExtra. */ - if (page_size >= TARGET_PAGE_SIZE) { - phys_addr &= TARGET_PAGE_MASK; + if (res.page_size >= TARGET_PAGE_SIZE) { + res.phys &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; /* Record some particulars for later lookup. */ - extra.x = phys_addr; + extra.x = res.phys; extra.x = FIELD_DP64(extra.x, PAGEENTRYEXTRA, ATTRS, - cacheattrs.attrs); + res.cacheattrs.attrs); extra.x = FIELD_DP64(extra.x, PAGEENTRYEXTRA, SHAREABILITY, - cacheattrs.shareability); + res.cacheattrs.shareability); extra.x = FIELD_DP64(extra.x, PAGEENTRYEXTRA, GUARDED, - cacheattrs.guarded); + res.cacheattrs.guarded); } - tlb_set_page_with_extra(cs, address, phys_addr, attrs, extra, - prot, mmu_idx, page_size); + tlb_set_page_with_extra(cs, address, res.phys, res.attrs, extra, + res.prot, mmu_idx, res.page_size); return true; } else if (probe) { return false; From patchwork Sun Jul 3 08:23:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586804 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2915872mab; Sun, 3 Jul 2022 01:38:23 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vVhFEF7m+8rdKfe38oQLdrvoF297eIEIkO/MCQmpfeVUAN62+hAFWHf5ayUnn7shdVDcD7 X-Received: by 2002:a81:14d6:0:b0:31c:4c40:c75b with SMTP id 205-20020a8114d6000000b0031c4c40c75bmr18041620ywu.129.1656837503015; Sun, 03 Jul 2022 01:38:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837503; cv=none; d=google.com; s=arc-20160816; b=op3Gj/bdiG0OMTCjqSWytZOquM1cczpMOtSx18upEXoe9qeMqxxt/8Ww3qfFenuHOK JCprrbe9UeVXnubEs5Q+xMcKy1O1JnpA4ozlCd4+GxbM9E/KmWYubGrGcT+lIDMQnZDT cIoDgBlpp2osPRczwlni3b+SEjYuMKoG9Dn1f+zJ5vCBxe8vCnoGqEuoqZpDOxLNPKbx oxFDegWZSjLHdLZcXTLMWjLywsDXkKXGDx1rdHh7UtetcBA4E1wF1LX9zDHos0OSUn8b LTZH9Q9shlmwnd0xpMwXkdzmCq9X1ly3x9gk7YSCag4PoEmvlU6uD2AEkyPWGAAqLcZQ r7NA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PdgMMDPY/PA7ZASda7ITPHb+8tgdBcmBCdmhnbT+eGk=; b=y+8XRBFmaqjazXirmHancHJGCVm6M1bN0wpUgM2zeENTuvvqACoHBO/Vi07V4YPBQ3 9/8rv8yFxYVtrHCl9MAra1WhQHwksDnw8LxEylriDHBaRoownfnkZ43QX88H9Wgq8fyi DtJ6xhTajNcdw6/sdHBiwAn+tw1z/w43wawunvLlgkPenOtlQqYGeYSUfob67jQasKv7 UNJuCTXjvRu00Uhu1PE9RUTjcgdmHfqG5oGarDc32mVcU0AhpinoIaCoTTnJqNsHBStW Y+6bc+0D+Q6R8oBh/Ek1nMklWkm0uK/U8uZCqyP2SHzlSg5mekoivg9wXmjgRKrZTUMl mtlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VFf5P75p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 09/62] target/arm: Fix ipa_secure in get_phys_addr Date: Sun, 3 Jul 2022 13:53:26 +0530 Message-Id: <20220703082419.770989-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The starting security state comes with the translation regime, not the current state of arm_is_secure_below_el3(). More use of the local variable, ipa_secure, which does not need to be written back to result->attrs.secure -- we compute that value later, after the S2 walk is complete. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1a946f3757..b78658161f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2304,6 +2304,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); + bool is_secure = regime_is_secure(env, mmu_idx); if (mmu_idx != s1_mmu_idx) { /* @@ -2328,18 +2329,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } ipa = result->phys; - ipa_secure = result->attrs.secure; - if (arm_is_secure_below_el3(env)) { - result->attrs.secure = - (ipa_secure - ? !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW) - : !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW)); + if (is_secure) { + /* Select TCR based on the NS bit from the S1 walk. */ + ipa_secure = !(result->attrs.secure + ? env->cp15.vstcr_el2.raw_tcr & VSTCR_SW + : env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); } else { - assert(!ipa_secure); + ipa_secure = false; } - s2_mmu_idx = (result->attrs.secure - ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); + s2_mmu_idx = (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; /* @@ -2383,7 +2382,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, result->cacheattrs); /* Check if IPA translates to secure or non-secure PA space. */ - if (arm_is_secure_below_el3(env)) { + if (is_secure) { if (ipa_secure) { result->attrs.secure = !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); @@ -2407,7 +2406,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, * cannot upgrade an non-secure translation regime's attributes * to secure. */ - result->attrs.secure = regime_is_secure(env, mmu_idx); + result->attrs.secure = is_secure; result->attrs.user = regime_is_user(env, mmu_idx); /* From patchwork Sun Jul 3 08:23:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586808 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2917427mab; Sun, 3 Jul 2022 01:42:01 -0700 (PDT) X-Google-Smtp-Source: AGRyM1skFH9P+6Se6TucpLRsnXkr1IJInYICGoynGOzHbCIwfejhz1JszbZCxEMjp/zGq8hR7QEi X-Received: by 2002:a0d:ca93:0:b0:31b:ac58:1047 with SMTP id m141-20020a0dca93000000b0031bac581047mr25717944ywd.323.1656837721798; Sun, 03 Jul 2022 01:42:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837721; cv=none; d=google.com; s=arc-20160816; b=gjxZgHCadaSNJ3nDUS6glRz5y6W9cK5ioQdWnb6ojfwNcbZ+7Zj3tfQ4VdzNcDDU0P 4iDundDmcmDBERyWaj6W5kb7qxTdLDbIs+gw7pUNBbTkzRkfRu4gxN8n3AS+MaNw1AD7 SyAZpsLxLC+AzNnIqmIzUwSbYamSaN1nSZKAsDC0osnLMYn6YrfZp8ze8htcCfxCQx6M kCiTMfQgnLSINKPaXHJGSm2SdCBxeuifGZpdnXsYN96T4jqwn+EZjR5Mvp6uC9zZZSua V25C/mAIvPu+Y22lOuULmo6t0ML9U64/gXJ10yGU60LwBF0CmBtsSgxxpUhq5hwfd/oS XJqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nWhJRX2CcLLqjJLeiFrCW24//WXCOsrf/EygkQpW/6g=; b=OiFcdqPUvtn35/njzlnotBvKZ4EawAJZQP31lWJVHDcwnUF0Djbu6rVm6HQON/4Tlc HCAy53t+UzSbtW94Gs56Om+BO8GTc1yFngdkMq2znLlRdhFn2NDdH38AS26moF5tgNNR HUB8XNjKjvis994BDwNb0OANveGzhyrMSdUt2BnyFRhVUb9SydZEMRUHTOOsXX3ezrgr Vv4Jj5T8agni4PVeuMZJYRgMSxu+okC6lq6UNP3HF2OjP6Vf2+HqaosnIbyhlho0fPSm yP5NLWaer9ATnvTlirx6ZqyxrElQnuAfshTd90NMvTP5NqxiU33/wxcSoRAWqGSnH1Pb i0mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MuttzmbS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 10/62] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Date: Sun, 3 Jul 2022 13:53:27 +0530 Message-Id: <20220703082419.770989-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 69 ++++++++++++++++++------------------------------ 1 file changed, 26 insertions(+), 43 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b78658161f..5e79c9be98 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,10 +16,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, hwaddr *phys_ptr, - MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + bool s1_is_el0, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) __attribute__((nonnull)); /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ @@ -204,18 +202,13 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, { if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - target_ulong s2size; - hwaddr s2pa; - int s2prot; - int ret; ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - ARMCacheAttrs cacheattrs = {}; - MemTxAttrs txattrs = {}; + GetPhysAddrResult s2 = {}; + int ret; ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false, - &s2pa, &txattrs, &s2prot, &s2size, fi, - &cacheattrs); + &s2, fi); if (ret) { assert(fi->type != ARMFault_None); fi->s2addr = addr; @@ -225,7 +218,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && - ptw_attrs_are_device(env, cacheattrs)) { + ptw_attrs_are_device(env, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -249,7 +242,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, assert(!*is_secure); } - addr = s2pa; + addr = s2.phys; } return addr; } @@ -968,19 +961,13 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, * table walk), must be true if this is stage 2 of a stage 1+2 * walk for an EL0 access. If @mmu_idx is anything else, * @s1_is_el0 is ignored. - * @phys_ptr: set to the physical address corresponding to the virtual address - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size_ptr: set to the size of the page containing phys_ptr + * @result: set on translation success, * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, hwaddr *phys_ptr, - MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + bool s1_is_el0, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); /* Read an LPAE long-descriptor translation table. */ @@ -1298,16 +1285,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { ns = mmu_idx == ARMMMUIdx_Stage2; xn = extract32(attrs, 11, 2); - *prot = get_S2prot(env, ap, xn, s1_is_el0); + result->prot = get_S2prot(env, ap, xn, s1_is_el0); } else { ns = extract32(attrs, 3, 1); xn = extract32(attrs, 12, 1); pxn = extract32(attrs, 11, 1); - *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); + result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); } fault_type = ARMFault_Permission; - if (!(*prot & (1 << access_type))) { + if (!(result->prot & (1 << access_type))) { goto do_fault; } @@ -1317,23 +1304,23 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - txattrs->secure = false; + result->attrs.secure = false; } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - cacheattrs->guarded = guarded; + result->cacheattrs.guarded = guarded; } if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { - cacheattrs->is_s2_format = true; - cacheattrs->attrs = extract32(attrs, 0, 4); + result->cacheattrs.is_s2_format = true; + result->cacheattrs.attrs = extract32(attrs, 0, 4); } else { /* Index into MAIR registers for cache attributes */ uint8_t attrindx = extract32(attrs, 0, 3); uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <= 7); - cacheattrs->is_s2_format = false; - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); + result->cacheattrs.is_s2_format = false; + result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); } /* @@ -1342,13 +1329,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * that case comes from TCR_ELx, which we extracted earlier. */ if (param.ds) { - cacheattrs->shareability = param.sh; + result->cacheattrs.shareability = param.sh; } else { - cacheattrs->shareability = extract32(attrs, 6, 2); + result->cacheattrs.shareability = extract32(attrs, 6, 2); } - *phys_ptr = descaddr; - *page_size_ptr = page_size; + result->phys = descaddr; + result->page_size = page_size; return false; do_fault: @@ -2350,10 +2337,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0, - &result->phys, &result->attrs, - &result->prot, &result->page_size, - fi, &result->cacheattrs); + ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + is_el0, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -2524,9 +2509,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, false, - &result->phys, &result->attrs, - &result->prot, &result->page_size, - fi, &result->cacheattrs); + result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, &result->phys, &result->attrs, From patchwork Sun Jul 3 08:23:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586812 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2918632mab; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 11/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v6 Date: Sun, 3 Jul 2022 13:53:28 +0530 Message-Id: <20220703082419.770989-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5e79c9be98..d70c9120fc 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -532,8 +532,7 @@ do_fault: static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, ARMMMUFaultInfo *fi) + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int level = 1; @@ -593,11 +592,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; - *page_size = 0x1000000; + result->page_size = 0x1000000; } else { /* Section. */ phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); - *page_size = 0x100000; + result->page_size = 0x100000; } ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); xn = desc & (1 << 4); @@ -623,12 +622,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, case 1: /* 64k page. */ phys_addr = (desc & 0xffff0000) | (address & 0xffff); xn = desc & (1 << 15); - *page_size = 0x10000; + result->page_size = 0x10000; break; case 2: case 3: /* 4k page. */ phys_addr = (desc & 0xfffff000) | (address & 0xfff); xn = desc & 1; - *page_size = 0x1000; + result->page_size = 0x1000; break; default: /* Never happens, but compiler isn't smart enough to tell. */ @@ -636,7 +635,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, } } if (domain_prot == 3) { - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; } else { if (pxn && !regime_is_user(env, mmu_idx)) { xn = 1; @@ -654,14 +653,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, fi->type = ARMFault_AccessFlag; goto do_fault; } - *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); } else { - *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); } - if (*prot && !xn) { - *prot |= PAGE_EXEC; + if (result->prot && !xn) { + result->prot |= PAGE_EXEC; } - if (!(*prot & (1 << access_type))) { + if (!(result->prot & (1 << access_type))) { /* Access permission fault. */ fi->type = ARMFault_Permission; goto do_fault; @@ -672,9 +671,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - attrs->secure = false; + result->attrs.secure = false; } - *phys_ptr = phys_addr; + result->phys = phys_addr; return false; do_fault: fi->domain = domain; @@ -2512,8 +2511,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - &result->phys, &result->attrs, - &result->prot, &result->page_size, fi); + result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, &result->phys, &result->prot, From patchwork Sun Jul 3 08:23:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586802 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2914444mab; Sun, 3 Jul 2022 01:35:06 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tbJR+jcbyrRv/WX+NKit+THt4NOZh4PE/QO+bqSck9KlOdpthgfmAPFnL/EEOd/4xfETEH X-Received: by 2002:a0d:cdc7:0:b0:318:7c40:6578 with SMTP id p190-20020a0dcdc7000000b003187c406578mr26560595ywd.202.1656837306557; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 12/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v5 Date: Sun, 3 Jul 2022 13:53:29 +0530 Message-Id: <20220703082419.770989-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d70c9120fc..490a57ec5a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -410,9 +410,7 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int level = 1; uint32_t table; @@ -460,7 +458,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* 1Mb section. */ phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); ap = (desc >> 10) & 3; - *page_size = 1024 * 1024; + result->page_size = 1024 * 1024; } else { /* Lookup l2 entry. */ if (type == 1) { @@ -482,12 +480,12 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, case 1: /* 64k page. */ phys_addr = (desc & 0xffff0000) | (address & 0xffff); ap = (desc >> (4 + ((address >> 13) & 6))) & 3; - *page_size = 0x10000; + result->page_size = 0x10000; break; case 2: /* 4k page. */ phys_addr = (desc & 0xfffff000) | (address & 0xfff); ap = (desc >> (4 + ((address >> 9) & 6))) & 3; - *page_size = 0x1000; + result->page_size = 0x1000; break; case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ if (type == 1) { @@ -495,7 +493,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, if (arm_feature(env, ARM_FEATURE_XSCALE) || arm_feature(env, ARM_FEATURE_V6)) { phys_addr = (desc & 0xfffff000) | (address & 0xfff); - *page_size = 0x1000; + result->page_size = 0x1000; } else { /* * UNPREDICTABLE in ARMv5; we choose to take a @@ -506,7 +504,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, } } else { phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); - *page_size = 0x400; + result->page_size = 0x400; } ap = (desc >> 4) & 3; break; @@ -515,14 +513,14 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, g_assert_not_reached(); } } - *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - *prot |= *prot ? PAGE_EXEC : 0; - if (!(*prot & (1 << access_type))) { + result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->prot |= result->prot ? PAGE_EXEC : 0; + if (!(result->prot & (1 << access_type))) { /* Access permission fault. */ fi->type = ARMFault_Permission; goto do_fault; } - *phys_ptr = phys_addr; + result->phys = phys_addr; return false; do_fault: fi->domain = domain; @@ -2514,8 +2512,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - &result->phys, &result->prot, - &result->page_size, fi); + result, fi); } } From patchwork Sun Jul 3 08:23:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586799 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2912733mab; Sun, 3 Jul 2022 01:30:47 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tG4i9M2BCJMKsn5HR7of0h1pmbr+vG/d2MP8h4XaM+vl0JMqz8pojBuOVpDh1ceQYBXBgX X-Received: by 2002:a25:34ce:0:b0:66e:332b:e002 with SMTP id b197-20020a2534ce000000b0066e332be002mr2972303yba.477.1656837047533; Sun, 03 Jul 2022 01:30:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837047; cv=none; d=google.com; s=arc-20160816; b=Rq7UqOZzxjBhpfxi5CGqb2ZmZG/4vRHZ89izYjX8eYIkAIEE4CgpWwNW4CF5jT50g/ Yg2WUyG+X/DII3CIC8JIuV1zo12kb6zVgz0cCPFdxfdCtMBwqZ2z0TgQ/vzE0gCyzqm7 qvy3plzM2YEVJ6MDzZPcceEdOrVQRMwTs58pNh3AoEAQxJaCx9PENlIKV7IsiPJDOZ4A MIEeEzLYmLn9aMNJ9+/6Jewt6SgZ0ysjpENL3uLt3BCDnCfERzAfTFskrcc8ZBQx/5OU OIEIdxnkAe6i/Ssd1wP8LCG3xBk4f9eoTf9CuEL7MPWVs0a8RsHjuvh/lFoXuJLdXOQI axwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EUX/T+NgNmJyoR8c7y7Ykrkjzc0XpAd0yqj7+G4mSDc=; b=BjmYSzMes7jA98eX93+f6aHW60qLX+YWSveV92Z617OPCRm04DqivNqka4KoxCOCAL aBsVvH7jrptX4HhQ20MgVBaiVNJuGDA8UEQbkF/QiAMvqpf5zNbz+4DNqqM8drEJe3hZ ZyBDu44nO+cOb9sO9DlC5kZVpd0OYgL9Sp0U8c203n7abIZ+uqH/M9RO54yBoYW27q/h WoWAl9n80S8+ifFLns3Stt3ee3qzvDTdKrp90goqt5YfVeMQQZtqfYAkA29pzWdBT7Bd s6a3fiwu4JVx2oh/KqQ/lnOzwEYUfVBwR1IQlOoeXnG0T5C3b+5vkULAN+7+/I1HhbtE LKYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MLeyEX3b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 13/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 Date: Sun, 3 Jul 2022 13:53:30 +0530 Message-Id: <20220703082419.770989-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 490a57ec5a..f2e429574d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1347,7 +1347,7 @@ do_fault: static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int n; @@ -1357,12 +1357,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled. */ - *phys_ptr = address; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->phys = address; + result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return false; } - *phys_ptr = address; + result->phys = address; for (n = 7; n >= 0; n--) { base = env->cp15.c6_region[n]; if ((base & 1) == 0) { @@ -1398,16 +1398,16 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, fi->level = 1; return true; } - *prot = PAGE_READ | PAGE_WRITE; + result->prot = PAGE_READ | PAGE_WRITE; break; case 2: - *prot = PAGE_READ; + result->prot = PAGE_READ; if (!is_user) { - *prot |= PAGE_WRITE; + result->prot |= PAGE_WRITE; } break; case 3: - *prot = PAGE_READ | PAGE_WRITE; + result->prot = PAGE_READ | PAGE_WRITE; break; case 5: if (is_user) { @@ -1415,10 +1415,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, fi->level = 1; return true; } - *prot = PAGE_READ; + result->prot = PAGE_READ; break; case 6: - *prot = PAGE_READ; + result->prot = PAGE_READ; break; default: /* Bad permission. */ @@ -1426,7 +1426,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, fi->level = 1; return true; } - *prot |= PAGE_EXEC; + result->prot |= PAGE_EXEC; return false; } @@ -2421,7 +2421,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } else { /* Pre-v7 MPU */ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - &result->phys, &result->prot, fi); + result, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", From patchwork Sun Jul 3 08:23:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586816 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2920385mab; Sun, 3 Jul 2022 01:48:29 -0700 (PDT) X-Google-Smtp-Source: AGRyM1us9nvLGEYZ9D4J6oenHp2VX70MV0CAVSqEKaiz7KKJ9j4HQCbjhHXGvTfwCn6GWcBs/bQP X-Received: by 2002:a0d:e8c2:0:b0:317:b1e0:c85d with SMTP id r185-20020a0de8c2000000b00317b1e0c85dmr26926838ywe.94.1656838109291; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 14/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 Date: Sun, 3 Jul 2022 13:53:31 +0530 Message-Id: <20220703082419.770989-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f2e429574d..4b69ecb1b9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1509,17 +1509,16 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int n; bool is_user = regime_is_user(env, mmu_idx); - *phys_ptr = address; - *page_size = TARGET_PAGE_SIZE; - *prot = 0; + result->phys = address; + result->page_size = TARGET_PAGE_SIZE; + result->prot = 0; if (regime_translation_disabled(env, mmu_idx) || m_is_ppb_region(env, address)) { @@ -1531,7 +1530,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, * which always does a direct read using address_space_ldl(), rather * than going via this function, so we don't need to check that here. */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); } else { /* MPU enabled */ for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { /* region search */ @@ -1573,7 +1572,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, if (ranges_overlap(base, rmask, address & TARGET_PAGE_MASK, TARGET_PAGE_SIZE)) { - *page_size = 1; + result->page_size = 1; } continue; } @@ -1611,7 +1610,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, continue; } if (rsize < TARGET_PAGE_BITS) { - *page_size = 1 << rsize; + result->page_size = 1 << rsize; } break; } @@ -1622,7 +1621,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, fi->type = ARMFault_Background; return true; } - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); } else { /* a MPU hit! */ uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); @@ -1639,16 +1638,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, case 5: break; /* no access */ case 3: - *prot |= PAGE_WRITE; + result->prot |= PAGE_WRITE; /* fall through */ case 2: case 6: - *prot |= PAGE_READ | PAGE_EXEC; + result->prot |= PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value */ if (arm_feature(env, ARM_FEATURE_M)) { - *prot |= PAGE_READ | PAGE_EXEC; + result->prot |= PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1664,16 +1663,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, case 1: case 2: case 3: - *prot |= PAGE_WRITE; + result->prot |= PAGE_WRITE; /* fall through */ case 5: case 6: - *prot |= PAGE_READ | PAGE_EXEC; + result->prot |= PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value */ if (arm_feature(env, ARM_FEATURE_M)) { - *prot |= PAGE_READ | PAGE_EXEC; + result->prot |= PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1686,14 +1685,14 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, /* execute never */ if (xn) { - *prot &= ~PAGE_EXEC; + result->prot &= ~PAGE_EXEC; } } } fi->type = ARMFault_Permission; fi->level = 1; - return !(*prot & (1 << access_type)); + return !(result->prot & (1 << access_type)); } bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, @@ -2416,8 +2415,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - &result->phys, &result->prot, - &result->page_size, fi); + result, fi); } else { /* Pre-v7 MPU */ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, From patchwork Sun Jul 3 08:23:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586807 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2916428mab; Sun, 3 Jul 2022 01:39:24 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vO8hfsoEolGkb0JTKfJf6ldvws1fGCTxCIP4CZk5ytCRu7r7xF2hsxYTFLh8GVtyd0eILc X-Received: by 2002:a81:c5:0:b0:317:6551:94e5 with SMTP id 188-20020a8100c5000000b00317655194e5mr27494025ywa.499.1656837564190; Sun, 03 Jul 2022 01:39:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837564; cv=none; d=google.com; s=arc-20160816; b=PCs8tHzdDNVrj0SY4yTfnx5LNOlNendtD5lKU835iO/R0nuXTAos088+WaRy1Y9v3y 4OotB5A5cPqa60IFun8Nag1BEGvFUhlz1M6qtC0n1BcWfoBut9wUPzG+sx4eNBZIItNq cwpeNSBxVx0cBAS2enRle2EtSCkIOlVYOLD2IqU/SDdVpW2yRMF/AOD6mAVdm/Cibh50 DBTvcOxxtqe43N+2tLlxx400pHw6kgUGagHvqIrjMYrHuK7IMDH+OMftzBBdGBkooIlI XB0wPBs9xplxxUdVxKRcxIf0nB0pkFj0bBIJ0/1dr2bEmnwXUuRzpwSLEjm59yKd+8T7 bXfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dcZqPXo79BDZKicxDVav3BkTqxcrjPA4mDAfxWZ855o=; b=RwMSeHCAxEaZWvhRBlmSOi8T7Z0uhFeopyfjqR9ieWOS/XYpgbBYKRgdmZafCTy3g7 QNjF4MtwRHbkmsAXTq5FdwtmgWnT6ixT8/SJ9MpeU1ylKyY+lYafumtN/R4jvWlVL5QQ QCABS9s1aWumt9qZzOdi3XtE3rw8pWZ/X40K7+FyMp6pqCV/7JfQDiM4u8s5NrCx/5+1 r+KXGbhv9Od6gLLFd5FdYBk7ZCqxkTcdKo4+Y7pawRBFd87Udb6A2kseff+fDC13bUfz foi18V3ZU1wK2cYvqW7yFd17kzroC8D+4P7mFynVPyAdDbzh4eODdzAwTHo+RJxthX+w RAAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BGe+4qSE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 15/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 Date: Sun, 3 Jul 2022 13:53:32 +0530 Message-Id: <20220703082419.770989-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4b69ecb1b9..ef28258d51 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1963,8 +1963,7 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, target_ulong *page_size, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { uint32_t secure = regime_is_secure(env, mmu_idx); @@ -1999,9 +1998,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, } else { fi->type = ARMFault_QEMU_SFault; } - *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; - *phys_ptr = address; - *prot = 0; + result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; + result->phys = address; + result->prot = 0; return true; } } else { @@ -2011,7 +2010,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, * might downgrade a secure access to nonsecure. */ if (sattrs.ns) { - txattrs->secure = false; + result->attrs.secure = false; } else if (!secure) { /* * NS access to S memory must fault. @@ -2024,17 +2023,19 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). */ fi->type = ARMFault_QEMU_SFault; - *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; - *phys_ptr = address; - *prot = 0; + result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; + result->phys = address; + result->prot = 0; return true; } } } - ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, &mpu_is_subpage, fi, NULL); - *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; + ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, + &result->phys, &result->attrs, &result->prot, + &mpu_is_subpage, fi, NULL); + result->page_size = + sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; return ret; } @@ -2410,8 +2411,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - &result->phys, &result->attrs, - &result->prot, &result->page_size, fi); + result, fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, From patchwork Sun Jul 3 08:23:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586821 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2921542mab; Sun, 3 Jul 2022 01:50:56 -0700 (PDT) X-Google-Smtp-Source: AGRyM1ssbmQr7wEXqrBjPZhrn0O2odFC9iU01vU6DUOVk9aeOvUCS+861ZUCYmF5Pixe01cIz0oJ X-Received: by 2002:a25:b80d:0:b0:66e:33ad:49bd with SMTP id v13-20020a25b80d000000b0066e33ad49bdmr2789246ybj.213.1656838256501; Sun, 03 Jul 2022 01:50:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838256; cv=none; d=google.com; s=arc-20160816; b=wjwaEV1CWtzL9PaHDX0o22Z9l2LDCyXkPha/u/Aps5JiZWBADTL3O8UXjZRaDr5WV6 Ppzl6k/+2XJrovt4mItpKvBNA7ew5F3PylNNfAurvvCo+CgJPrn/lNQCG7PK2Fo4UA3g /WtMAyj3TbzKvPFZ5vCr4QfT2at+Rid1DEJWf2NmAlNFn6Jzu+RsdpYnNvp7DYwynbA0 dpe5cV6nGOdYR8cj8cqL/c5zYG9igZGF7anICr60D+FTZjXla0vwV14O9CvYGItqS/7S G6ZL0C9OR1aoq4Qlf+GGkwaVqGk41svL3FcHkBQjj5jDHBX77/xEST7Z8Pgo3w6wm5wl DEBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=k+mjMX0KtyF64EiiGnY2kjZkHIBqsqSc4+dYDHj5ESs=; b=mnAJl3MTmgUZwX8IkL56gubu71Yi3Xx4vRaQ7EzypHRHfeMlGpTdS5E7JOqbUWpqZy z46Zux77SCxfrDXouwSHhS4jFOezK0AGikyb/0xXb6B5rhEUGnExfTlsR6O7e2wmvjM5 GrfZiHNjjxmIGNJ1QdkP/lv4Psh8+Rw0KWlv9lWdhfH4Fjnd5iHKqYLVuJaVYArij+Js GLy8sSy7CzcVwRk59mgyK4uETGu2nKnj9pZp6OC3WPHB4y0dJGZamgGk8t+hJ7jN8A0I NCd2r7/WoS1oAk67haw1p3C6Z1FRG6GdiSKKJBTtKY9NTcw0Y1cRO7np17M5LTuKVJti HMyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yfY9z+kW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 16/62] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup Date: Sun, 3 Jul 2022 13:53:33 +0530 Message-Id: <20220703082419.770989-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/internals.h | 11 +++++------ target/arm/m_helper.c | 16 +++++++--------- target/arm/ptw.c | 20 +++++++++----------- 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 7d08917f88..a817acaaf4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1115,12 +1115,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, V8M_SAttributes *sattrs); -bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion); - /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { /* @@ -1147,6 +1141,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion); + void arm_log_exception(CPUState *cs); #endif /* !CONFIG_USER_ONLY */ diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 84c6796b8d..69d4a63fa6 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2770,15 +2770,10 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) V8M_SAttributes sattrs = {}; uint32_t tt_resp; bool r, rw, nsr, nsrw, mrvalid; - int prot; - ARMMMUFaultInfo fi = {}; - MemTxAttrs attrs = {}; - hwaddr phys_addr; ARMMMUIdx mmu_idx; uint32_t mregion; bool targetpriv; bool targetsec = env->v7m.secure; - bool is_subpage; /* * Work out what the security state and privilege level we're @@ -2809,18 +2804,21 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) != 0 || alt) { + GetPhysAddrResult res = {}; + ARMMMUFaultInfo fi = {}; + bool is_subpage; + /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - &phys_addr, &attrs, &prot, &is_subpage, - &fi, &mregion); + &res, &is_subpage, &fi, &mregion); if (mregion == -1) { mrvalid = false; mregion = 0; } else { mrvalid = true; } - r = prot & PAGE_READ; - rw = prot & PAGE_WRITE; + r = res.prot & PAGE_READ; + rw = res.prot & PAGE_WRITE; } else { r = false; rw = false; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ef28258d51..b012577f17 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1697,8 +1697,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, + GetPhysAddrResult *result, bool *is_subpage, ARMMMUFaultInfo *fi, uint32_t *mregion) { /* @@ -1720,8 +1719,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); *is_subpage = false; - *phys_ptr = address; - *prot = 0; + result->phys = address; + result->prot = 0; if (mregion) { *mregion = -1; } @@ -1803,7 +1802,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, if (matchregion == -1) { /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); } else { uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); @@ -1818,9 +1817,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, xn = 1; } - *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn && !(pxn && !is_user)) { - *prot |= PAGE_EXEC; + result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap); + if (result->prot && !xn && !(pxn && !is_user)) { + result->prot |= PAGE_EXEC; } /* * We don't need to look the attribute up in the MAIR0/MAIR1 @@ -1833,7 +1832,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, fi->type = ARMFault_Permission; fi->level = 1; - return !(*prot & (1 << access_type)); + return !(result->prot & (1 << access_type)); } static bool v8m_is_sau_exempt(CPUARMState *env, @@ -2032,8 +2031,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, } ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, - &result->phys, &result->attrs, &result->prot, - &mpu_is_subpage, fi, NULL); + result, &mpu_is_subpage, fi, NULL); result->page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; return ret; From patchwork Sun Jul 3 08:23:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586803 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2914450mab; Sun, 3 Jul 2022 01:35:07 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vfe3QVR9yy1j9yXmDhtiuVSYPntR2eLOi5q8A5FykWdgUuBkBFbRJo/1GkxruDjrpyG2P5 X-Received: by 2002:a25:e211:0:b0:669:9cf9:bac7 with SMTP id h17-20020a25e211000000b006699cf9bac7mr22910287ybe.407.1656837307360; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 17/62] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup Date: Sun, 3 Jul 2022 13:53:34 +0530 Message-Id: <20220703082419.770989-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This can be made redundant with result->page_size, by moving the basic set of page_size from get_phys_addr_pmsav8. We still need to overwrite page_size when v8m_security_lookup signals a subpage. Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 ++-- target/arm/m_helper.c | 3 +-- target/arm/ptw.c | 19 ++++++++++--------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a817acaaf4..f6a9b963d3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1143,8 +1143,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion); + GetPhysAddrResult *result, ARMMMUFaultInfo *fi, + uint32_t *mregion); void arm_log_exception(CPUState *cs); diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 69d4a63fa6..01263990dc 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2806,11 +2806,10 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) if (arm_current_el(env) != 0 || alt) { GetPhysAddrResult res = {}; ARMMMUFaultInfo fi = {}; - bool is_subpage; /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - &res, &is_subpage, &fi, &mregion); + &res, &fi, &mregion); if (mregion == -1) { mrvalid = false; mregion = 0; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b012577f17..5274d0b304 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1697,8 +1697,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion) + GetPhysAddrResult *result, ARMMMUFaultInfo *fi, + uint32_t *mregion) { /* * Perform a PMSAv8 MPU lookup (without also doing the SAU check @@ -1715,10 +1715,10 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, int n; int matchregion = -1; bool hit = false; + bool is_subpage = false; uint32_t addr_page_base = address & TARGET_PAGE_MASK; uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); - *is_subpage = false; result->phys = address; result->prot = 0; if (mregion) { @@ -1770,13 +1770,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, ranges_overlap(base, limit - base + 1, addr_page_base, TARGET_PAGE_SIZE)) { - *is_subpage = true; + is_subpage = true; } continue; } if (base > addr_page_base || limit < addr_page_limit) { - *is_subpage = true; + is_subpage = true; } if (matchregion != -1) { @@ -1793,6 +1793,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, hit = true; } } + result->page_size = is_subpage ? 1 : TARGET_PAGE_SIZE; if (!hit) { /* background fault */ @@ -1968,7 +1969,6 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, uint32_t secure = regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs = {}; bool ret; - bool mpu_is_subpage; if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); @@ -2031,9 +2031,10 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, } ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, - result, &mpu_is_subpage, fi, NULL); - result->page_size = - sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; + result, fi, NULL); + if (sattrs.subpage) { + result->page_size = 1; + } return ret; } From patchwork Sun Jul 3 08:23:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586810 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2917733mab; Sun, 3 Jul 2022 01:42:47 -0700 (PDT) X-Google-Smtp-Source: AGRyM1u2jXe1a7/DJGZ9aBe3Q009AUY+CEE8pLndCf7h7W6wDgpr9ytA1m/S8APs9Y+Ho4AF856D X-Received: by 2002:a81:3a08:0:b0:31c:2f56:4fee with SMTP id h8-20020a813a08000000b0031c2f564feemr24750656ywa.449.1656837767129; Sun, 03 Jul 2022 01:42:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837767; cv=none; d=google.com; s=arc-20160816; b=IOXkDfyIyL5375i1OLwN0fEwRsVAa2J87Ck54A7ShzBeWd61DHMarVK9wiHU7p7Lya ZzOEAyC5izWok88s/YGpzRORpBNWrWhPWjdRjmHb4orPfR+ZqeCphk4qVoFpaTxijGcW ljbdeekq9uriESrQW63untcHwxQWXGXIKI6USp/tKrm2rtwDr6ZJG21NBpkaV9UdbK0U 74Z+oeGjnnwE+rN8XJFGTyXsDtI2wI2DuK4LSHg11PkctTLAjuQ3TfeIu7iCdW5ObHOI ziSke+pVIRUIkw9wbS4PICQkzvmnsLZ/AVzjSom22oAJbxaO/rz/o35Xf8H/j8jxhmAQ CKSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zlvoZgbtv2iYgMtdizbSI+TVx/on1gTKhG9DRzhIk2s=; b=M1MiThYEOKP7FOydQj9MUKEJ5tmrTL5gxCVS3RwQlkVIMmcFxlEuXjMK8P/KHOKf8g VE0Gu09oOjgpeTrYWIC1p4TjAHHbSPOfNlvO1nodRSOb65vYlYq1aaS5TFVJvxvHrEAv cTKKNLWRx5La2k2LqhfMRupPCvY6OzZj3S0NqozKdvpPYUFpiWQeHHmie/jwUoly8X/f n0Ft8YOPtoA3V6mGrEPmYzlk9DRdacGQrkdGNiTeLkarUD6XLQLuqlfG9OXilMh7wl6y pBu2VhRg0ozNu8ygo7i7C/wwzKmeo+x/4nYSHibMoM2FJd7jE8McX7vEb/QebbOZY8Sz P7tA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N9uMbgzy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 18/62] target/arm: Add is_secure parameter to v8m_security_lookup Date: Sun, 3 Jul 2022 13:53:35 +0530 Message-Id: <20220703082419.770989-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from v8m_security_lookup. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/internals.h | 2 +- target/arm/m_helper.c | 9 ++++++--- target/arm/ptw.c | 9 +++++---- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f6a9b963d3..30bda00a09 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1113,7 +1113,7 @@ typedef struct V8M_SAttributes { void v8m_security_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - V8M_SAttributes *sattrs); + bool secure, V8M_SAttributes *sattrs); /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 01263990dc..45fbf19559 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -689,7 +689,8 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { V8M_SAttributes sattrs = {}; - v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); + v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, + targets_secure, &sattrs); if (sattrs.ns) { attrs.secure = false; } else if (!targets_secure) { @@ -2002,7 +2003,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, ARMMMUFaultInfo fi = {}; MemTxResult txres; - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, + regime_is_secure(env, mmu_idx), &sattrs); if (!sattrs.nsc || sattrs.ns) { /* * This must be the second half of the insn, and it straddles a @@ -2826,7 +2828,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) } if (env->v7m.secure) { - v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); + v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, + targetsec, &sattrs); nsr = sattrs.ns && r; nsrw = sattrs.ns && rw; } else { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5274d0b304..3b70c423a8 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1853,8 +1853,8 @@ static bool v8m_is_sau_exempt(CPUARMState *env, } void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - V8M_SAttributes *sattrs) + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool is_secure, V8M_SAttributes *sattrs) { /* * Look up the security attributes for this address. Compare the @@ -1882,7 +1882,7 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, } if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { - sattrs->ns = !regime_is_secure(env, mmu_idx); + sattrs->ns = !is_secure; return; } @@ -1971,7 +1971,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, bool ret; if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); + v8m_security_lookup(env, address, access_type, mmu_idx, + secure, &sattrs); if (access_type == MMU_INST_FETCH) { /* * Instruction fetches always use the MMU bank and the From patchwork Sun Jul 3 08:23:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586805 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2916364mab; Sun, 3 Jul 2022 01:39:15 -0700 (PDT) X-Google-Smtp-Source: AGRyM1u7X7FOYwxwm5dxWjQY4ClhU210F4zEugZ6r3ScvEMC53qLCGSWBrvOoFiyG+DKqWV/q5FG X-Received: by 2002:a81:6e88:0:b0:31b:d12d:4ed4 with SMTP id j130-20020a816e88000000b0031bd12d4ed4mr27492120ywc.187.1656837555636; Sun, 03 Jul 2022 01:39:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837555; cv=none; d=google.com; s=arc-20160816; b=ObERIZYGJjm+pyq8WXbkygqa6vRwhl+cI4bVQr+JkbEu7SpqEwM1VXiM4WkHxrK4qj xLobHXWb9lOSiOTNU5BZLF8AkkS3oC1FHvEY5eP6+CZkpsvGvtArTEaao0MoqkYTJAaC jMfqR9myYIBmOziWpzIPa/Obm+Of9IQkJeMeQaUJB0FzRMZBC/xK4LTkj41doW5x6MtD 8UiEG6gwlwdjS3qT/db3v/v5z5o1Fd3gmuHKnmEjP9/d3bTTcpfwen3UWnOWigEb9s3w r1hwnkDw41DMd5If3ITFQhG1LrwQmrsqOKkJz3m8MnexepcugeDhrvTRVxSgVXhlZpAD raQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LaYP+2o95zy27QHmyX20UD82IAVILTEsp61gOqT10lM=; b=GgLcuFSvEkRC1aiS6M0EdCHWG3rNwZILXlMfBD869WIMkcIo6ATpUoYpPDpLS1Br+T h0QwFdpbCFMOR62mF7yhprX2JxHdO0G54Nyus3u1Topj3XSPnhsOuTwoznDE2VvkzSWE l2m72DgiIlLlI66PPvGsDCfJhUZfoT6CzutMO+r3N5smDYxOdXH9pkdIFinE4UqHvwHo 8mzghh0B1ttj80EkbtqhDWjA1Lq3s3fiyJaUy4YHTY78SYJzK4+rAEk/Flm3PjmZrwsS P4Fz08k/lCADxmZj+3sVsjYwiZqSEc7GKMk0iNarbQHSgWGMIwaDWMv+qY6ER3t1HpZu UsRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KChJYuAu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 19/62] target/arm: Add is_secure parameter to pmsav8_mpu_lookup Date: Sun, 3 Jul 2022 13:53:36 +0530 Message-Id: <20220703082419.770989-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from pmsav8_mpu_lookup. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/internals.h | 4 ++-- target/arm/m_helper.c | 2 +- target/arm/ptw.c | 7 +++---- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 30bda00a09..f75ac2e1b7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1143,8 +1143,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi, - uint32_t *mregion); + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi, uint32_t *mregion); void arm_log_exception(CPUState *cs); diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 45fbf19559..5ee4ee15b3 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2810,7 +2810,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) ARMMMUFaultInfo fi = {}; /* We can ignore the return value as prot is always set */ - pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, + pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, targetsec, &res, &fi, &mregion); if (mregion == -1) { mrvalid = false; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3b70c423a8..1a0e708d11 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1697,8 +1697,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi, - uint32_t *mregion) + bool secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi, uint32_t *mregion) { /* * Perform a PMSAv8 MPU lookup (without also doing the SAU check @@ -1711,7 +1711,6 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, */ ARMCPU *cpu = env_archcpu(env); bool is_user = regime_is_user(env, mmu_idx); - uint32_t secure = regime_is_secure(env, mmu_idx); int n; int matchregion = -1; bool hit = false; @@ -2031,7 +2030,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, } } - ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, + ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { result->page_size = 1; From patchwork Sun Jul 3 08:23:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586809 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2917657mab; Sun, 3 Jul 2022 01:42:38 -0700 (PDT) X-Google-Smtp-Source: AGRyM1v1QdmvMnv6Cb6PaiGJ+2GhHLCFJdvwNMLLreaBA9J4+kAGzFIT8QU0gFmfXaU/iFK8OrOl X-Received: by 2002:a5b:e92:0:b0:66e:3583:8b8d with SMTP id z18-20020a5b0e92000000b0066e35838b8dmr2230091ybr.276.1656837758640; Sun, 03 Jul 2022 01:42:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837758; cv=none; d=google.com; s=arc-20160816; b=JuMXriDkgAxtwMvXwErnqHbmxAdsrT2CHVo3MmvKwFcvZ14t+uGN+dBUrY2MNZo7km NC+dhwKvfYrdwe7yTzfd3bM5NKgApj5F1AA+5O+0EL4sf8N92NX8aLyKNNJLGJTmk0ka Q0DvJ9JEc36a1mozXuDn0IkhYp3HV9DxasZzRZgapXYWvETV0b2TMfWnY8MsjcCJSul7 IgiS2gLY93ZQfttxe8HNZ3xLnEqF/r4YhG8NK5tbTFGdXpe5mznOT3SB4uT/eaF/D/fl fv+gidlGtLIJY++wIn55fntoksxbF9E+bHLHjo24BXIVzGo3oDriMT5xRHUzEkvT9eYs kHcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UvRs/fI4qqQtxbNs3Ld/tro7HQYE0RTJrbm3VX6tYyA=; b=tme09B1ilZUowyDrGAF2jKKzDNTv/krtjISh14SadOeHDVBnCfcv6M7CKUP1pxUvCu MAoDlhB8shK20VvyJU+vZxIUqafaJIlycbbqGfjrGHpGRQe8QuiCdjIo7PZpmTmb/iNb PcpAGU7709UaxZga7s9mZQLM8B1tCQEJuMBCkXdyjZBCaZex5C/DE8R4uiq1/MAzNBMP FPml0GUUbWgQ99DYjbsJTjaNHCKJpUaBpNZJIwCmzwFEn4NqWOaepZAJnKBFj/bzoKE1 pIiStC5Ro7KIkGZETn0tIXrWa8qq4C5l47uEJPbKK8Q9j+/+EDzlleID0z1Sup/tbnjL WKvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Crkcueic; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 20/62] target/arm: Add is_secure parameter to get_phys_addr_v5 Date: Sun, 3 Jul 2022 13:53:37 +0530 Message-Id: <20220703082419.770989-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from get_phys_addr_v5. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1a0e708d11..1bef9c6c60 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -410,7 +410,8 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { int level = 1; uint32_t table; @@ -429,8 +430,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, fi->type = ARMFault_Translation; goto do_fault; } - desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); + desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -468,8 +468,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* Fine pagetable. */ table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); + desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -2509,7 +2508,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - result, fi); + is_secure, result, fi); } } From patchwork Sun Jul 3 08:23:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586813 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2918866mab; Sun, 3 Jul 2022 01:45:11 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sJjT5AdxNPR6Pkir+gn9Kmjbb1dUbJfbBkoDmGO2ZpTw16h7yrKFkznH0ER1vbeCn+TmTv X-Received: by 2002:a05:6902:2cc:b0:66e:3562:608 with SMTP id w12-20020a05690202cc00b0066e35620608mr2211907ybh.461.1656837911183; Sun, 03 Jul 2022 01:45:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837911; cv=none; d=google.com; s=arc-20160816; b=xY0kuVAU8Pq2HOLaD2X9tJEpvG0WLRtkSPDh/ElhtYYXnBYOxeVypf4mn/gQbzzmR5 jWMKfmwmo4/eyvustZWMvWjBg5JwWwHQ57hG8k9mDo10I6GPTCGepy9jJt887uxaVk2k jJBDBhbYPXDQ/qa2DQuTg7oF25PaAZNlekdwJI3elY/KnOJFjE+kkOQatlY1I0A4KDXL Gsld/SfjSjMAx6iRYUKSpVPgxqjEcbEg9igVwEJwDYLoJ8QaDal8NwmqUF9RLQ5foOEF 90MLPjPYHb2k1ie20BJxPh6t9HBcNja/tb+XHTXgcLnxI/En5xOnJk+7DQPamlAv8QT/ JoHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2QgifQ8/UXpFYLo0AlrMI1Z36M4FSsNZYn7tIgKAL9c=; b=StFIqA6+YtsICBV772FlIWs+LiMWMkKebGO84fPfMD/zOzt94BYy08lWdKtbk4Kt5M WQPZSYrm9LkBFfQM7OUbaqzp2FtfQ80jgYQIWkBEJhyJRAqwAM51RZD3JFH/yM4WEY7D 2OJJG2xdmRY1msezA1a//ZXsx/o5QpC67qFqswCcHQC3rct++hxmRlBTHs+vbiy7eT0u Dj/K1JIfuuNUR9y56fMH4yyg0QG4zpQKsd8aZ6bHqQ1t4lMwufkjCmcDi8Jg/Oq6iuo8 f+JqXZewFUtanR2TvBm+Tm36O3t1wvWno5kcWtcBTS5wenEwDdPyDm3fGbsfEIb/VBFx SKeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H5v4vily; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 21/62] target/arm: Add is_secure parameter to get_phys_addr_v6 Date: Sun, 3 Jul 2022 13:53:38 +0530 Message-Id: <20220703082419.770989-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from get_phys_addr_v6. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1bef9c6c60..d424dec729 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -529,7 +529,8 @@ do_fault: static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int level = 1; @@ -552,8 +553,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, fi->type = ARMFault_Translation; goto do_fault; } - desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); + desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -606,8 +606,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, ns = extract32(desc, 3, 1); /* Lookup l2 entry. */ table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); + desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -2505,7 +2504,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - result, fi); + is_secure, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, is_secure, result, fi); From patchwork Sun Jul 3 08:23:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586817 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2920674mab; Sun, 3 Jul 2022 01:49:10 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vh3uE+1GFN7WEOu2IJn7bwJpQ2LSqSzykXntAwXIJ6PQ5e0eM96O0XJ+XUQUXyfhtp2JIW X-Received: by 2002:a25:2d1d:0:b0:66c:a759:e79a with SMTP id t29-20020a252d1d000000b0066ca759e79amr23820089ybt.515.1656838150010; Sun, 03 Jul 2022 01:49:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838150; cv=none; d=google.com; s=arc-20160816; b=coyfXpIITXN3fN6+Z5jC4PfoWAHeW6CiiWYSLVgzvmFd87xOplse5oWyRHo7KWdf7t u+cV0i+le5QI3jwUcamuvtIvuitBcopvY/tv7cpDyTkZgqFnBo6/OPj7nro9p5qA0IEW +4GuBMwl2Z2jQjC1fqEeGGh9/XXYy1QvAvDZa3QMkreFAgHtrBGdaqGPJ9BN4Arypn7a 6y6J1IUwB+6VnOwj1JoUwzO/HNJY2zm6PRFDZIQBDP9D9Aj7ka7cSYrAkrDTpviWHvT1 hf3+Z6rhMeXDK6kQrrH0N3IOotwYA1C8ibw8PbrDljGVVY6XTmaVhDpv/htLHFimHDPY a85A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GMzc8ik2WaalfDjtAiTiJK+N4oOIk3ZEdYeq0p1CiQs=; b=NSxlAnj/8BXK/Lrs1I3Ql8W7MzB+CMBZb2NiB14txEU7YjIr0yV5QxZIJYvGrsTQ91 LPhWXiJBTJll60uF20yn1tfLgWzIKIlmKktywomzmu1m5INceDG6E/WYzYPJZjLUFRGS Els7tUdYgz8r6rPVt/cfNANAPRTI2StFMxNu/Rq0BJvM4/F1GkrSAJOmf/9R/+jzXk+d KCOijObO05zEdeviL44Fpzej0WpL/YbIF+8ooJS4RwaG/csvlHt8DQF7mqNYQzyjTDF8 8ic8AZhfXoAt/hNbw8VydPvtI5jlgeSVokSPMrLg7L9+GnXIE6+Ep69CHsr49O+anDjR AP9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pJZzEUNh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 22/62] target/arm: Add secure parameter to get_phys_addr_pmsav8 Date: Sun, 3 Jul 2022 13:53:39 +0530 Message-Id: <20220703082419.770989-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from get_phys_addr_pmsav8. Since we already had a local variable named secure, use that. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d424dec729..f7892a0c48 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1960,10 +1960,9 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, + bool secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - uint32_t secure = regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs = {}; bool ret; @@ -2408,7 +2407,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - result, fi); + is_secure, result, fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, From patchwork Sun Jul 3 08:23:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586806 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2916401mab; Sun, 3 Jul 2022 01:39:20 -0700 (PDT) X-Google-Smtp-Source: AGRyM1se6fMPzx9y1Lu4/6z5k60g+ABBPRkB8K2cmT+4HROyspda6CkIqv7utoasEQXT3K9sP/vO X-Received: by 2002:a0d:cb13:0:b0:318:39b9:89fc with SMTP id n19-20020a0dcb13000000b0031839b989fcmr28016358ywd.413.1656837560336; Sun, 03 Jul 2022 01:39:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837560; cv=none; d=google.com; s=arc-20160816; b=ellrkxuqM3lTKSXM5KrHrmXqByUMyUZlawqz8E7/Mx/i3kZCY34GruIrMQiIGwRg6W wVuEJnMPO4f3FujduHEAHDUAiME7nDRN0zBivjmPt1CugMV+5n7fWQZzBJgyUmScrZsZ b6H3kY/SzOpJdMF7ljnbMeTT+NXqjMlOOEeimskIYn9o2YpOSLEOK03JubZeikMBubZF sPl28K+wI9fGzpBmwp9GSk5AkQ+5P/M1KRQdAWVmGHEL/9qGdTbyAhI4Jr/FPKxctJ+U PAig0Dzd4wbPyv21BEZpWRe8IcQMiEF+B+vFqGaBKxPyrANd90pIh164MF+SiDkappq8 eJGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5cg/L7Tmrf48Jc3I5pInXguHqlazi2G1pFqTrme/O8Y=; b=p8O14CvrLKw2MpRBuWWJOgtcitonLDavV1R415Wr/kl57KCl/EFxNEJsmP1C77Pe1z UpwYY/tD6GjBQCSmAltrhv1AIe8Tnjs9KVX2KxzjP8tLpGwVK6twLSxdOMuFaa00IjYh JCseMDS8ul8Rg4yavQhXw00gZAUkqhXiS/8GBZjvkl87Igg5yizvPXXR78l5UT4f8GvJ MBHblqvRCzMQiQsgaCBulVS/kPPKAheaZHIhL+ucxAM6ACvZFi03SQduD8STOZEaFyur DlYJ6oQv+UEOemwMA+fBsn0LImN09T5A7G/Tdzgtn2m55PHhMseXsA+OnRmk7mG6GBzF 6QVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R4FWNolk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 23/62] target/arm: Add is_secure parameter to pmsav7_use_background_region Date: Sun, 3 Jul 2022 13:53:40 +0530 Message-Id: <20220703082419.770989-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from pmsav7_use_background_region. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f7892a0c48..23cfccce6c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1485,7 +1485,7 @@ static bool m_is_system_region(CPUARMState *env, uint32_t address) } static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, - bool is_user) + bool is_secure, bool is_user) { /* * Return true if we should use the default memory map as a @@ -1498,8 +1498,7 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, } if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] - & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; } else { return regime_sctlr(env, mmu_idx) & SCTLR_BR; } @@ -1512,6 +1511,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, { ARMCPU *cpu = env_archcpu(env); int n; + bool secure = regime_is_secure(env, mmu_idx); bool is_user = regime_is_user(env, mmu_idx); result->phys = address; @@ -1614,7 +1614,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } if (n == -1) { /* no hits */ - if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) { /* background fault */ fi->type = ARMFault_Background; return true; @@ -1734,7 +1734,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } else if (m_is_ppb_region(env, address)) { hit = true; } else { - if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + if (pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) { hit = true; } From patchwork Sun Jul 3 08:23:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586814 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2919580mab; Sun, 3 Jul 2022 01:46:46 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sY1XLFfmsID0KLmmxjKimyKhRY172tJVdBcVMz65MsB2leZtha6nT7ZF3oTSYLmhqO1ClC X-Received: by 2002:a5b:1d0:0:b0:66e:1f73:ee62 with SMTP id f16-20020a5b01d0000000b0066e1f73ee62mr7328874ybp.249.1656838006758; Sun, 03 Jul 2022 01:46:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838006; cv=none; d=google.com; s=arc-20160816; b=lfo+KBmiZAnL55rwHB79Fhs8MMan2QrkO6VZNJ62U8r/61j8aQfYoPBVgt/gx+LD2y +5SlIZxxrwrqChFo0TzXf+XZcrHevysqVeTTZefyilEhP8i+BMiba8ptjpO28aZpFDiA WvtEHIRHodIFZttVl2xYS2weUG23qJ4nOchDoTMW4nYxsiY0DKDUEtqWg+Kpl4YenfL/ w5mMfZ6Kk8zUptGDN3PLxRHwFvMD7jFcCZuSgt2qhqtYiIX3bYo9hTwexdQm8y3d/f7G 0SgqE7Yhtx7POuKgXsMbfsTQHq/WK+ljbaIpw0mTOoRWYcvJgvVhF7OvpIB8zwUEOShx vLBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EzCzj0W0FC9zsZchyEyMQYjih3KhzZw2NYS2mL3V7Bc=; b=WF+9lemFM3FS7Ame0sLl8FQA3ZaHGujbPE6886EnGwSt0510220tTgtsQ7FC1yX4RP NK70OVuaTa5eBt5sT4jQptTZPq0Q4q2q67MGyjJaxHmNvKInLIeYtw5Y4Xt1L7uHEtcF DSvrNsOLpbE49uEeVTyU+zyWTllERT8SGNWOZgEZBT/n0W5bODqvCr33rCAZpuJxzAJl H4SP+OV64haJwH9iSg8o78yqOSJwDVUFM4E3LiqZiUJXOT34Iq+4DrYM3DkggidcSPZR oef0QZrGUu3Jl1EJhCuR8QmCVOsemupWjx6tjbV/tuKXsAnJ6+ZkPOWb2+TATpJqISiZ 49TQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pxBuHiZe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 24/62] target/arm: Add is_secure parameter to get_phys_addr_lpae Date: Sun, 3 Jul 2022 13:53:41 +0530 Message-Id: <20220703082419.770989-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from get_phys_addr_lpae. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 23cfccce6c..b883826643 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,8 +16,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool s1_is_el0, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ @@ -207,8 +207,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, GetPhysAddrResult s2 = {}; int ret; - ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false, - &s2, fi); + ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, + *is_secure, false, &s2, fi); if (ret) { assert(fi->type != ARMFault_None); fi->s2addr = addr; @@ -961,8 +961,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool s1_is_el0, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); /* Read an LPAE long-descriptor translation table. */ @@ -1179,7 +1179,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * remain non-secure. We implement this by just ORing in the NSTable/NS * bits at each step. */ - tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); + tableattrs = is_secure ? 0 : (1 << 4); for (;;) { uint64_t descriptor; bool nstable; @@ -2331,7 +2331,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, memset(result, 0, sizeof(*result)); ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - is_el0, result, fi); + ipa_secure, is_el0, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -2499,8 +2499,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, false, - result, fi); + return get_phys_addr_lpae(env, address, access_type, mmu_idx, + is_secure, false, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, is_secure, result, fi); From patchwork Sun Jul 3 08:23:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586822 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2921886mab; Sun, 3 Jul 2022 01:51:44 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vAPMbtzCla7Yx9zqWv+x/e0leiFMtTpQoUMwc9eCwBLbZJq6BCq9svQZKuQM7ZqFi6VGCE X-Received: by 2002:a25:9904:0:b0:66e:2b64:763 with SMTP id z4-20020a259904000000b0066e2b640763mr5268942ybn.210.1656838304125; Sun, 03 Jul 2022 01:51:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838304; cv=none; d=google.com; s=arc-20160816; b=NQngXOLpeDl3RUfhOmUCfiRUOJAg+d22rK7bpuqcevPlTEICKSxUp/HK3AxOkcgdkP QXdYmVLrChdGUnz0Wek5GzgHTes40kdBj5uIu4XOr1h8A4sZu4WCl+8k2vxIaWmAOC0H NzuGx7v3jaB2iv4Y5ChyOFqk7JNATAbSUFps+xwLRxhT7i/wdHMkV/UkzWi1hHWUOEfu k79IBkJaGBqXtdLyHkC6WkHlGWi+XHy67TS/m7FD8HHroJ5mGES25a5zOKC4zH5JmTxN r1ngfAd4d7DS8KiRJSvK0CSVRqPW3cwj1QTjXZWpTrl3dKTJ4DPUl26LvqL1Jy0lB+4q D+bQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TKxPLdADuP+9Wny++zRwM0SIOJMxWQvaLP+5vkpY9No=; b=G5Bz5vmgUcPPtQBwIepWzjRwWXbrTDkFvVaKt75vAfKxcvXLRiiiB8W3bXFgoHrWFb I1yQApZ1NzKjBugym3alsunrwuMy81FgddA0JOIuCLYUNKz0zXZZd0VQ2Q0jKnUBlmng KcI0zo8H57EAmep389osnrC3ciMsCnJz49U0nS6xDs0hwZ1g3sFAdJKXYaC0hlndHaUF L7k8ajus23JHd7DtLLed+CHzXlBJh9HZ/uflOJF3RqUpDPpxtguxJmDIIkkE971psPYc 4NlNqUusGXbEVb96xF0kqwKSzbz4YjxlbrgPv7Mdw4Jow+bE9oJmsSbFek+IZiFN4HNQ BQQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b9pIIYQV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 25/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav7 Date: Sun, 3 Jul 2022 13:53:42 +0530 Message-Id: <20220703082419.770989-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from get_phys_addr_pmsav7 Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b883826643..33fa8f094b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1506,12 +1506,11 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, + bool secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int n; - bool secure = regime_is_secure(env, mmu_idx); bool is_user = regime_is_user(env, mmu_idx); result->phys = address; @@ -2411,7 +2410,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - result, fi); + is_secure, result, fi); } else { /* Pre-v7 MPU */ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, From patchwork Sun Jul 3 08:23:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586825 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2922807mab; Sun, 3 Jul 2022 01:54:07 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sTRo4impwOsPlX3fEufvI4MVNfPur4rjJxTM2sAZhObojDta7RKDfWwD19VMVVA6xKk/Uu X-Received: by 2002:a05:6902:1002:b0:66d:8e44:1abc with SMTP id w2-20020a056902100200b0066d8e441abcmr21159301ybt.178.1656838447638; Sun, 03 Jul 2022 01:54:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838447; cv=none; d=google.com; s=arc-20160816; b=Nzti6z3IsvC1BYRtEPfH7K6+i7DE/R6bLpBLvA7e049jZR2WRkPYX8SG0fmnSYo81d mfJ6v5knmPDyvtM+20yv0dH1V8j2Ez4u9sSxHm6j/dfDQhA7bp0a5QcDTG6BuQQkU6vO uxekrrsocOHoHEqsQ/R9lFP9S5Gw1ZP1AqM625QlWfWhaXAUT/6SZnwLh2WnJGNS93hm xljTNi84OFGz0rkVmhd/hvX2FSBjfgSZgdOK/vbno6xq30NmNEbNyrysikgavC7Tq9Cr 3uROsOdK+98CM1F4SFixl5jfPVY9u0iJWt1V/CF+t4ndBl6MiGtfQWAFfoVAcn9Tk9tb oUxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Rkur50bTtgiL1BQusxIr0ufhiN00akHEytOTXsqW27E=; b=Wf0x2TQz+lCGRnVvV3jlg52aWo3hHK4N2W6yUBuWXIKreAj9VGVNmnG3BVQq0Ex6jP fK/nZmkE9w8xQ3TJiKijrEJ8GhYvSqCfSywjFcgQy2qL7sXs1Rcu2zHIE17/h974sLmk /cR3LiKMaTFFBenY6AIVPlsKuV2QU1AR1KnuqBHwXe5DcL14Kn1wNNqrUmdhOg+iAuxv /p38hA7ouXM9/09dm7ek/zTjpvWQfLjMLZpk8/mE0cuzDLvKn32PaUK5HUbs6GhXNejv 9edniG+Hm57vEm6AEu0zlOQibAmWkN2SPdCPi1sEnnYIqOUOKkBES26E4CV+zf0JId+b zRjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GPy/VTF2"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 26/62] target/arm: Add is_secure parameter to regime_translation_disabled Date: Sun, 3 Jul 2022 13:53:43 +0530 Message-Id: <20220703082419.770989-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from regime_translation_disabled. This fixes a bug in S1_ptw_translate and get_phys_addr where we had passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if Stage2 is disabled, affecting FEAT_SEL2. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 33fa8f094b..8313a2d74a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -131,12 +131,13 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) } /* Return true if the specified stage of address translation is disabled */ -static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) +static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, + bool is_secure) { uint64_t hcr_el2; if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & + switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -163,7 +164,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { + if (!is_secure && regime_el(env, mmu_idx) == 1) { return true; } } @@ -201,7 +202,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2, *is_secure)) { ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; GetPhysAddrResult s2 = {}; @@ -1351,9 +1352,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, int n; uint32_t mask; uint32_t base; + bool is_secure = regime_is_secure(env, mmu_idx); bool is_user = regime_is_user(env, mmu_idx); - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ result->phys = address; result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -1517,7 +1519,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, result->page_size = TARGET_PAGE_SIZE; result->prot = 0; - if (regime_translation_disabled(env, mmu_idx) || + if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -1728,7 +1730,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabled */ hit = true; } else if (m_is_ppb_region(env, address)) { hit = true; @@ -2303,7 +2305,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, result, fi); /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, + is_secure)) { return ret; } @@ -2431,7 +2434,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, /* Definitely a real MMU, not an MPU */ - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { uint64_t hcr; uint8_t memattr; From patchwork Sun Jul 3 08:23:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586818 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2920961mab; Sun, 3 Jul 2022 01:49:39 -0700 (PDT) X-Google-Smtp-Source: AGRyM1v5ZI428ildQJXcX/2qKXVHqQ8FgGZCFZWysFZ95XIYx8c2lB/QDBiD1ih9Ay1jFFK7b0r4 X-Received: by 2002:a05:6902:301:b0:669:40ba:a754 with SMTP id b1-20020a056902030100b0066940baa754mr25676328ybs.470.1656838179328; Sun, 03 Jul 2022 01:49:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838179; cv=none; d=google.com; s=arc-20160816; b=jGdSSLQfEMDCH3cnaKqU7R192KD9PUcaQa6cfIuPKYSjMxXdZeUOaVhWA+NBIuwQWK N6IO/2D34Esl6JEcAfPBPCTMm/pfxDdNrAIxsprYIWDIvY82/bOiVhYQUOvNednTGpA5 fxGT1fTgJSyiKlDLN4bGNfpJhz0ToRe6BHMtEbEufGCYtrdF6eU52xnIGi2smXtPL7Wl IzY6NVauPt24dqr77BzJcXxyIYJ2Z3NYRAxMsong8/w9aWIIoTPhebX0Xj5fsTJ7luOU xFUDcbMj4+rcXXTlKL4hc8xbdm9p5ossT1BxQxGtjhpJMPgEA+dVhl0/oG4z2U7xiuzu Ao0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=f33EhXDWkHjxsmDh1J20IKySocqOzXPOfiocCVykyDU=; b=nx5vbOZ6+dC3Be3j8ZFUpA8GMEJKXkHTQ8g/3mQqW9F0XVcvRKmwsb8UfdLSZJpY3Y 2iVjgOhcwCVrzlMqToCI5O58eYbJx0XHvtR9bTCYw0W5xxaQ6UPtEyr1oiuYTS0Wharx gUjJbsuEZAfhcMmJ1B9jfkjb+unXEfbwhTKhIoJcddnQrDc6rcE6HoJ10Vt9Y5j6yzJm YgITGBz3D0ADPG7mwRI1zjI8o8PesQrZEOpQwosOkrXVS/F3m76jpJ67Uw5bVWc7gG/N l/85Nl3P6LTiPEOwTK0WOoAVNEKt4pNq10LxkqT3bTAMtYReLppS3Fskzn4tcGNozzFD PrDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lq70iUy0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 27/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav5 Date: Sun, 3 Jul 2022 13:53:44 +0530 Message-Id: <20220703082419.770989-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from get_phys_addr_pmsav5. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8313a2d74a..340f73997a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1346,13 +1346,12 @@ do_fault: static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, + bool is_secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int n; uint32_t mask; uint32_t base; - bool is_secure = regime_is_secure(env, mmu_idx); bool is_user = regime_is_user(env, mmu_idx); if (regime_translation_disabled(env, mmu_idx, is_secure)) { @@ -2417,7 +2416,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } else { /* Pre-v7 MPU */ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - result, fi); + is_secure, result, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", From patchwork Sun Jul 3 08:23:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586823 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2922052mab; Sun, 3 Jul 2022 01:52:03 -0700 (PDT) X-Google-Smtp-Source: AGRyM1s2b+94zUX70H/A5XfT4w+c8J9EAW99ShXUy7iJaRrx5Dvax2wk+VF04bas3GWIAGpMZGMN X-Received: by 2002:a25:d381:0:b0:66e:2943:1c9d with SMTP id e123-20020a25d381000000b0066e29431c9dmr5555350ybf.67.1656838323156; Sun, 03 Jul 2022 01:52:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838323; cv=none; d=google.com; s=arc-20160816; b=tTiltTjQ44z0zRI8re/+bQvN/nI2iKL4262sn4mYsyxvfK75XbfBpaTcD0bMoFJHQJ 3Sc/8L5FgbmJB+IEwU7A6OxcC8zVkkfbxISwS1/p48yRTDBWmqsmGs0PP6sq77BBgSrg fxJb6puWABAgQAjrNxdeHrWLv5nBbhOtD1ttUlOS8VX17C7mkzGnbu8uVcLVh72RmKnu q0nnsz8KPTOwgHql1jJASjQVhgoVK3pOc9QMt/OUt4ZSLmrKxa1MXJogGbplEQGeTNKy Jm8MlZ1FVm3L5xZ1OCoEd7AIwQgJJqhFSg1gWi97XWnQpoJJnFKP6M3Lxl5U8KW2rkwt tVHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HoZLv2+HUiSgRn8yhxEf96NQZLTisYlzO31dNJIvCns=; b=nIH6qNwp0yZrd/LOZEShE00oGd5opdMVeIMJyYwMlzWiEaCFtXPYNcOFfUASOT32kY 0FLwJCimSbNdDEPmsw2vayokkakQ1pgrFKHFs7PLjFdBSOapwL78BbUPzCNX2u3BZt2r cFtw1puA4cpNRySLRAFFxFSyo90kfas+AG4EmcQXwuC4BeSa/yaWDCl0WY6PNwC72SLD Mhg0OgWYkkZ6FJbUFYHdUgGiCoMDqpkQ+loZ5igZtpJp+r9DWukx8P9v4f0uUDYtddci gabzQIZRfjJLzdaV8ZSyIcdU2trzlVmBJBSDjSIFtgGHojbwJecWEj6us9tEEXqkJi/x lkxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F3xXxFbS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 28/62] target/arm: Split out get_phys_addr_with_secure Date: Sun, 3 Jul 2022 13:53:45 +0530 Message-Id: <20220703082419.770989-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Retain the existing get_phys_addr interface using the security state derived from mmu_idx. Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++++++ target/arm/ptw.c | 21 +++++++++++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f75ac2e1b7..81c386ee15 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1136,6 +1136,12 @@ typedef struct GetPhysAddrResult { ARMCacheAttrs cacheattrs; } GetPhysAddrResult; +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) + __attribute__((nonnull)); + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 340f73997a..b25e3a8c87 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2279,12 +2279,12 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, * @result: set on translation success. * @fi: set to fault info if the translation fails */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); - bool is_secure = regime_is_secure(env, mmu_idx); if (mmu_idx != s1_mmu_idx) { /* @@ -2300,8 +2300,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ARMMMUIdx s2_mmu_idx; bool is_el0; - ret = get_phys_addr(env, address, access_type, s1_mmu_idx, - result, fi); + ret = get_phys_addr_with_secure(env, address, access_type, + s1_mmu_idx, is_secure, result, fi); /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, @@ -2511,6 +2511,15 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } } +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +{ + return get_phys_addr_with_secure(env, address, access_type, mmu_idx, + regime_is_secure(env, mmu_idx), + result, fi); +} + hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { From patchwork Sun Jul 3 08:23:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586827 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2923623mab; Sun, 3 Jul 2022 01:55:51 -0700 (PDT) X-Google-Smtp-Source: AGRyM1se3MvdLWzNqq+LZdTIseoY9HFUpRjWB+8bqOdPvcOVXXq7yt0NPNgjOc1n495Iy0P0fRBN X-Received: by 2002:a81:4bc7:0:b0:318:3409:27db with SMTP id y190-20020a814bc7000000b00318340927dbmr27925704ywa.414.1656838550934; Sun, 03 Jul 2022 01:55:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838550; cv=none; d=google.com; s=arc-20160816; b=CRXvYxJwDUhVjO93sY7Al6AX0DqA35C8r3OqJBxH/h0mYtZ1W0vaYQUvGKRX4qjcmy x3ka8bd0WGkHgPC5WqSuC4X5iANNAc5RyGNwfsI1TxcwfMWIXf8tnUPT3cMGcnDWBE+F +e753wZX11tYHuNyC6OxYojRaKscm4vqh5p85kNNGeQPvUA75KnsVoNn+Zhmo65r4yuD T5dVv/xBUnDhyQaTU75p0vWJTETfcEKhcnX/JL+NXjRw7A6VZTo3AEc5s49LnYum9uUF sXJYK9Kbq/WnOifuZv1T4vRZOyV9KIVnk0It3IqomNjP5auG+5q+claEyPYjQj+3fU6G gFWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nKGjUZfBkhVbWA12ORMzUOT3YB96l6xmhnKiB3/6fQo=; b=gjJIfAEEEoZfrEZQMcxaRtDp0awJ3lOWH2P7fORwKonE09OLSDtVo3NjRLO3QwoE9R T4hKu5AleElf+5zaQifUI+QqJylRgF/zRyXYE8zUz+qRjBzjZWKP9fnDPlXA3QQ1NXOK B3tgeRLccedPtWNok1bvW/eunlHc2mG3dtXxJSrTysLPJjM+GNmfX8L1vdvhYXsN9TLz JYwjVXP8nbNma5F4nMGdhi6cLlAMHW00fxSpCIJlGm/yPdUwZ0jNq1kGrDDxb2WKqB4i /yK3V7f8ig3JMMyyNux/O4uYNa/vnDU1xLs2BSouSNsDJkjkd5BvprhfychqXQgE8QkY 3SBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=agMKJwUK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 29/62] target/arm: Add is_secure parameter to v7m_read_half_insn Date: Sun, 3 Jul 2022 13:53:46 +0530 Message-Id: <20220703082419.770989-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from v7m_read_half_insn. As it happens, both callers pass true, but that is a detail of v7m_handle_execute_nsc we need not expose to the callee. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/m_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 5ee4ee15b3..203ba411f6 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1981,7 +1981,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) return true; } -static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, uint32_t addr, uint16_t *insn) { /* @@ -2003,8 +2003,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, ARMMMUFaultInfo fi = {}; MemTxResult txres; - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, - regime_is_secure(env, mmu_idx), &sattrs); + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattrs); if (!sattrs.nsc || sattrs.ns) { /* * This must be the second half of the insn, and it straddles a @@ -2109,7 +2108,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) /* We want to do the MPU lookup as secure; work out what mmu_idx that is */ mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true); - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) { return false; } @@ -2125,7 +2124,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) goto gen_invep; } - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn)) { return false; } From patchwork Sun Jul 3 08:23:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586826 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2923186mab; Sun, 3 Jul 2022 01:54:57 -0700 (PDT) X-Google-Smtp-Source: AGRyM1s1FksNp6FlLiYKB0XMXuK4izzMxm0TtHWHRjK5S2qmw/zEmOl8RquHrgy1YQM0W+Wyymx4 X-Received: by 2002:a25:8388:0:b0:66e:3afd:9299 with SMTP id t8-20020a258388000000b0066e3afd9299mr1092393ybk.246.1656838497759; Sun, 03 Jul 2022 01:54:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838497; cv=none; d=google.com; s=arc-20160816; b=otriHsoVi5PKF/zEET2UWbJwqh4GxMoZeNR/leq1mvCeO5ttsrEYwyMMLiEzWa9uTC hE4NDJv5yPHqFFoSEH8tCCy2TPt+5s3AGNjNjjQgVyek93nsmXra7MP/u8hF2Obc7GKi mLr1elpDXNWW+ANqeFxzcQk6OEjLXolKtq4bbncblnlLYR99+F3BZb6Y/1GpVDkmR6Jq kbeqnBXZoci/r3G1ZfH/3GkLLGJG1g7UbAZlq3CYKXj/Ijxh35y5yAoaooceGAGODPTJ kQ9ew8CxsNO2KN8Eps7HLaYy/VyWB/vb5Fl+DGqyyYDUKin0+l6Mb+UZ5xp4U9pH4OlP Y2lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ksx6W4Sx5o5nja+lkexLW8pvcoLuTT+mih01KAHBd4Q=; b=sluQHOiaGlltNPxYN0ZT9gcVgnV0JjcgyWnVb1Q1h4e3Asl5w8nfd58zpRBRJ8lx5n Uuv1QhThoh3DWL24xxXW+kFqCFx6YGwedGkuu20KeaLGypaFNN3fxbihNlFWW1nv5/Gh EZEp75b0y07VzB2ctsv6zOCl1EyJHuguI86kRIyvJ6+28P7Ywj3jrvDorlkJmoESR2c4 48Bz9jW/uL8FfNkSar4cK+IQGT7qXsoOGTmWgBn6bj1lLvv6k7mBgjXIukPTh54Mpbhk UP7YkL1ZQFKnwS/NSlS3zdiNFZwi3M6Su1NeXk23dCRyF+NJwcS2yeIEJlvhjbaDdYkg B8gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wZ7H3pKQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 30/62] target/arm: Add TBFLAG_M32.SECURE Date: Sun, 3 Jul 2022 13:53:47 +0530 Message-Id: <20220703082419.770989-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the use of regime_is_secure from arm_tr_init_disas_context. Instead, provide the value of v8m_secure directly from tb_flags. Rather than use regime_is_secure, use the env->v7m.secure directly, as per arm_mmu_idx_el. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 4 ++++ target/arm/translate.c | 3 +-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4a41b5dcef..919e7c27a3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3162,6 +3162,8 @@ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ +/* Set if in secure mode */ +FIELD(TBFLAG_M32, SECURE, 6, 1) /* * Bit usage when in AArch64 state diff --git a/target/arm/helper.c b/target/arm/helper.c index fb13e0f4c0..0908c20215 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11281,6 +11281,10 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, DP_TBFLAG_M32(flags, STACKCHECK, 1); } + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { + DP_TBFLAG_M32(flags, SECURE, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 6617de775f..540ce84d95 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9359,8 +9359,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->vfp_enabled = 1; dc->be_data = MO_TE; dc->v7m_handler_mode = EX_TBFLAG_M32(tb_flags, HANDLER); - dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && - regime_is_secure(env, dc->mmu_idx); + dc->v8m_secure = EX_TBFLAG_M32(tb_flags, SECURE); dc->v8m_stackcheck = EX_TBFLAG_M32(tb_flags, STACKCHECK); dc->v8m_fpccr_s_wrong = EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG); dc->v7m_new_fp_ctxt_needed = From patchwork Sun Jul 3 08:23:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586829 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2924844mab; Sun, 3 Jul 2022 01:58:59 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vghrrbTcruwL3NiwLoJFbFRc+ZRKBgUyeqW46uqJSwnuphet3h+0Rf+hBkMcK4qaeEpFqr X-Received: by 2002:a05:6902:84:b0:63d:4a3d:eb5 with SMTP id h4-20020a056902008400b0063d4a3d0eb5mr24192334ybs.145.1656838739837; Sun, 03 Jul 2022 01:58:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838739; cv=none; d=google.com; s=arc-20160816; b=EPh3mHwq4FEn8KbRQfGfAxcgwG56q/ssVPddPZG/2rjc0pRt4r1h11lxyfbLvUA1RN gIvfN469kzwmZUWwetwZxNlkduipyfO9F3GXyH+D2vjToFqFa6gMUjCRO8oRUhop18LE cytFQNqCFVmStWvJNizzWfTUMdzbK7VfEyjAJXEcyo8gv0nHrcrAf9shGS4AtT8arbZc tIZxTUZuUpj6KYZHz8p42RMkEPgcUHNBxvxP3z/2r0qEun14R7G8ytTnThdYB9OJa+Wq fFi0IRGuqy2LwFfMt6DZabIXGUjyfHL2JPgrY0h3JLrBOv0RBr88yhHdDf/doofjFLnt kYXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UJliRv7SE0glwKqdJ6L5blCFVHOfbsAKHLHPwEgHUps=; b=ylBVH1JKH6A9opbxhkAw5aI+zawItMYmVVTr2ddkiUBWTJOndKEAY+C/tE4dIEdpnI AjM1/4GvtYcYAKgaz5Bocei9DMfCg6CgZ4oxpDsw8yJwz5hYkPATkZ3aZrdEHG8NHURE GlsfDpjKrtDLmauhXmtGPb5yUGVs2PnZDH9S12FrUh90hTaaFDDqizF1lRRqAIlxPoYz H/xfRq+wHwJ6+tydnNYSjdi94xdY1m7H/BJah6tCtjoQd7Z5RJkisXRmG5kVl0qe4VfE cyC9sAtuOFUULJT8Fql0/EBmBrDRg47UAOvNkj1ml96GSvdTGLIRyJdLWW62JU8GvDED jQVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="U+j9d/Xo"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:25:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 31/62] target/arm: Merge regime_is_secure into get_phys_addr Date: Sun, 3 Jul 2022 13:53:48 +0530 Message-Id: <20220703082419.770989-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the last use of regime_is_secure; remove it entirely before changing the layout of ARMMMUIdx. Signed-off-by: Richard Henderson --- target/arm/internals.h | 42 ---------------------------------------- target/arm/ptw.c | 44 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 42 insertions(+), 44 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 81c386ee15..d7062c6503 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -676,48 +676,6 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) } } -/* Return true if this address translation regime is secure */ -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E2: - case ARMMMUIdx_Stage2: - case ARMMMUIdx_MPrivNegPri: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MUser: - return false; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_MSPrivNegPri: - case ARMMMUIdx_MSUserNegPri: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSUser: - return true; - default: - g_assert_not_reached(); - } -} - static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b25e3a8c87..a7c0d616a0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2515,9 +2515,49 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { + bool is_secure; + + switch (mmu_idx) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_E2: + case ARMMMUIdx_Stage2: + case ARMMMUIdx_MPrivNegPri: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: + is_secure = false; + break; + case ARMMMUIdx_SE3: + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: + case ARMMMUIdx_SE2: + case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_MSPrivNegPri: + case ARMMMUIdx_MSUserNegPri: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSUser: + is_secure = true; + break; + default: + g_assert_not_reached(); + } return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - regime_is_secure(env, mmu_idx), - result, fi); + is_secure, result, fi); } hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, From patchwork Sun Jul 3 08:23:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586828 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2924778mab; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:26:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 32/62] target/arm: Add is_secure parameter to do_ats_write Date: Sun, 3 Jul 2022 13:53:49 +0530 Message-Id: <20220703082419.770989-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use get_phys_addr_with_secure directly. This is the one place where the value of is_secure may not equal arm_is_secure(env). Signed-off-by: Richard Henderson --- target/arm/helper.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0908c20215..e98fc75646 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3171,7 +3171,8 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, #ifdef CONFIG_TCG static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx) + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool is_secure) { bool ret; uint64_t par64; @@ -3179,7 +3180,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ARMMMUFaultInfo fi = {}; GetPhysAddrResult res = {}; - ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi); + ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx, + is_secure, &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never @@ -3351,6 +3353,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx = ARMMMUIdx_SE3; + secure = true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3372,6 +3375,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx = ARMMMUIdx_SE10_0; + secure = true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3387,16 +3391,18 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ mmu_idx = ARMMMUIdx_E10_1; + secure = false; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ mmu_idx = ARMMMUIdx_E10_0; + secure = false; break; default: g_assert_not_reached(); } - par64 = do_ats_write(env, value, access_type, mmu_idx); + par64 = do_ats_write(env, value, access_type, mmu_idx, secure); A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3412,7 +3418,8 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; uint64_t par64; - par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2); + /* There is no SecureEL2 for AArch32. */ + par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false); A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3455,6 +3462,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx = ARMMMUIdx_SE3; + secure = true; break; default: g_assert_not_reached(); @@ -3473,7 +3481,8 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, g_assert_not_reached(); } - env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); + env->cp15.par_el[1] = do_ats_write(env, value, access_type, + mmu_idx, secure); #else /* Handled by hardware accelerator. */ g_assert_not_reached(); From patchwork Sun Jul 3 08:23:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586811 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2918599mab; Sun, 3 Jul 2022 01:44:38 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tWSOYugy3818Ky77HwO5wgj7X5whc1tVRO17scisMnuHZz3b3eoarDlG75xGia3pTI/yxx X-Received: by 2002:a0d:e787:0:b0:31c:95d:4381 with SMTP id q129-20020a0de787000000b0031c095d4381mr26698847ywe.334.1656837878379; Sun, 03 Jul 2022 01:44:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656837878; cv=none; d=google.com; s=arc-20160816; b=Gqan6QcsM77KCnESfwreoW0uun9TouxORsaj2sl874Fd/ETFZ9tKAInaj2wUs+dFp7 Oxdugm10PzL8yHDzlob2fmbazPByjxX+8YDJrBliebJZPCVkY7n+bMpZFr0VAwlI5DV+ iK2gsq+WPtFid8F+YX37i9f9zIxBp6hWfirEAvzizggUkw3Ld5jSGN6vHeVV303aacR3 C9DU9oio5xVU8C9YssDJqNtAuTjd+qK0FgDhoXAUIYzCfHgbztPtOmOqChzP4phXR28C THBMqAigpMJXZIX4jth2T673uM9hL1Bs90XE3Xe6b0U00mt6aO4KIdoirIuJQfTOo7Np dmDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IDvBuKlYPmTlJ+6Vya3+/flWJH90DNxC8w/lfcBypPA=; b=Md+/KCnz3GKuww5ivewJPGSC0cX289VYDfmZv8Z9c9TM4YF+iIwd/uX3XfeC4kVdZR W1QO6wehhhKFL+umzs5QuDV1/Q5G/lQvQYqULTDkTDA0DjXKhUFx374pNE03cUN1izSm kG9xEo0yiI++sJt7cwpxunmRsAZ6ukvTNEjgfSs7re7SnPT24ZIfe/IQSs+eDbMgdKL3 uHcPWECwRbSG+XGeuGTDrDu/fFrfLPc2oW8wH8ChPQewrS+yl206ZCly+8CEIar8qNxF lDfHwGBGHaXlRlTnz/i20ku8DRwYY1/98WxnvnnTEkZ05e0zQe4dua5SGFLeAl8R1J// 8A3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h2FYAvty; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:26:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 33/62] target/arm: Fold secure and non-secure a-profile mmu indexes Date: Sun, 3 Jul 2022 13:53:50 +0530 Message-Id: <20220703082419.770989-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For a-profile, which does not bank system registers, it takes quite a lot of code to switch between security states. In the process, registers such as TCR_EL{1,2} must be swapped, which in itself requires the flushing of softmmu tlbs. Therefore it doesn't buy us anything to separate tlbs by security state. Retain the distinction between Stage2 and Stage2_S. This will be important as we implement FEAT_RME, and do not wish to add a third set of mmu indexes for Realm state. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 69 +++++++----------- target/arm/internals.h | 31 +------- target/arm/helper.c | 144 +++++++++++++------------------------ target/arm/ptw.c | 25 ++----- target/arm/translate-a64.c | 8 --- target/arm/translate.c | 6 +- 7 files changed, 83 insertions(+), 202 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index a14f167d11..6f702f58d9 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -40,6 +40,6 @@ struct PageEntryExtra { }; #endif -#define NB_MMU_MODES 15 +#define NB_MMU_MODES 8 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 919e7c27a3..04423f8d6c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2848,26 +2848,26 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); * table over and over. * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. + * 7. we fold together the secure and non-secure regimes for A-profile, + * because there are no banked system registers, so the process of + * switching between secure and non-secure is already heavyweight. * * This gives us the following list of cases: * - * NS EL0 EL1&0 stage 1+2 (aka NS PL0) - * NS EL1 EL1&0 stage 1+2 (aka NS PL1) - * NS EL1 EL1&0 stage 1+2 +PAN - * NS EL0 EL2&0 - * NS EL2 EL2&0 - * NS EL2 EL2&0 +PAN - * NS EL2 (aka NS PL2) - * S EL0 EL1&0 (aka S PL0) - * S EL1 EL1&0 (not used if EL3 is 32 bit) - * S EL1 EL1&0 +PAN - * S EL3 (aka S PL1) + * EL0 EL1&0 stage 1+2 (aka NS PL0) + * EL1 EL1&0 stage 1+2 (aka NS PL1) + * EL1 EL1&0 stage 1+2 +PAN + * EL0 EL2&0 + * EL2 EL2&0 + * EL2 EL2&0 +PAN + * EL2 (aka NS PL2) + * EL3 (aka S PL1) * * for a total of 11 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes - * as A profile. They only need to distinguish NS EL0 and NS EL1 (and - * NS EL2 if we ever model a Cortex-R52). + * as A profile. They only need to distinguish EL0 and EL1 (and + * EL2 if we ever model a Cortex-R52). * * M profile CPUs are rather different as they do not have a true MMU. * They have the following different MMU indexes: @@ -2906,9 +2906,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ #define ARM_MMU_IDX_M 0x40 /* M profile */ -/* Meanings of the bits for A profile mmu idx values */ -#define ARM_MMU_IDX_A_NS 0x8 - /* Meanings of the bits for M profile mmu idx values */ #define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 @@ -2922,22 +2919,14 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, - ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, - - ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, + ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system @@ -2946,9 +2935,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, /* * Not allocated a TLB: used only for second stage of an S12 page * table walk, or for descriptor loads during first stage of an S1 @@ -2956,8 +2942,8 @@ typedef enum ARMMMUIdx { * then various TLB flush insns which currently are no-ops or flush * only stage 1 MMU indexes will need to change to flush stage 2. */ - ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2_S = 4 | ARM_MMU_IDX_NOTLB, /* * M-profile. @@ -2987,14 +2973,7 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E2), TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), - TO_CORE_BIT(SE10_0), - TO_CORE_BIT(SE20_0), - TO_CORE_BIT(SE10_1), - TO_CORE_BIT(SE20_2), - TO_CORE_BIT(SE10_1_PAN), - TO_CORE_BIT(SE20_2_PAN), - TO_CORE_BIT(SE2), - TO_CORE_BIT(SE3), + TO_CORE_BIT(E3), TO_CORE_BIT(MUser), TO_CORE_BIT(MPriv), diff --git a/target/arm/internals.h b/target/arm/internals.h index d7062c6503..1bbe4d950e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -655,21 +655,12 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -680,11 +671,8 @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -695,30 +683,20 @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_SE2: case ARMMMUIdx_E2: return 2; - case ARMMMUIdx_SE3: + case ARMMMUIdx_E3: return 3; - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_Stage1_SE0: - return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_E10_0: case ARMMMUIdx_Stage1_E0: + return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3; case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_MPrivNegPri: @@ -944,9 +922,6 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: return true; default: return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index e98fc75646..7d9d4a9ad9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1737,6 +1737,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* Begin with base v8.0 state. */ uint32_t valid_mask = 0x3fff; ARMCPU *cpu = env_archcpu(env); + uint64_t changed; /* * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always @@ -1796,7 +1797,22 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* Clear all-context RES0 bits. */ value &= valid_mask; - raw_write(env, ri, value); + changed = env->cp15.scr_el3 ^ value; + env->cp15.scr_el3 = value; + + /* + * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * we must invalidate all TLBs below EL3. + */ + if (changed & SCR_NS) { + tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2)); + } } static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2627,9 +2643,6 @@ static int gt_phys_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2642,9 +2655,6 @@ static int gt_virt_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3352,7 +3362,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ switch (el) { case 3: - mmu_idx = ARMMMUIdx_SE3; + mmu_idx = ARMMMUIdx_E3; secure = true; break; case 2: @@ -3360,10 +3370,9 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* fall through */ case 1: if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { - mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); + mmu_idx = ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx = ARMMMUIdx_Stage1_E1; } break; default: @@ -3374,7 +3383,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx = ARMMMUIdx_SE10_0; + mmu_idx = ARMMMUIdx_E10_0; secure = true; break; case 2: @@ -3382,7 +3391,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) mmu_idx = ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx = ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3451,17 +3460,16 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); + mmu_idx = ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx = ARMMMUIdx_Stage1_E1; } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; + mmu_idx = ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx = ARMMMUIdx_SE3; + mmu_idx = ARMMMUIdx_E3; secure = true; break; default: @@ -3469,13 +3477,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx = ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; + mmu_idx = ARMMMUIdx_E10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; + mmu_idx = ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); @@ -3775,11 +3783,6 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint16_t mask = ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | ARMMMUIdxBit_E20_0; - - if (arm_is_secure_below_el3(env)) { - mask >>= ARM_MMU_IDX_A_NS; - } - tlb_flush_by_mmuidx(env_cpu(env), mask); } raw_write(env, ri, value); @@ -3799,11 +3802,6 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint16_t mask = ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; - - if (arm_is_secure_below_el3(env)) { - mask >>= ARM_MMU_IDX_A_NS; - } - tlb_flush_by_mmuidx(cs, mask); raw_write(env, ri, value); } @@ -4274,11 +4272,6 @@ static int vae1_tlbmask(CPUARMState *env) ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; } - - if (arm_is_secure_below_el3(env)) { - mask >>= ARM_MMU_IDX_A_NS; - } - return mask; } @@ -4305,10 +4298,6 @@ static int vae1_tlbbits(CPUARMState *env, uint64_t addr) mmu_idx = ARMMMUIdx_E10_0; } - if (arm_is_secure_below_el3(env)) { - mmu_idx &= ~ARM_MMU_IDX_A_NS; - } - return tlbbits_for_regime(env, mmu_idx, addr); } @@ -4341,30 +4330,17 @@ static int alle1_tlbmask(CPUARMState *env) * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; - } else { - return ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0; - } + return (ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0); } static int e2_tlbmask(CPUARMState *env) { - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE20_0 | - ARMMMUIdxBit_SE20_2 | - ARMMMUIdxBit_SE20_2_PAN | - ARMMMUIdxBit_SE2; - } else { - return ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2; - } + return (ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2); } static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4391,7 +4367,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3); } static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4417,7 +4393,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, { CPUState *cs = env_cpu(env); - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); } static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4445,7 +4421,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, CPUState *cs = CPU(cpu); uint64_t pageaddr = sextract64(value << 12, 0, 56); - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3); } static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4484,12 +4460,10 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, { CPUState *cs = env_cpu(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); - bool secure = arm_is_secure_below_el3(env); - int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; - int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, - pageaddr); + int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + ARMMMUIdxBit_E2, bits); } static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4497,10 +4471,10 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, { CPUState *cs = env_cpu(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); - int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr); tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_SE3, bits); + ARMMMUIdxBit_E3, bits); } #ifdef TARGET_AARCH64 @@ -4606,8 +4580,7 @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env, static int vae2_tlbmask(CPUARMState *env) { - return (arm_is_secure_below_el3(env) - ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); + return ARMMMUIdxBit_E2; } static void tlbi_aa64_rvae2_write(CPUARMState *env, @@ -4653,8 +4626,7 @@ static void tlbi_aa64_rvae3_write(CPUARMState *env, * flush-last-level-only. */ - do_rvae_write(env, value, ARMMMUIdxBit_SE3, - tlb_force_broadcast(env)); + do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); } static void tlbi_aa64_rvae3is_write(CPUARMState *env, @@ -4668,7 +4640,7 @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env, * flush-last-level-only or inner/outer specific flushes. */ - do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); + do_rvae_write(env, value, ARMMMUIdxBit_E3, true); } #endif @@ -10604,8 +10576,7 @@ uint64_t arm_sctlr(CPUARMState *env, int el) /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ if (el == 0) { ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); - el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0) - ? 2 : 1; + el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1; } return env->cp15.sctlr_el[el]; } @@ -11149,22 +11120,15 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE20_0: return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: return 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return 2; - case ARMMMUIdx_SE3: + case ARMMMUIdx_E3: return 3; default: g_assert_not_reached(); @@ -11217,15 +11181,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } break; case 3: - return ARMMMUIdx_SE3; + return ARMMMUIdx_E3; default: g_assert_not_reached(); } - if (arm_is_secure_below_el3(env)) { - idx &= ~ARM_MMU_IDX_A_NS; - } - return idx; } @@ -11407,15 +11367,11 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, switch (mmu_idx) { case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ DP_TBFLAG_A64(flags, UNPRIV, 1); break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: /* * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is * gated by HCR_EL2. == '11', and so is LDTR. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a7c0d616a0..1fb4d44600 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -65,12 +65,6 @@ unsigned int arm_pamax(ARMCPU *cpu) ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE10_0: - return ARMMMUIdx_Stage1_SE0; - case ARMMMUIdx_SE10_1: - return ARMMMUIdx_Stage1_SE1; - case ARMMMUIdx_SE10_1_PAN: - return ARMMMUIdx_Stage1_SE1_PAN; case ARMMMUIdx_E10_0: return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: @@ -95,11 +89,8 @@ static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE10_0: case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE20_0: case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_SE0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -2320,7 +2311,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, } s2_mmu_idx = (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); - is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; + is_el0 = mmu_idx == ARMMMUIdx_E10_0; /* * S1 is done, now do S2 translation. @@ -2528,6 +2519,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: + is_secure = arm_is_secure_below_el3(env); + break; case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: @@ -2535,17 +2528,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, case ARMMMUIdx_MUser: is_secure = false; break; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_SE2: + case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 57f492ccef..ff14c90997 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -111,14 +111,6 @@ static int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_E20_2_PAN: useridx = ARMMMUIdx_E20_0; break; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - useridx = ARMMMUIdx_SE10_0; - break; - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - useridx = ARMMMUIdx_SE20_0; - break; default: g_assert_not_reached(); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 540ce84d95..f6e61dffe9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -237,16 +237,12 @@ static inline int get_a32_user_mem_index(DisasContext *s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { + case ARMMMUIdx_E3: case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); From patchwork Sun Jul 3 08:23:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586831 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2927566mab; Sun, 3 Jul 2022 02:03:43 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tqs2YvdA3MBIwKpYHdSyK29Qrbx961syjfYPgiF2Hku68Mj72XR7qhvyTV6GJM+1D2TXLj X-Received: by 2002:a25:ec0b:0:b0:669:b376:8bf5 with SMTP id j11-20020a25ec0b000000b00669b3768bf5mr24623925ybh.111.1656839023225; Sun, 03 Jul 2022 02:03:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839023; cv=none; d=google.com; s=arc-20160816; b=neP4MCSjIJHMGvOdee6nkhOqFaVKCZvhUYxzXVepg9zf2cx2P2+a2/WGjcQDdn7rUP b77ysSFl41VeKfAGcKz5J9KI3byhu9Sf4emi2AJufQ1hNe0MI78zZuLIhcpIhF082Kvy 1ZcN24bJ5ePS6Jkcv5rF3JeQ6zHVBy16dOHNO7sJ4UQDo5j5D4F3EusvQLPMSgPL4jYn 5lxtl0ui0XlGFEHeHmvy878ysmcfBHrfZCYXNrxG6cyqz5Fb+LSYbHKsRCkZAYDoFaSg ZNfh8fGcrxROIarmQu69oe3BAhBLguin4FIgMy6Hdv28Oi1k1zxFSfAY2tEHCEdtUN5C ySkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/RaZZc14+S6hYz1OWvaDxJGxtM/J8YX/Y05Pry77JbE=; b=XiPzDfUeEnY++6nhHHl7jf5tCKQ+k/E3+HB0aCtT2NnNMp+ohFjgUZ+p8FA2glqmS/ Ox7yb5m0uFE/gFKWkm7DHaZeBghA88oUCOFLH7QSZZaUftW1JjsVikLk4qF3k4p4tSub 00vtNqvgTI7ETrDP7eI6Pw9WLcUz5ScANBbAeQ2AYMAA70HXfQozdwS/fFEOHLGI7SO+ PMaRyMR/NY5ZARmytgo0L1u2JqqwRD3AIt3/ycHAeR78MhEMGT2Xanym/gRza8/uL0kY 0mAqlRiSiLPizNO1LPNZkdcZDxEa6FrcdEZmFMZiBiLHtNOVlJu5n+Ztjk15e8sBAMyJ hlhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F2wMatOZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:26:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 34/62] target/arm: Reorg regime_translation_disabled Date: Sun, 3 Jul 2022 13:53:51 +0530 Message-Id: <20220703082419.770989-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use a switch on mmu_idx for the a-profile indexes, instead of three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1fb4d44600..8b80716e38 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -148,21 +148,39 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, hcr_el2 = arm_hcr_el2_eff(env); - if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: /* HCR.DC means HCR.VM behaves as 1 */ return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; - } - if (hcr_el2 & HCR_TGE) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!is_secure && regime_el(env, mmu_idx) == 1) { + if (!is_secure && (hcr_el2 & HCR_TGE)) { return true; } - } + break; - if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: /* HCR.DC means SCTLR_EL1.M behaves as 0 */ - return true; + if (hcr_el2 & HCR_DC) { + return true; + } + break; + + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_E2: + case ARMMMUIdx_E3: + break; + + default: + g_assert_not_reached(); } return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; From patchwork Sun Jul 3 08:23:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586815 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2920375mab; Sun, 3 Jul 2022 01:48:27 -0700 (PDT) X-Google-Smtp-Source: AGRyM1u2A3tijGldcscoc+Fp+xn2h5RcV4cR5sKCarXIEhEpd6G9f8PK6R/dgAXgXBF5lPQD/bgn X-Received: by 2002:a25:b68a:0:b0:66d:98df:81cd with SMTP id s10-20020a25b68a000000b0066d98df81cdmr21398255ybj.454.1656838107456; Sun, 03 Jul 2022 01:48:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838107; cv=none; d=google.com; s=arc-20160816; b=zgZYWI+wM/Xvo+yNnlIZz3NWLLFd7pu6VownNw2j8mXgzpEvWC3m7k2X3sw6pt3XNC AOvomvuJvdYFsHnIIjX3K10UWNV1dh0tS/Zp6+9y7G9LGLbehH8gq525GSovJ/xh0hbQ z3nMSeWYyagpNrWCGiLkbjCU/S99Q5FLz0hgsQ/K4F24h5UkBqvBhHcrzS2a6FdNj06g Q6Pun+gI64tUaWBzpU6TnESUGAXyuIAf4fU3yyZCgK7pK1p4oeI3UN+zLQGCnU0XymbA jvOVoMGArY+yvJMfEjilJmfx68kX/FhnG11vxjUyfhrzh78qTuEkHqq9TE16XiU86xOL vvKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UdWt/TITPMQtfVvFmAMORDuCVpC5zM3kt486JkKHmUA=; b=0sTU0FunvjTsI7FRJN3/eh/zY/JG5ehjRAA1lvJ4+9ygx2Pi4rIYfiuKd/GXawd0P2 3DW/mDtArymXyYfYjEggaZXFYhnaqh5G2mMDc3tZ3/maJ8nIpOxADdyS4TasdcSmdtfm i4QuNjBNEh4G6WPXHGSqHurPODsa+BLdJAA6OeDha0DZnPfRGbWRLYqXl2m+OEcMOrkJ TObMMgkJCnZYCne08Dxq6mv/k7slQNdLsBuQkeS/lmRqW89FZ03ES6tAcvr2FgwGeQxK cFDR2bNPKFWh2HmtFMA/+bz0wq98MgBKbDyR/9cp+WjsOEGMhYSuqTgcM1oYNAObnF6Z j78g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nXmvw1i0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:26:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 35/62] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Date: Sun, 3 Jul 2022 13:53:52 +0530 Message-Id: <20220703082419.770989-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The effect of TGE does not only apply to non-secure state, now that Secure EL2 exists. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b80716e38..f76a8e931a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -157,8 +157,8 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!is_secure && (hcr_el2 & HCR_TGE)) { + /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */ + if (hcr_el2 & HCR_TGE) { return true; } break; From patchwork Sun Jul 3 08:23:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586820 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2921354mab; Sun, 3 Jul 2022 01:50:28 -0700 (PDT) X-Google-Smtp-Source: AGRyM1s7f4CNcFx73LPau5eXbWYynvgSs1z+4AK9tGcE8NQHpcqVacgJqkvY9GJfSoJe3X89+pXp X-Received: by 2002:a25:850b:0:b0:66c:d287:625a with SMTP id w11-20020a25850b000000b0066cd287625amr24541156ybk.31.1656838228730; Sun, 03 Jul 2022 01:50:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838228; cv=none; d=google.com; s=arc-20160816; b=kUxZBLwSQs6P3NpjxOtAXFp+GNpTMYmr988PCa3yrYCYCCJJHwGDnStr5Rt/NbDdw6 ryeVVvyTsIPdJ1mkf9Zz5ejPfg6tZtGd/DmNCcw4kL6kC6K4w6Cp2U9tPQLIynWF3ObK Wd9r35CtkR86yog4vracYfyyjdm61Ca6fKguO8NHErkVFNWpwvm6LHkwPICfh+7ykmFZ bMOEj3k6HRyK8HbCDFAeJVuo9f8YaG4YVKrU5DOYSbBi597K/u6jpNSzEdz9b6KM02uZ g/pBgsNWrzp3i+t5QlA5gRhame7DCTdSkInQD75P8nnZnhNp3YiZ97UW2iNCP9vT19QX vZWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0mD6vxNSf+I50Th5Elr1blnSVn6mQpha4WrhIJX+W14=; b=Qegjc4Ay/uhmVHOylNZeepuXpIJUDw3jzcI5FjydHfnZGsHgL8onsqKacawNnKXRhN 3c2LmQgbU8mFSnsCnj38h+NwWxSXGTH4BzC3awfBKpqMU7udMf4rP8gkzKEwJyy1FAom GdASuEtL8TuGuVaT0Q3vjTuAkvJhFlUkiVAWr3gNz0UtzOfFDeItKSJjDcnrv66C6NO9 xEGOJ2O7nolvciYCvgg6qjQgt71asy1UVRQwc4PZOvS5K7cz53hWSyPKnjG2aQM4JjjV dclVpCyBzEbcOf7zUtGT+WQLZ0tEEiez12CRI/f93M8G+GhY1dYebVHl7dNzKNFN7V4Z tBQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dG50zlki; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:26:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 36/62] target/arm: Introduce arm_hcr_el2_eff_secstate Date: Sun, 3 Jul 2022 13:53:53 +0530 Message-Id: <20220703082419.770989-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For page walking, we may require HCR for a security state that is not "current". Signed-off-by: Richard Henderson --- target/arm/cpu.h | 20 +++++++++++++------- target/arm/helper.c | 11 ++++++++--- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 04423f8d6c..dd577a08bc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2376,15 +2376,15 @@ static inline bool arm_is_secure(CPUARMState *env) * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. * This corresponds to the pseudocode EL2Enabled() */ +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) +{ + return (arm_feature(env, ARM_FEATURE_EL2) + && (!secure || (env->cp15.scr_el3 & SCR_EEL2))); +} + static inline bool arm_is_el2_enabled(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_EL2)) { - if (arm_is_secure_below_el3(env)) { - return (env->cp15.scr_el3 & SCR_EEL2) != 0; - } - return true; - } - return false; + return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); } #else @@ -2398,6 +2398,11 @@ static inline bool arm_is_secure(CPUARMState *env) return false; } +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) +{ + return false; +} + static inline bool arm_is_el2_enabled(CPUARMState *env) { return false; @@ -2410,6 +2415,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *env) * "for all purposes other than a direct read or write access of HCR_EL2." * Not included here is HCR_RW. */ +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d9d4a9ad9..176be48c46 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5197,15 +5197,15 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, } /* - * Return the effective value of HCR_EL2. + * Return the effective value of HCR_EL2, at the given security state. * Bits that are not included here: * RW (read from SCR_EL3.RW as needed) */ -uint64_t arm_hcr_el2_eff(CPUARMState *env) +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) { uint64_t ret = env->cp15.hcr_el2; - if (!arm_is_el2_enabled(env)) { + if (!arm_is_el2_enabled_secstate(env, secure)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -5264,6 +5264,11 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); +} + /* * Corresponds to ARM pseudocode function ELIsInHost(). */ From patchwork Sun Jul 3 08:23:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586834 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2930578mab; Sun, 3 Jul 2022 02:09:15 -0700 (PDT) X-Google-Smtp-Source: AGRyM1t4VQr3uoss8lsuxqeC8VYMQjhmdRN13soA33fFMFXlfO/Rnd4/69pU805JRgO+1SWwhmMN X-Received: by 2002:a81:6b0a:0:b0:31c:827c:9388 with SMTP id g10-20020a816b0a000000b0031c827c9388mr6127169ywc.181.1656839355143; Sun, 03 Jul 2022 02:09:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839355; cv=none; d=google.com; s=arc-20160816; b=hWgDgIuvTpMYkW15lIAGK6bxHCfIvx+QT9Jv0uwsRUfllxjIfFvkrCTyEjD2aqE5ZG c474Ta/ZKTUh7TqfelzMdNORyPdkbgkYImim5i2pS/XfpiNFw46LqlxIbCOvvRy7kRfJ Hxu1vHZk9PaYCUPHOcm02wpn+omyL/I9/XKoFTd/L2MOVaqzmnjlwEMW685sJ5pEwI5n kIDZl2+qJVLY5GTo+5xri0WcHpQ6dkz+Ohf2MslJ82Zty8mldNpSd4hEcacqXLDQ35Vw wOWKe3doHjhzQXsPTS8IbdR+d5lsB2RbokarzDKJj4shAl6MITfbwGaaj8MUWHKv2vTE xYsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GvXUGU1iRA1atVwXCiqqvbPFvrWHZ4nIvxHqNJBxHmA=; b=gsCKRsfuX/JIBld8UQQWHgQjz66W2Gr21TxH03fF4ehc2awXDKJKjqL+KyF/5zHrL3 gDLFb4GKRK8TS+loM+l4gpZmUL/S1qJ0oswR1uiNr4owPMaHwRsufHjh+Qv2i77LCWkH ZWtf5BdLn59Bp7KEl6N3Bm5F3ZmVmBkqm6VK+0ehrVtyRV4Rl0xLBvv0oI8ELyhr5UYX wdWpm/SERusXtfVA7zJrTS10qwlPT8wtadZ5IieysdXeUjIdQhAN6EjPBmxuUolRIyxr hTttCSMz24wQDHYZsCRWOwbH1AbA727suM6vpjOCaueBCE5cvhPlX+8ZfBVb/77UIsDX Ileg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jCv21o8u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:26:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate Date: Sun, 3 Jul 2022 13:53:54 +0530 Message-Id: <20220703082419.770989-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename the argument to is_secure_ptr, and introduce a local variable is_secure with the value. We only write back to the pointer toward the end of the function. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f76a8e931a..12288ac365 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -207,24 +207,26 @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure, + hwaddr addr, bool *is_secure_ptr, ARMMMUFaultInfo *fi) { + bool is_secure = *is_secure_ptr; + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, *is_secure)) { - ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S - : ARMMMUIdx_Stage2; + !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { + ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S + : ARMMMUIdx_Stage2; GetPhysAddrResult s2 = {}; int ret; ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - *is_secure, false, &s2, fi); + is_secure, false, &s2, fi); if (ret) { assert(fi->type != ARMFault_None); fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; - fi->s1ns = !*is_secure; + fi->s1ns = !is_secure; return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && @@ -237,19 +239,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; - fi->s1ns = !*is_secure; + fi->s1ns = !is_secure; return ~0; } if (arm_is_secure_below_el3(env)) { /* Check if page table walk is to secure or non-secure PA space. */ - if (*is_secure) { - *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + if (is_secure) { + is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); } else { - *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); } + *is_secure_ptr = is_secure; } else { - assert(!*is_secure); + assert(!is_secure); } addr = s2.phys; From patchwork Sun Jul 3 08:23:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586832 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2928536mab; Sun, 3 Jul 2022 02:05:11 -0700 (PDT) X-Google-Smtp-Source: AGRyM1s/IB33S/N72dhUt1+Fm+G5QQ8CgaFJukznJcY1j/GQPSIPWmEwFXeapQu2sm7pknslphhv X-Received: by 2002:a81:6dce:0:b0:31c:9398:45a5 with SMTP id i197-20020a816dce000000b0031c939845a5mr222117ywc.65.1656839111713; Sun, 03 Jul 2022 02:05:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839111; cv=none; d=google.com; s=arc-20160816; b=GDu7Pgienghodcs3G/lUJNjMcmO/pguEU4zsQATKTP+MaLszwQfvtBirX94wnbbknG UWFe/2jqVjJOybQsb28eun7H/1wKO1fo4oeL4alKJftKYfc70meKtAuejSPQdCcOeKsg eZOvESeukuScprk/e1uVMR+QJqEuBTWPG5IeoZkI1s4XSGHZIhKLcIofN6IjCRhgf49s cm/9dJyhhVelBjHDQrPWX3SK7sWDAZ67IPdpAfefyHmaEmPyYy5qqM0oUf+SB6K5gmTA HZQvm0Aw51YwoMCTK5+ixuxKB8q1J/Q6HjkmfjtH/l49LMBJJdbHclNjadqdTkK0RYjd MBrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XqyFuY6xtQUWsP/jQ4A5BA4dQ9EI8+6RDOKP4j5I7T8=; b=lgR0S4eCBqzT+w+mWroMTHoHO/qwAw3tBY9t6aq4A8fyM4p/KcMmrls3vV1GJAhcwk Vhdqk+HT+XYQbSR7F4pfwzLHZxXAq/BTSlVvzMx01Nq2YRv9oWb9INyvP6ypCE8jYj01 MXlDgAzdrP6xS4Ol9+esSSEZll4h79YluYVxlcAkdYaCRq9+qF4rPjA6cRmE0Igo4JuU P48p01pQwrCioSNM7iOx9hxyqtL8xyK3WbN/MQt3QSp5YtLjlb9QN1jZ3BpFGokS+AEw mOicr3j5dmskINBa4LFE00U7+r9nKgFZGyw+fPArY5GRYQgdIZ73UyBhCn1UKwqd4h4g ny5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="SX/PtmQo"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:26:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 38/62] target/arm: Fix S2 disabled check in S1_ptw_translate Date: Sun, 3 Jul 2022 13:53:55 +0530 Message-Id: <20220703082419.770989-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass the correct stage2 mmu_idx to regime_translation_disabled, which we computed afterward. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 12288ac365..12b6c2c98b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -211,11 +211,10 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { bool is_secure = *is_secure_ptr; + ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { - ARMMMUIdx s2_mmu_idx = is_secure ? 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Signed-off-by: Richard Henderson --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 12b6c2c98b..93c533e60d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2168,8 +2168,7 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the * combined attributes in MAIR_EL1 format. */ -static uint8_t combined_attrs_fwb(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2) +static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2) { switch (s2.attrs) { case 7: @@ -2242,7 +2241,7 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, /* Combine memory type and cacheability attributes */ if (arm_hcr_el2_eff(env) & HCR_FWB) { - ret.attrs = combined_attrs_fwb(env, s1, s2); + ret.attrs = combined_attrs_fwb(s1, s2); } else { ret.attrs = combined_attrs_nofwb(env, s1, s2); } From patchwork Sun Jul 3 08:23:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586836 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2931409mab; Sun, 3 Jul 2022 02:10:35 -0700 (PDT) X-Google-Smtp-Source: AGRyM1skeybZ5I23sY6mzcZVbO25FKhQQarS2y5m/0oQeMUMjKZVZcHQzCjwrecSxz39qW5MkOvU X-Received: by 2002:a5b:191:0:b0:66e:1afe:ae02 with SMTP id r17-20020a5b0191000000b0066e1afeae02mr8127054ybl.310.1656839435552; Sun, 03 Jul 2022 02:10:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839435; cv=none; d=google.com; s=arc-20160816; b=pvhr8+mMFNesR4JcsDta2OKjQIzuvvlyo15pgHPKha2cchbRcYP3DKCi7CRJepiH+0 6JjWgix1EP8E+Kkg/tIUqBXPwtal8t6zsFF7XZssnnvDTrBWuuMgcEeAAMmlzaKsccwH QSDECWFesDXu3+BG4C76vlO0sqnhF9MxphOVzseFcirxBOUHGym7n1zsfHFj8qjn/ib1 hx1ee4j/90FbJBMMCKveu4Gf7zmZwXLCMnAxoQo+zZZyhkU6Gh+oWm/igz2NXo7kAqHE GA4J6gPitGD3adjPqoc3nde7Q1xzsUfNEl4M95qqXopF7j02HwoDInBWeKqtMbEfJNDS 2CSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=27Wz5DSCW8ENXu7065ZoRBnr2V/wpxEQdmpGVTXjexE=; b=yXopMoaoTROf4ubh7AkVnz9k1GpPJqEdOBi88cL/Xrj+9AKb/N7mTPMbJ6FZW9+15I YgY+SevZmOHVEIYs63oD8NeyLQsYRazNInmAmMVTdqqkUk+jMhlX0qHXTXAiNJlZG1h2 nbxZiKG0iNj71DqDmITR05oFFNwSwQfvAyuT6fk3UnISGJUzny7kgmVaSytNTOjrXwKj G3haEeyCK4vamJrWpGm9MeSj9wq+CPEKk8RUjwzfXnksle0pS37fMMjHyti3DhZKlT+D NFRIVjMIlLoJjJVKYxyIKDx7YdAJ/AKPAQ5nTuI4WD/ZSrSf92EkLM0UE/68PWp1IqY+ ECzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xu9jo53r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 40/62] target/arm: Pass HCR to attribute subroutines. Date: Sun, 3 Jul 2022 13:53:57 +0530 Message-Id: <20220703082419.770989-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These subroutines did not need ENV for anything except retrieving the effective value of HCR anyway. We have computed the effective value of HCR in the callers, and this will be especially important for interpreting HCR in a non-current security state. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 93c533e60d..a760ab86c5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -186,7 +186,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } -static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) +static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) { /* * For an S1 page table walk, the stage 1 attributes are always @@ -198,7 +198,7 @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) * when cacheattrs.attrs bit [2] is 0. */ assert(cacheattrs.is_s2_format); - if (arm_hcr_el2_eff(env) & HCR_FWB) { + if (hcr & HCR_FWB) { return (cacheattrs.attrs & 0x4) == 0; } else { return (cacheattrs.attrs & 0xc) == 0; @@ -216,6 +216,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { GetPhysAddrResult s2 = {}; + uint64_t hcr; int ret; ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, @@ -228,8 +229,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s1ns = !is_secure; return ~0; } - if ((arm_hcr_el2_eff(env) & HCR_PTW) && - ptw_attrs_are_device(env, s2.cacheattrs)) { + + hcr = arm_hcr_el2_eff(env); + if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -2055,14 +2057,14 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, * ref: shared/translation/attrs/S2AttrDecode() * .../S2ConvertAttrsHints() */ -static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) +static uint8_t convert_stage2_attrs(uint64_t hcr, uint8_t s2attrs) { uint8_t hiattr = extract32(s2attrs, 2, 2); uint8_t loattr = extract32(s2attrs, 0, 2); uint8_t hihint = 0, lohint = 0; if (hiattr != 0) { /* normal memory */ - if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ + if (hcr & HCR_CD) { /* cache disabled */ hiattr = loattr = 1; /* non-cacheable */ } else { if (hiattr != 1) { /* Write-through or write-back */ @@ -2108,12 +2110,12 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the * combined attributes in MAIR_EL1 format. */ -static uint8_t combined_attrs_nofwb(CPUARMState *env, +static uint8_t combined_attrs_nofwb(uint64_t hcr, ARMCacheAttrs s1, ARMCacheAttrs s2) { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; - s2_mair_attrs = convert_stage2_attrs(env, s2.attrs); + s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs); s1lo = extract32(s1.attrs, 0, 4); s2lo = extract32(s2_mair_attrs, 0, 4); @@ -2213,7 +2215,7 @@ static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2) * @s1: Attributes from stage 1 walk * @s2: Attributes from stage 2 walk */ -static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, +static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, ARMCacheAttrs s1, ARMCacheAttrs s2) { ARMCacheAttrs ret; @@ -2240,10 +2242,10 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, } /* Combine memory type and cacheability attributes */ - if (arm_hcr_el2_eff(env) & HCR_FWB) { + if (hcr & HCR_FWB) { ret.attrs = combined_attrs_fwb(s1, s2); } else { - ret.attrs = combined_attrs_nofwb(env, s1, s2); + ret.attrs = combined_attrs_nofwb(hcr, s1, s2); } /* @@ -2309,6 +2311,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; + uint64_t hcr; ret = get_phys_addr_with_secure(env, address, access_type, s1_mmu_idx, is_secure, result, fi); @@ -2354,7 +2357,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, } /* Combine the S1 and S2 cache attributes. */ - if (arm_hcr_el2_eff(env) & HCR_DC) { + hcr = arm_hcr_el2_eff(env); + if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to * Normal Non-Shareable, @@ -2367,7 +2371,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, } cacheattrs1.shareability = 0; } - result->cacheattrs = combine_cacheattrs(env, cacheattrs1, + result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1, result->cacheattrs); /* Check if IPA translates to secure or non-secure PA space. */ From patchwork Sun Jul 3 08:23:58 2022 Content-Type: text/plain; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 41/62] target/arm: Fix ATS12NSO* from S PL1 Date: Sun, 3 Jul 2022 13:53:58 +0530 Message-Id: <20220703082419.770989-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This has been broken since arm_hcr_el2_eff gained a check for "el2 enabled" for Secure EL2. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a760ab86c5..43a82c3c7f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -146,7 +146,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, } } - hcr_el2 = arm_hcr_el2_eff(env); + hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure); switch (mmu_idx) { case ARMMMUIdx_Stage2: @@ -230,7 +230,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, return ~0; } - hcr = arm_hcr_el2_eff(env); + hcr = arm_hcr_el2_eff_secstate(env, is_secure); if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: @@ -2357,7 +2357,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, } /* Combine the S1 and S2 cache attributes. */ - hcr = arm_hcr_el2_eff(env); + hcr = arm_hcr_el2_eff_secstate(env, is_secure); if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to @@ -2490,7 +2490,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, result->page_size = TARGET_PAGE_SIZE; /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr = arm_hcr_el2_eff(env); + hcr = arm_hcr_el2_eff_secstate(env, is_secure); result->cacheattrs.shareability = 0; result->cacheattrs.is_s2_format = false; if (hcr & HCR_DC) { From patchwork Sun Jul 3 08:23:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586842 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2935202mab; Sun, 3 Jul 2022 02:18:16 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sKJs/Rvmh/kiXtIOlIllPBA17D7WQ2zpiwmkPwhKs22NpzcYtfNM47n7tFdfZf/n+jMQef X-Received: by 2002:a81:1355:0:b0:31c:9441:ec1b with SMTP id 82-20020a811355000000b0031c9441ec1bmr193296ywt.101.1656839896172; Sun, 03 Jul 2022 02:18:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839896; cv=none; d=google.com; s=arc-20160816; b=oQxamxd52kUGvG5gDZWWqDSdiWSV4yXhTtPCdF+9huJqw4i1uAITQdW5KNIjCePUSs owjUkTO+B3cZdyE6qojURwXXLtGKTcm7GV7eb+KxomuCA9QhcjiWzHDEhDrjAuTZJ16+ RwFhdhXp7ASn6h8OUF3LddU7dExDps+WUZNHKpKDDBhIZDQUciVnd5E03SXGIuz1K/yT cWX/nMw55Rg84+sdEoLfXrBOFaXv+vJkyG2NkY1X5s63PDBPBvvuDETESpRzHAryqR8m hljfDdHa1S0EhVPyBB1YlDOkWVBiQVbTbV89WojQuqQH7DroywrSo4N7e13lyn/Wm3sX 9PZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AiWy/j3oKk4cigaisVDN3VGQJ/Lj1RcvwVUPj1j1dIE=; b=HXFe3LWtdOjLNjI/MklEJmMyl28wN/RybIAH1Mee7ks25dM0LsB00D2fldu5ECiKJx fc4SDWgEv/hFXpeJcnRc7tByedlH6RiwH+MegG0VLASqaap2l4CrJ+R8MRJYiJpzyqPg cNksJEFcN2WiRodBDEtL/xnGG1sol3sAxzpXgiHuYj769/50QPqtVkKle+JcEnOjHaW6 Rrz3IeMZxChGKRw3VBwRvfg+IonxCgoavq+1F2vCXmPbXfHN6LW1wTuf8RAvU769idPc +Ip1HEgOZ6lpTCHNmcXYUJBWA9dWEsaD61moOgINnYROc4bQ97lz36fg1Kaoul8aSL+Q CFOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dptdrjwa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 42/62] target/arm: Split out get_phys_addr_disabled Date: Sun, 3 Jul 2022 13:53:59 +0530 Message-Id: <20220703082419.770989-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/ptw.c | 138 +++++++++++++++++++++++++---------------------- 1 file changed, 74 insertions(+), 64 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 43a82c3c7f..0f4b9b0166 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2268,6 +2268,78 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, return ret; } +/* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.S1DisabledOutput(). + */ +static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + uint64_t hcr; + uint8_t memattr; + + if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { + int r_el = regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax = arm_pamax(env_archcpu(env)); + uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; + int addrtop, tbi; + + tbi = aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type == MMU_INST_FETCH) { + tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi = (tbi >> extract64(address, 55, 1)) & 1; + addrtop = (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) != 0) { + fi->type = ARMFault_AddressSize; + fi->level = 0; + fi->stage2 = false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address = extract64(address, 0, 52); + } + } + + result->phys = address; + result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->page_size = TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr = arm_hcr_el2_eff_secstate(env, is_secure); + result->cacheattrs.shareability = 0; + result->cacheattrs.is_s2_format = false; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr = 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr = 0xff; /* Normal, WB, RWA */ + } + } else if (access_type == MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr = 0xee; /* Normal, WT, RA, NT */ + } else { + memattr = 0x44; /* Normal, NC, No */ + } + result->cacheattrs.shareability = 2; /* outer sharable */ + } else { + memattr = 0x00; /* Device, nGnRnE */ + } + result->cacheattrs.attrs = memattr; + return 0; +} + /** * get_phys_addr - get the physical address for this virtual address * @@ -2448,71 +2520,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, /* Definitely a real MMU, not an MPU */ if (regime_translation_disabled(env, mmu_idx, is_secure)) { - uint64_t hcr; - uint8_t memattr; - - /* - * MMU disabled. S1 addresses within aa64 translation regimes are - * still checked for bounds -- see AArch64.TranslateAddressS1Off. - */ - if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { - int r_el = regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax = arm_pamax(env_archcpu(env)); - uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; - int addrtop, tbi; - - tbi = aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type == MMU_INST_FETCH) { - tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi = (tbi >> extract64(address, 55, 1)) & 1; - addrtop = (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) != 0) { - fi->type = ARMFault_AddressSize; - fi->level = 0; - fi->stage2 = false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address = extract64(address, 0, 52); - } - } - result->phys = address; - result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size = TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr = arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability = 0; - result->cacheattrs.is_s2_format = false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr = 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr = 0xff; /* Normal, WB, RWA */ - } - } else if (access_type == MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr = 0xee; /* Normal, WT, RA, NT */ - } else { - memattr = 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability = 2; /* outer sharable */ - } else { - memattr = 0x00; /* Device, nGnRnE */ - } - result->cacheattrs.attrs = memattr; - return 0; + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, is_secure, false, result, fi); From patchwork Sun Jul 3 08:24:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586838 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2933669mab; Sun, 3 Jul 2022 02:15:04 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vxui94FPn7fyHphEhoXqamsjpXLjbiJbk3aDOfGUKR43WOzz0GsQoSDfuptJT4jMziqIgo X-Received: by 2002:a81:928c:0:b0:31c:7c9b:9ff2 with SMTP id j134-20020a81928c000000b0031c7c9b9ff2mr7813628ywg.490.1656839704390; Sun, 03 Jul 2022 02:15:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839704; cv=none; d=google.com; s=arc-20160816; b=lxdH/iBYzlRrcOcHg8cNucoKoebklzP+3bladE8ujqLa/9eC8qk+i5BOFMIlbda1Xj cy2ccuua1oMk1ZEFIGrgIXFD07cYvV3KZGU6UL377SCMcNmMDcjf3dUKTEFn9zj5iANP HGffDms5EHavd9TojTyCBODJbrRGZK+8OKRFAip0aRZ1x2mnjbvHsu6zs9hbMUsciITm Pnr7Q71dCijJKuQ1uBhyEv2ZOSqShPykPsCYhYjoyx9GcjYG0j/BpRde3rOc+x7j8TlI 4ZRvUb/BhhsZ5okoERHAI2wt/u5Sj6Uy7bF1y+yJ5MY4h5dSXf6QRfLpcJz+dms2xDbr GhhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=czDINC237o/2raNbHTOaskPo+9bv5Oqa4q6sEcK6I78=; b=TLAdLEE18CZaQgv1u8GyNLYJrQvvxK2nWlNnfDvZf0PBULSvp8xFv8NhhxN0gZXh8a hNd+WCiL+1vXnwpWJTsM+aGyUZS0xtUi12ACTgaaGV9jpOahdGqHuqWUilDYwuG1xkL5 oD1otno/zqWaeTXq+1rjCesLwXPaCqK4/MuNHBSfmkdJ5Fiiz6oJ1dSBfMNKaBg8e8ax dZGM3pnq4657+VnqQWGAWxeiBX8aAy98ptkGftgdoHTvcCVZQVGT8es78BLhK7+wMQSU VbgXInCVXsNOC+hzzZS6XI7kNEkNX9FY+cgUE1f+c8nto/Xt3zrpMrP9CVymFluZiLi2 /biQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hj7o0Y3r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 43/62] target/arm: Reorg get_phys_addr_disabled Date: Sun, 3 Jul 2022 13:54:00 +0530 Message-Id: <20220703082419.770989-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use a switch. Do not apply memattr or shareability for Stage2 translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the pseudocode in AArch64.S1DisabledOutput. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 115 +++++++++++++++++++++++++++-------------------- 1 file changed, 67 insertions(+), 48 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0f4b9b0166..3a098882a6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2278,64 +2278,83 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - uint64_t hcr; - uint8_t memattr; + uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); + uint8_t memattr, shareability; - if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { - int r_el = regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax = arm_pamax(env_archcpu(env)); - uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; - int addrtop, tbi; + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + memattr = 0x00; /* unused, but Device, nGnRnE */ + shareability = 0; /* unused, but non-shareable */ + break; - tbi = aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type == MMU_INST_FETCH) { - tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr = 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr = 0xff; /* Normal, WB, RWA */ } - tbi = (tbi >> extract64(address, 55, 1)) & 1; - addrtop = (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) != 0) { - fi->type = ARMFault_AddressSize; - fi->level = 0; - fi->stage2 = false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address = extract64(address, 0, 52); + shareability = 0; /* non-shareable */ + goto check_range; } + /* fall through */ + + default: + if (access_type == MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr = 0xee; /* Normal, WT, RA, NT */ + } else { + memattr = 0x44; /* Normal, NC, No */ + } + shareability = 2; /* Outer sharable */ + } else { + memattr = 0x00; /* unused, but Device, nGnRnE */ + shareability = 0; /* non-shareable */ + } + /* fall through */ + + check_range: + { + int r_el = regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax = arm_pamax(env_archcpu(env)); + uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; + int addrtop, tbi; + + tbi = aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type == MMU_INST_FETCH) { + tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi = (tbi >> extract64(address, 55, 1)) & 1; + addrtop = (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) != 0) { + fi->type = ARMFault_AddressSize; + fi->level = 0; + fi->stage2 = false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of + * the bits above PAMax are zero, so logically we only + * need to clear the top byte for TBI. But it's clearer + * to follow the pseudocode set of addrdesc.paddress. + */ + address = extract64(address, 0, 52); + } + } + break; } result->phys = address; result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; result->page_size = TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr = arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability = 0; result->cacheattrs.is_s2_format = false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr = 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr = 0xff; /* Normal, WB, RWA */ - } - } else if (access_type == MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr = 0xee; /* Normal, WT, RA, NT */ - } else { - memattr = 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability = 2; /* outer sharable */ - } else { - memattr = 0x00; /* Device, nGnRnE */ - } + result->cacheattrs.shareability = shareability; result->cacheattrs.attrs = memattr; return 0; } From patchwork Sun Jul 3 08:24:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586846 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2936378mab; Sun, 3 Jul 2022 02:20:46 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sgNRwko8yuJnx2NOuHVt9uIQPMCmaarGyxqFuyqGWZ/Jg08C9cHeFGEW6m/+X+VeSbI4eb X-Received: by 2002:a81:2f45:0:b0:317:71c7:fcdc with SMTP id v66-20020a812f45000000b0031771c7fcdcmr27371761ywv.73.1656840046856; Sun, 03 Jul 2022 02:20:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656840046; cv=none; d=google.com; s=arc-20160816; b=xXKSdluGvPcy2jd0terJ8bDKK0rx361TUfk/Afa5XUS4+unJJo4CiwzcO2ztqeK8lF QDk9D+pwmCmYtuKH0g6IFLuReBY9BTKDntx/Tb46NnpfrmTaUjUMeXvhLDPotkRdy/4v dpAIPOHdssfE74RnPWKcnerYk3iRbFveHSnt/p0OrEx8GWTx8O8DQbHGi7+zI+6WBPMn vfAkZNh9LBUOrNxyn1rm5JuoqkYVbeX0xV6DnFdKwcjza5JRKDQUyh6IbKy3Kcyu0e8m GOGR61lkQm9oWFF+nzsoAsv9YHgXHVbcjUqnsadmhv3WGXsz3auo7wmbsVO6m0E9HCUg n/3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2GREabbEg+nDIDAuvpznWWqWDzHWosOK+NnY9rFGuOE=; b=iIoobLJb3bYxtFf1H6LowjJKi/58MUILA6cAHafUUopCFtgUuWcxAKqI9J8rPEEKlK vjjEajmWnBMlIezdzJT8fRKyJQXAOq0mR8kuv+T3afkPptq7HVEmSrqTBk9GyYBsBLfq OQgwJ6Awam3ysaiiEMSHoPe5uXlfoqkpv7+bVGLO83wsip4HiKag0sxbTycKEE1F7S9V lb4LuIS3cE1dkc4wZGmctNyZYRepFC5UIoDUIjN07bybi828frlhu506SD2C88Uzo+2v daH69Ty2N6NZ7iFGqXStFACMitY8cZNFqrU1Zg7Weoegi7um+Eq3nZKvETaLvZ2Fw2T6 vv4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZvUEkPZp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS} Date: Sun, 3 Jul 2022 13:54:01 +0530 Message-Id: <20220703082419.770989-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not yet used, but add mmu indexes for 1-1 mapping to physical addresses. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 4 ++++ target/arm/ptw.c | 9 +++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6f702f58d9..931808f2e7 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -40,6 +40,6 @@ struct PageEntryExtra { }; #endif -#define NB_MMU_MODES 8 +#define NB_MMU_MODES 10 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dd577a08bc..c5aec164ba 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2934,6 +2934,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, + /* * These are not allocated TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3a098882a6..7510a9276a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -179,6 +179,11 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_S: + /* No translation for physical address spaces. */ + return true; + default: g_assert_not_reached(); } @@ -2284,6 +2289,8 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_S: memattr = 0x00; /* unused, but Device, nGnRnE */ shareability = 0; /* unused, but non-shareable */ break; @@ -2574,6 +2581,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, is_secure = arm_is_secure_below_el3(env); break; case ARMMMUIdx_Stage2: + case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -2582,6 +2590,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, break; case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: From patchwork Sun Jul 3 08:24:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586849 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2937504mab; Sun, 3 Jul 2022 02:23:53 -0700 (PDT) X-Google-Smtp-Source: AGRyM1un9EIcF09TH023Qn3oD5waR0ZJQjeRRoV4z8ktBtu+SdQTBxaL5qE2EuCBOAWcnfBFkKSH X-Received: by 2002:a25:9ac9:0:b0:66e:4531:d3aa with SMTP id t9-20020a259ac9000000b0066e4531d3aamr89772ybo.182.1656840233032; Sun, 03 Jul 2022 02:23:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656840233; cv=none; d=google.com; s=arc-20160816; b=l9huhWAkSEvuiayZmVWhQkNU7TSSXwnY8En+VsHo773xCuwfNvuVvCGPWFK9OOiiiN y0pj/egHYi6WHsROoCn9QLS/zeAj5p4yHOBfXsw1RSlwEJYbQeGqHpk6wZvlovCenT5G wg429cdpcaoHvEIIu6SHx8kgsXUhEnglJ8DvG5hEIbJ0zBeQev9xtq4wTEESrkV5TdV9 MsYe8IYBgEIc7pe2p40W3W4Oy1X3Z7FlePCbvQHAttfvSi5vxLfEECd53MnPcGDvuHbx H6BCKETLo+bsI4pjLlCF3Ag+CjsnQXcIukiTG1oI3LJeHYmvxyhGbE6q4Rg8zMxU3LO0 fEdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0aCiSl53YzA2hANru329Wrf7w6Qosp+yjx/RWCF2Qxk=; b=x8KZa9YwsQJ8pv5ZipoOgh2gDk0YvKTmf00XsZLx52bRxidajUBT3NLvG5Pn6PgSfV U8PSMY7i0149GeLZ7TYWwIVqflXhvo4yhNSNR+/55/GQqxvPEhYg7JIbg+J5pBZ2vAQp do8IBmI88DrT//gb3HC7iid4zxJDBi2LtQQZANiac1tLQc8ZTuY5RyRpK7CDtNNWglsJ JsLrH7TOe9JPCpeQuU1FuM2VQH/18G/CgADHQdCgMUAN8EZcNaFvkdVUuJ5kutUCqtBy OtmpsleXqCpJ8zWrksPT6wI5UiAc2NrKeOTr1p76fIGXl9v5IeWmRTu/AYd7Yq9iy8db AdwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RjDNJ84/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 45/62] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx Date: Sun, 3 Jul 2022 13:54:02 +0530 Message-Id: <20220703082419.770989-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb. Flush the tlb when invalidating stage 1+2 translations. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 20 +++++++++++--------- target/arm/helper.c | 4 +++- 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 931808f2e7..ddbb2db1b9 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -40,6 +40,6 @@ struct PageEntryExtra { }; #endif -#define NB_MMU_MODES 10 +#define NB_MMU_MODES 12 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c5aec164ba..8ea9f08511 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2938,6 +2938,15 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, + /* + * Used for second stage of an S12 page table walk, or for descriptor + * loads during first stage of an S1 page table walk. Note that both + * are in use simultaneously for SecureEL2: the security state for + * the S2 ptw is selected by the NS bit from the S1 ptw. + */ + ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, + /* * These are not allocated TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. @@ -2945,15 +2954,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, - /* - * Not allocated a TLB: used only for second stage of an S12 page - * table walk, or for descriptor loads during first stage of an S1 - * page table walk. Note that if we ever want to have a TLB for this - * then various TLB flush insns which currently are no-ops or flush - * only stage 1 MMU indexes will need to change to flush stage 2. - */ - ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage2_S = 4 | ARM_MMU_IDX_NOTLB, /* * M-profile. @@ -2984,6 +2984,8 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(E3), + TO_CORE_BIT(Stage2), + TO_CORE_BIT(Stage2_S), TO_CORE_BIT(MUser), TO_CORE_BIT(MPriv), diff --git a/target/arm/helper.c b/target/arm/helper.c index 176be48c46..499577f24e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4332,7 +4332,9 @@ static int alle1_tlbmask(CPUARMState *env) */ return (ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0); + ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_Stage2 | + ARMMMUIdxBit_Stage2_S); } static int e2_tlbmask(CPUARMState *env) From patchwork Sun Jul 3 08:24:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586851 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2939177mab; Sun, 3 Jul 2022 02:27:10 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sOJOzWR9G6BBf+UROwu6Ma1i+QiK2Ho1Jn/e8r4THesPXD6h1t1jHXQINInykxHkxPr3cp X-Received: by 2002:a81:1388:0:b0:31c:6fcd:dad4 with SMTP id 130-20020a811388000000b0031c6fcddad4mr10881943ywt.219.1656840429926; Sun, 03 Jul 2022 02:27:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656840429; cv=none; d=google.com; s=arc-20160816; b=r6mP40vThN7QmputSo8Mq62EUHF8/MgPZV4WmgLXgoaxbgQjTJNevkUttsvkv8uMqR vwHB1+ZdaKYpBEc6mN3xNk2FolWG2AI5pfppTF+QMAnO0mR8bTL4+FWgi02PRffcI/97 V8vqaMF5YRwem/tJN7knpdmkHDPGrXfUeyqRGH8hthXPUmibFiO9QxtnxrKUBGqb8zTc 6RSH76pBSo2lrbbayDKMRY5YC1U4pyWyp0rtnBH8Jw7QDxR1zpLo2wf9twTC4mzo4WeU xc+5oyjvi09gt0m9Ya8UlYIBRvmRtHyqM5lQbqDgTgktPz9NjWk1StgJVZWZT0GrR1Of G1VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AgrCDzDvTqOdWxJ0VR4VmcOIV2B9QnGlk8qFxEZQR4I=; b=w2JgW1s1HeNVeEh8sfQi1MRnLv/EmK0wKgCCUQ1IESw6A5SfHag6wGwBzNAN3yswxV Z4Daw172bpzBEnMotc1RsMh97ZoCvPAyY7CiZHZrczZ/DTa/eCNwnDrlqFlY+nVdvSca KmNlAH7mIvt8CIqezIZ7xU8Wmlu7r+3HA6jQ9XKbc90W7nCQRdjdTvRg3K7Onvz0kipF QzfjcL3QuHZ7VT3+w5e9XTbbPxcQJ6DVPV0YUF5ZOghVWgE8MhXiAbP2LOskAoJTAby1 V6qF+Aw13hErZn7ZwkgUF3BvjcdLn4/ETGsn3KFcwTTl/bFdQjv2BknhuAlEGTv4nJ8+ KccQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OxUyRGI4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 46/62] target/arm: Use softmmu tlbs for page table walking Date: Sun, 3 Jul 2022 13:54:03 +0530 Message-Id: <20220703082419.770989-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and arm_ldq_ptw. Use probe_access_extra to find the host address, and if so use a host load. If the probe fails, we've got our fault info already. On the off chance that page tables are not in RAM, continue to use the address_space_ld* functions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/ptw.c | 206 +++++++++++++++++++++++----------------- target/arm/tlb_helper.c | 17 +++- 3 files changed, 139 insertions(+), 89 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8ea9f08511..e5e3084ec9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -231,6 +231,8 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; +typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -720,6 +722,9 @@ typedef struct CPUArchState { struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; + /* Optional fault info across tlb lookup. */ + ARMMMUFaultInfo *tlb_fi; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7510a9276a..ed25f4b91e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/range.h" +#include "exec/exec-all.h" #include "cpu.h" #include "internals.h" #include "idau.h" @@ -191,52 +192,58 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } -static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) -{ - /* - * For an S1 page table walk, the stage 1 attributes are always - * some form of "this is Normal memory". The combined S1+S2 - * attributes are therefore only Device if stage 2 specifies Device. - * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00, - * ie when cacheattrs.attrs bits [3:2] are 0b00. - * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie - * when cacheattrs.attrs bit [2] is 0. - */ - assert(cacheattrs.is_s2_format); - if (hcr & HCR_FWB) { - return (cacheattrs.attrs & 0x4) == 0; - } else { - return (cacheattrs.attrs & 0xc) == 0; - } -} - /* Translate a S1 pagetable walk through S2 if needed. */ -static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure_ptr, - ARMMMUFaultInfo *fi) +static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, + bool *is_secure_ptr, void **hphys, hwaddr *gphys, + ARMMMUFaultInfo *fi) { bool is_secure = *is_secure_ptr; ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + MemTxAttrs attrs = {}; + PageEntryExtra extra; + int flags; - if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - GetPhysAddrResult s2 = {}; - uint64_t hcr; - int ret; + if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) + || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { + s2_mmu_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + } - ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - is_secure, false, &s2, fi); - if (ret) { - assert(fi->type != ARMFault_None); - fi->s2addr = addr; - fi->stage2 = true; - fi->s1ptw = true; - fi->s1ns = !is_secure; - return ~0; + env->tlb_fi = fi; + flags = probe_access_extra(env, addr, MMU_DATA_LOAD, + arm_to_core_mmu_idx(s2_mmu_idx), + true, hphys, &attrs, &extra, 0); + env->tlb_fi = NULL; + + if (unlikely(flags & TLB_INVALID_MASK)) { + assert(fi->type != ARMFault_None); + fi->s2addr = addr; + fi->stage2 = true; + fi->s1ptw = true; + fi->s1ns = !is_secure; + return false; + } + + if (s2_mmu_idx == ARMMMUIdx_Stage2 || s2_mmu_idx == ARMMMUIdx_Stage2_S) { + uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); + uint8_t s2attrs = FIELD_EX64(extra.x, PAGEENTRYEXTRA, ATTRS); + bool is_device; + + /* + * For an S1 page table walk, the stage 1 attributes are always + * some form of "this is Normal memory". The combined S1+S2 + * attributes are therefore only Device if stage 2 specifies Device. + * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00, + * ie when s2attrs bits [3:2] are 0b00. + * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie + * when s2attrs bit [2] is 0. + */ + if (hcr & HCR_FWB) { + is_device = (s2attrs & 0x4) == 0; + } else { + is_device = (s2attrs & 0xc) == 0; } - hcr = arm_hcr_el2_eff_secstate(env, is_secure); - if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { + if ((hcr & HCR_PTW) && is_device) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -246,24 +253,19 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->stage2 = true; fi->s1ptw = true; fi->s1ns = !is_secure; - return ~0; + return false; } - - if (arm_is_secure_below_el3(env)) { - /* Check if page table walk is to secure or non-secure PA space. */ - if (is_secure) { - is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); - } else { - is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); - } - *is_secure_ptr = is_secure; - } else { - assert(!is_secure); - } - - addr = s2.phys; } - return addr; + + if (is_secure) { + /* Check if page table walk is to secure or non-secure PA space. */ + *is_secure_ptr = !(attrs.secure + ? env->cp15.vstcr_el2.raw_tcr & VSTCR_SW + : env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + + *gphys = extra.x & R_PAGEENTRYEXTRA_PA_MASK; + return true; } /* All loads done in the course of a page table walk go through here. */ @@ -271,56 +273,88 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - MemTxAttrs attrs = {}; - MemTxResult result = MEMTX_OK; - AddressSpace *as; + void *hphys; + hwaddr gphys; uint32_t data; + bool be; - addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure = is_secure; - as = arm_addressspace(cs, attrs); - if (fi->s1ptw) { + if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + &hphys, &gphys, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - if (regime_translation_big_endian(env, mmu_idx)) { - data = address_space_ldl_be(as, addr, attrs, &result); + + be = regime_translation_big_endian(env, mmu_idx); + if (likely(hphys)) { + /* Page tables are in RAM, and we have the host address. */ + if (be) { + data = ldl_be_p(hphys); + } else { + data = ldl_le_p(hphys); + } } else { - data = address_space_ldl_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs = { .secure = is_secure }; + AddressSpace *as = arm_addressspace(cs, attrs); + MemTxResult result = MEMTX_OK; + + if (be) { + data = address_space_ldl_be(as, gphys, attrs, &result); + } else { + data = address_space_ldl_le(as, gphys, attrs, &result); + } + if (unlikely(result != MEMTX_OK)) { + fi->type = ARMFault_SyncExternalOnWalk; + fi->ea = arm_extabort_type(result); + return 0; + } } - if (result == MEMTX_OK) { - return data; - } - fi->type = ARMFault_SyncExternalOnWalk; - fi->ea = arm_extabort_type(result); - return 0; + return data; } static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - MemTxAttrs attrs = {}; - MemTxResult result = MEMTX_OK; - AddressSpace *as; + void *hphys; + hwaddr gphys; uint64_t data; + bool be; - addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure = is_secure; - as = arm_addressspace(cs, attrs); - if (fi->s1ptw) { + if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + &hphys, &gphys, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - if (regime_translation_big_endian(env, mmu_idx)) { - data = address_space_ldq_be(as, addr, attrs, &result); + + be = regime_translation_big_endian(env, mmu_idx); + if (likely(hphys)) { + /* Page tables are in RAM, and we have the host address. */ + if (be) { + data = ldq_be_p(hphys); + } else { + data = ldq_le_p(hphys); + } } else { - data = address_space_ldq_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs = { .secure = is_secure }; + AddressSpace *as = arm_addressspace(cs, attrs); + MemTxResult result = MEMTX_OK; + + if (be) { + data = address_space_ldq_be(as, gphys, attrs, &result); + } else { + data = address_space_ldq_le(as, gphys, attrs, &result); + } + if (unlikely(result != MEMTX_OK)) { + fi->type = ARMFault_SyncExternalOnWalk; + fi->ea = arm_extabort_type(result); + return 0; + } } - if (result == MEMTX_OK) { - return data; - } - fi->type = ARMFault_SyncExternalOnWalk; - fi->ea = arm_extabort_type(result); - return 0; + return data; } static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 28495ff525..d0b978bb9a 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -208,10 +208,21 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); - ARMMMUFaultInfo fi = {}; GetPhysAddrResult res = {}; + ARMMMUFaultInfo local_fi, *fi; int ret; + /* + * Allow S1_ptw_translate to see any fault generated here. + * Since this may recurse, read and clear. + */ + fi = cpu->env.tlb_fi; + if (fi) { + cpu->env.tlb_fi = NULL; + } else { + fi = memset(&local_fi, 0, sizeof(local_fi)); + } + /* * Walk the page table and (if the mapping exists) add the page * to the TLB. On success, return true. Otherwise, if probing, @@ -220,7 +231,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, */ ret = get_phys_addr(&cpu->env, address, access_type, core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &res, &fi); + &res, fi); if (likely(!ret)) { PageEntryExtra extra = {}; @@ -252,7 +263,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } } #else From patchwork Sun Jul 3 08:24:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586833 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2928907mab; Sun, 3 Jul 2022 02:05:52 -0700 (PDT) X-Google-Smtp-Source: AGRyM1t92pbQ+m8MfBAvjySCnOqwrQK7nMvWB7qVgIRc98p2Wri03aYwHqEN0cPQMiu7v6RYoy0+ X-Received: by 2002:a0d:ff81:0:b0:317:bfca:bb33 with SMTP id p123-20020a0dff81000000b00317bfcabb33mr26326025ywf.516.1656839152656; Sun, 03 Jul 2022 02:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839152; cv=none; d=google.com; s=arc-20160816; b=UZRM+Bw7PCMWslU6mcoa//T3cjxc8HC3E4jj3t46vBN587w9hOIYavP2NVpRbNQ1XV ebH2b2/WfxvyzBxiqpcS7Ss0eraG1pTSJXD2zwvgpuT7SqaO+oIH6bmoL0Psg3GKaFvR faASSzTXRiJHuaclI9UbA9EnBIE47+LbEbmh0PzyzzVHVGIBi2q38g8JqTxhEBKR9qdH vM4TMnGjT+qxBgMqubnPkSkVIJqgD8jjEnYe2f8rZMx0wsgoB8gUxmKfAgtZ0UOENNWx bSzVZuhmR9jZ/TrhoNIJi/KwLfUDQwijrdLK6ofWYK/dhde9jIDsSYJEnDufjuof0QaY Bokg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Vebk4kjBIMxCcXUePIuYSzzVW8J2WXPtrvs+wC4TX+s=; b=vKUFqHqVAGl05oqQ0I6zmeGJsnCtVbzd4BpThhwconhWglq1aFKZiwRBBkPhsOpHm4 oWyA3l3xMfniMQMZoKnpuHUCA5b4zKiS3xXqxubOf3p7sCCzsamr4B85j2X9Uyc/cTX+ Pod06XKttXgx/+z/aAO7ARY22yCO3XcS00Izn2JGmrOeGSQ3164A/P/Xb3sUd46vleXf G8g37REajF/SFphc9KXf1TjWJpxXnrzoLiAwFsJEZ1p7XaDUmXM5K2mbzSQWuM0F4kdQ yapcDp7fA9oa72X7nX+AwRZ20WEzOKPy8x0B0jH68RGcci2zmsT6Vk3YP1YzxIUl/rZV RdLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DEhuURVF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 47/62] target/arm: Hoist check for disabled stage2 translation. Date: Sun, 3 Jul 2022 13:54:04 +0530 Message-Id: <20220703082419.770989-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If stage2 translation is disabled, E1&0 translation is just a single stage. Use the complete single stage path rather than breaking out of the middle of the two stage path. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ed25f4b91e..84d72ac249 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2433,9 +2433,10 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, if (mmu_idx != s1_mmu_idx) { /* * Call ourselves recursively to do the stage 1 and then stage 2 - * translations if mmu_idx is a two-stage regime. + * translations if mmu_idx is a two-stage regime, and stage2 enabled. */ - if (arm_feature(env, ARM_FEATURE_EL2)) { + if (arm_feature(env, ARM_FEATURE_EL2) && + !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { hwaddr ipa; int s1_prot; int ret; @@ -2448,9 +2449,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, ret = get_phys_addr_with_secure(env, address, access_type, s1_mmu_idx, is_secure, result, fi); - /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, - is_secure)) { + /* If S1 fails, return early. */ + if (ret) { return ret; } From patchwork Sun Jul 3 08:24:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586837 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2931637mab; Sun, 3 Jul 2022 02:10:55 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sQM1Xg7asKqgzOOSkV9DWnfxYIa2bLT6bq5G+ukqujsmJtcaHDgOEcKC++3uCxz4P4y5wP X-Received: by 2002:a05:6638:d96:b0:33c:d6f8:4a8c with SMTP id l22-20020a0566380d9600b0033cd6f84a8cmr13216279jaj.146.1656839455278; Sun, 03 Jul 2022 02:10:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839455; cv=none; d=google.com; s=arc-20160816; b=KCwvxjaAGiALfvcPiWVdjvfrWridoVr/FAALnpf0BPRV6yNGNGuDok/hg4yCk3QHLy jlvxCuXBMGglmYUdCCnuhYJglO+dLPFcUGeh6qMRTCJOtdG912UOjiwMQgdQ6YDx33Km bB69RgIxP2csVKithlAXVydu3mOpKCLUTyj6rqTtbgpyrWTjP4lVi0GWmm3SODcrlnFI wpu9Y7MemRUoYX4TFROSPuqXZOylCrMWqwU2tgL8GNbP6yX/2PH7XcAvITpEC3Ws05+S 4+6mlut920S80kcQLbmIJCSaW0S26c8xHrUbBkBmRgBn7IiDPZvEXGJ519k0u7BpjfE0 pm5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XNrURcON7TIYKeGGNMcTizSaXpWHipL5ZGIPBDvwmUY=; b=WhSIMVsViyV3DVZH3xJnNZIgsLjhJJ9awi/u/kZOna2D3TVlUW/CsyIPWMDsrOURUT pNskIfT0FMga6NNzKK+yFDzjKlxqov/EBGH0py+Dy/bn+o5BWxIVJ1QrB9wgjQa8Qkm6 QRF1Ckh2J06ci2bZm3RpTlDragjTJ4U5Y3PU8vNe2RP3Ym6PFMHdVIQ5RjScdAegef8S t9yMpNWP8dzVXXdBokZkf8SpmeLpRJcao6qUZPzgs1BYjRkViLMTdqtZtsYG3WqKOLnM x0NgOWLQ9hxETZNzYHdTEVrKhk8iwqZUyM03QcRZgvfBvGDbuu5G7zlQvGrvuV0JN40b aMhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eBlyHVso; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 48/62] target/arm: Split out get_phys_addr_twostage Date: Sun, 3 Jul 2022 13:54:05 +0530 Message-Id: <20220703082419.770989-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/ptw.c | 182 +++++++++++++++++++++++++---------------------- 1 file changed, 96 insertions(+), 86 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 84d72ac249..993f015904 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2400,6 +2400,95 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, return 0; } +static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx s1_mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + hwaddr ipa; + int s1_prot; + int ret; + bool ipa_secure; + ARMCacheAttrs cacheattrs1; + ARMMMUIdx s2_mmu_idx; + bool is_el0; + uint64_t hcr; + + ret = get_phys_addr_with_secure(env, address, access_type, s1_mmu_idx, + is_secure, result, fi); + + /* If S1 fails, return early. */ + if (ret) { + return ret; + } + + ipa = result->phys; + if (is_secure) { + /* Select TCR based on the NS bit from the S1 walk. */ + ipa_secure = !(result->attrs.secure + ? env->cp15.vstcr_el2.raw_tcr & VSTCR_SW + : env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } else { + ipa_secure = false; + } + + s2_mmu_idx = (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); + is_el0 = s1_mmu_idx == ARMMMUIdx_Stage1_E0; + + /* + * S1 is done, now do S2 translation. + * Save the stage1 results so that we may merge + * prot and cacheattrs later. + */ + s1_prot = result->prot; + cacheattrs1 = result->cacheattrs; + memset(result, 0, sizeof(*result)); + + ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + ipa_secure, is_el0, result, fi); + fi->s2addr = ipa; + + /* Combine the S1 and S2 perms. */ + result->prot &= s1_prot; + + /* If S2 fails, return early. */ + if (ret) { + return ret; + } + + /* Combine the S1 and S2 cache attributes. */ + hcr = arm_hcr_el2_eff_secstate(env, is_secure); + if (hcr & HCR_DC) { + /* + * HCR.DC forces the first stage attributes to + * Normal Non-Shareable, + * Inner Write-Back Read-Allocate Write-Allocate, + * Outer Write-Back Read-Allocate Write-Allocate. + * Do not overwrite Tagged within attrs. + */ + if (cacheattrs1.attrs != 0xf0) { + cacheattrs1.attrs = 0xff; + } + cacheattrs1.shareability = 0; + } + result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1, + result->cacheattrs); + + /* Check if IPA translates to secure or non-secure PA space. */ + if (is_secure) { + if (ipa_secure) { + result->attrs.secure = + !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); + } else { + result->attrs.secure = + !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) || + (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); + } + } + return 0; +} + /** * get_phys_addr - get the physical address for this virtual address * @@ -2437,93 +2526,14 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, */ if (arm_feature(env, ARM_FEATURE_EL2) && !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { - hwaddr ipa; - int s1_prot; - int ret; - bool ipa_secure; - ARMCacheAttrs cacheattrs1; - ARMMMUIdx s2_mmu_idx; - bool is_el0; - uint64_t hcr; - - ret = get_phys_addr_with_secure(env, address, access_type, - s1_mmu_idx, is_secure, result, fi); - - /* If S1 fails, return early. */ - if (ret) { - return ret; - } - - ipa = result->phys; - if (is_secure) { - /* Select TCR based on the NS bit from the S1 walk. */ - ipa_secure = !(result->attrs.secure - ? env->cp15.vstcr_el2.raw_tcr & VSTCR_SW - : env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); - } else { - ipa_secure = false; - } - - s2_mmu_idx = (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); - is_el0 = mmu_idx == ARMMMUIdx_E10_0; - - /* - * S1 is done, now do S2 translation. - * Save the stage1 results so that we may merge - * prot and cacheattrs later. - */ - s1_prot = result->prot; - cacheattrs1 = result->cacheattrs; - memset(result, 0, sizeof(*result)); - - ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - ipa_secure, is_el0, result, fi); - fi->s2addr = ipa; - - /* Combine the S1 and S2 perms. */ - result->prot &= s1_prot; - - /* If S2 fails, return early. */ - if (ret) { - return ret; - } - - /* Combine the S1 and S2 cache attributes. */ - hcr = arm_hcr_el2_eff_secstate(env, is_secure); - if (hcr & HCR_DC) { - /* - * HCR.DC forces the first stage attributes to - * Normal Non-Shareable, - * Inner Write-Back Read-Allocate Write-Allocate, - * Outer Write-Back Read-Allocate Write-Allocate. - * Do not overwrite Tagged within attrs. - */ - if (cacheattrs1.attrs != 0xf0) { - cacheattrs1.attrs = 0xff; - } - cacheattrs1.shareability = 0; - } - result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1, - result->cacheattrs); - - /* Check if IPA translates to secure or non-secure PA space. */ - if (is_secure) { - if (ipa_secure) { - result->attrs.secure = - !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); - } else { - result->attrs.secure = - !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) - || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); - } - } - return 0; - } else { - /* - * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); + return get_phys_addr_twostage(env, address, access_type, + s1_mmu_idx, is_secure, + result, fi); } + /* + * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. + */ + mmu_idx = s1_mmu_idx; } /* From patchwork Sun Jul 3 08:24:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586853 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2940380mab; Sun, 3 Jul 2022 02:29:49 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uCOvQFs2V3SfSNLaSbqde+ei1IE7wyHF+sjrk1TWcLs4abEZinA+r/b3SMvTy62TOKJDsk X-Received: by 2002:a25:2541:0:b0:66e:2e17:7526 with SMTP id l62-20020a252541000000b0066e2e177526mr4924314ybl.312.1656840589072; Sun, 03 Jul 2022 02:29:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656840589; cv=none; d=google.com; s=arc-20160816; b=zlXohXEy50TaEb5cE1CO2hpnWynJ1+pQspdLoQyYiqMV0Jt2LgulWcgNp8N0Am+KYX cQK+Gpbm7sJLhfctnye17nptju0C2fSWQpnT8faz8HvF11x3qtTcy0iQZr76ap7tlE2x +Soyx2LoCi/RpkluCxh8HWSCC0dT6tlfleYNthYFAFBeh8ldznA6D6rpI3JiZuZbZ8if Toy77XU8zy1DBuwhqXtXduUzkob6ZfdlQGShhwdNXeEvz+vtAZDcK2QpOsxznzGimBQm kVwNnAIPp9YpppjAvEpJcddscBIL0BBdCtnzA1HFf+FmIodKeoqeJMbMA7JtpaMF+ovi 9oKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IFacPIEDusd1hE7rtQmwmoagq5wzcnFBcC4AqTaOWD4=; b=QanNvjNasODeOHhrcS2mkxwW+FWeFjCsSkJf7iT58/kbnQ/mp+OCmc+g56mhPSOsAZ YrHmC+BWS20PDCOdRnZIQuY1lvHv0VkY7RLulAj6L/KgmD/WHq+qUa74f1BBrWp2N8sk pcUs4UkB50uIlIR1YlrlPrRzNXAvU8c/x9rl+CW6OKaFv81JPreR2qS+C7KSwgg0dFs2 SZWIRAivti9RCAXQjRqziTIbfDzRCjyHuS1LCIvAAdbSOKkrp508GjGRnb804p5BES5Y n1yWbsdjdqCGfaHfVSB7AxR2ny20Dn1VU1JrcjnH9XTXpP9qseNPRjVyNqYlZt4QAcWA 2gsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rI43nmAv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines Date: Sun, 3 Jul 2022 13:54:06 +0530 Message-Id: <20220703082419.770989-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The return type of the functions is already bool, but in a few instances we used an integer type with the return statement. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 993f015904..a2c441d947 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2376,7 +2376,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, fi->type = ARMFault_AddressSize; fi->level = 0; fi->stage2 = false; - return 1; + return true; } /* @@ -2397,7 +2397,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, result->cacheattrs.is_s2_format = false; result->cacheattrs.shareability = shareability; result->cacheattrs.attrs = memattr; - return 0; + return false; } static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, @@ -2408,7 +2408,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, { hwaddr ipa; int s1_prot; - int ret; + bool ret; bool ipa_secure; ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; @@ -2486,7 +2486,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); } } - return 0; + return false; } /** From patchwork Sun Jul 3 08:24:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586840 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2933993mab; Sun, 3 Jul 2022 02:15:47 -0700 (PDT) X-Google-Smtp-Source: AGRyM1ulhpMg1vA0r5P7Q0BPBzSl8Vd3Qsr6GOIaVel+ZI/UB5foco/uUwn7GgUMog7rd36wz/Pm X-Received: by 2002:a81:9185:0:b0:31c:7e9b:255b with SMTP id i127-20020a819185000000b0031c7e9b255bmr6874573ywg.2.1656839747238; Sun, 03 Jul 2022 02:15:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839747; cv=none; d=google.com; s=arc-20160816; b=FOyl+QcNfvCjjjz0awcko3Or8/ULdq6UFHgx2kwemcOBIZy438lmHN9P6RVpPYm0+t xY2BrvuwH1Ju9gA7CyHdBKoAzN75SJX0mEvRizKuUy8zOSlVedi4bZNWKyvtVN76ZAc2 skc5adQafbCU/3yo5VGlgJQ4kaSnfSP2E1nnZagDl1x6MwL5e6KPwCFwJuErigU0Nq9o RAmtmsMFtCc3YQL8CEfPnKhKpUtjQrFQXLuEdE29TBiAhd46Wr+AZkr75YciNqEa6qgD 9Ye0LMsjN1WmzMjV9SfK9j+jsPinfeERKaOGNQvqhCmINzdxPhrNYNHgecg4DnfGGjY/ jF0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UbIrVuD695ihfGEi7s3Q8RXV9zhlhUlzREnUxvNfINo=; b=Mp/ecxO0smuPtVVF8+g3n/8+8wMkLcv1QySrZ8sYSFarTnYUOOP2/Qga+wimdjZQye SDkkuGjTVfDCVeTJrFRpmSTM0LnPJBJ10z8dsEJW3xuWam5H0hXJogChvszmT2i6eI2B 0MmgPr70F+qB4XOLmRDOogGC7BRIQHGMcrmV/l0v0dnhaAJ3swcd66iywlanBngCyKLa lrqPN588VTgL22LcEnwdgTenWRPThyMk0Dft1Hz5I6XrQ9FT9hOGNXq1zx47+cnaFyxD 7XbMvRd1WBfkqvdNls9XxDLOG++kwte63LMSzfh9pLfJhGbpd8z9mDBEpv1KAp4sqH7A VMww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KIWcNY28; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation Date: Sun, 3 Jul 2022 13:54:07 +0530 Message-Id: <20220703082419.770989-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If stage2 is disabled, we do not need to adjust mmu_idx. Below, we'll use get_phys_addr_lpae and not recurse. Adjust regime_is_user so that it can be used for E10_0. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a2c441d947..e42286b4c1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -90,6 +90,7 @@ static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: @@ -99,10 +100,6 @@ static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) return true; default: return false; - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - g_assert_not_reached(); } } @@ -2530,10 +2527,6 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, s1_mmu_idx, is_secure, result, fi); } - /* - * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. - */ - mmu_idx = s1_mmu_idx; } /* From patchwork Sun Jul 3 08:24:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586844 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2935397mab; Sun, 3 Jul 2022 02:18:40 -0700 (PDT) X-Google-Smtp-Source: AGRyM1t4ier5caymls2U0zcVoXqVzdQRsQN7gNpCoh/w7TgNgLFGy3SuzuVMQH5goM8hZgzaQi3O X-Received: by 2002:a81:11cb:0:b0:31c:7de9:4614 with SMTP id 194-20020a8111cb000000b0031c7de94614mr7373473ywr.23.1656839919996; Sun, 03 Jul 2022 02:18:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656839919; cv=none; d=google.com; s=arc-20160816; b=sqjNDxkutr6sMNxQlvwlDwgfOLh5dMO4dNFC4MFI91jT/VfC82cgd/R042xhfbMYKD 0ksk1LQzTtYGyPeX2Gd6h1aaRCPTSywJ0znrjx9qoZe9LxiDflRcYDlW8DYFL76fUrGt mSB4UWBXKNOLWh5bQYRyRJKGQXoKYRfkOvoF8HL+XLCsbD8ZkFshCu6PdVtAa5AaKgOO SbV4dGkWkdjxKJP0XrgSk+AQvoz0AcgEbWxXnOCDuj1FCN//SffXEdsoqZUILy/Z8rOs QUfl6PCZl7B8BP6SATmF5GDvNhTQK4n4IZDA+wD8ujoWZqTu1b4808ZDdInJE2+FjxZX ArdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nffg//dkzBQoqRm5IXNwBlQ5m5g6qr/efQ0ZTxyujnA=; b=ScB/D82kMT4MgSBz6f0wXRtjfyWArbJDvI+nlZGdCMMZcfxJsyVXk/oH2kECip+UvJ aL/MsbYKA8tQaVAKqyYGYs1RXdndZCLzoBUDKNl9TDyeS9kNFWs08p8/DRNd21vDem73 zxR33twxXdXyEVjaRW8I+kwFy4/mI9iFgIWDE1WsvtHgXWHlfCKBncEXp1ag4cLYos90 SaDCwl2eWB6l8Pu8M2+aqpfTki6CIUmUDB8zxNjCSOWe7bHGFthCTEYnVSAGGcO0MjKT 72nK3y6SIOVpcD7H1YRf1fsL9C1Zq1UtADJe4H3BKhHiXSEUGqIL+k8/X1pSmve5DtHi ADmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tDHaKxhX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 51/62] target/arm: Add ptw_idx argument to S1_ptw_translate Date: Sun, 3 Jul 2022 13:54:08 +0530 Message-Id: <20220703082419.770989-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist the computation of the mmu_idx for the ptw up to get_phys_addr_with_secure and get_phys_addr_twostage. This removes the duplicate check for stage2 disabled from the middle of the walk, performing it only once. Pass ptw_idx through get_phys_addr_{v5,v6,lpae} and arm_{ldl,ldq}_ptw. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 100 +++++++++++++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 33 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e42286b4c1..6eb61849d3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -17,7 +17,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, bool s1_is_el0, + ARMMMUIdx ptw_idx, bool is_secure, + bool s1_is_el0, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); @@ -190,21 +191,16 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, } /* Translate a S1 pagetable walk through S2 if needed. */ -static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, +static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, + ARMMMUIdx s2_mmu_idx, hwaddr addr, bool *is_secure_ptr, void **hphys, hwaddr *gphys, ARMMMUFaultInfo *fi) { bool is_secure = *is_secure_ptr; - ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; MemTxAttrs attrs = {}; PageEntryExtra extra; int flags; - if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) - || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - s2_mmu_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; - } - env->tlb_fi = fi; flags = probe_access_extra(env, addr, MMU_DATA_LOAD, arm_to_core_mmu_idx(s2_mmu_idx), @@ -267,7 +263,8 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, /* All loads done in the course of a page table walk go through here. */ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) + ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, + ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); void *hphys; @@ -275,7 +272,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, uint32_t data; bool be; - if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, &hphys, &gphys, fi)) { /* Failure. */ assert(fi->s1ptw); @@ -311,7 +308,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, } static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) + ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, + ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); void *hphys; @@ -319,7 +317,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, uint64_t data; bool be; - if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, &hphys, &gphys, fi)) { /* Failure. */ assert(fi->s1ptw); @@ -460,8 +458,8 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + ARMMMUIdx ptw_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int level = 1; uint32_t table; @@ -480,7 +478,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, fi->type = ARMFault_Translation; goto do_fault; } - desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -518,7 +516,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* Fine pagetable. */ table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -579,8 +577,8 @@ do_fault: static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + ARMMMUIdx ptw_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int level = 1; @@ -603,7 +601,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, fi->type = ARMFault_Translation; goto do_fault; } - desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -656,7 +654,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, ns = extract32(desc, 3, 1); /* Lookup l2 entry. */ table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -1011,7 +1009,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, bool s1_is_el0, + ARMMMUIdx ptw_idx, bool is_secure, + bool s1_is_el0, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); @@ -1237,7 +1236,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; nstable = extract32(tableattrs, 4, 1); - descriptor = arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, fi); + descriptor = arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, ptw_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -2408,7 +2407,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, bool ret; bool ipa_secure; ARMCacheAttrs cacheattrs1; - ARMMMUIdx s2_mmu_idx; + ARMMMUIdx s2_mmu_idx, s2_ptw_idx; bool is_el0; uint64_t hcr; @@ -2430,7 +2429,13 @@ static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, ipa_secure = false; } - s2_mmu_idx = (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); + if (ipa_secure) { + s2_mmu_idx = ARMMMUIdx_Stage2_S; + s2_ptw_idx = ARMMMUIdx_Phys_S; + } else { + s2_mmu_idx = ARMMMUIdx_Stage2; + s2_ptw_idx = ARMMMUIdx_Phys_NS; + } is_el0 = s1_mmu_idx == ARMMMUIdx_Stage1_E0; /* @@ -2442,7 +2447,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, s2_ptw_idx, ipa_secure, is_el0, result, fi); fi->s2addr = ipa; @@ -2514,19 +2519,49 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, bool is_secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); + ARMMMUIdx s1_mmu_idx, s2_mmu_idx, ptw_idx; - if (mmu_idx != s1_mmu_idx) { + switch (mmu_idx) { + case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + do_disabled: + /* Checking Phys early avoids special casing later vs regime_el. */ + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); + + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* First stage lookup uses second stage for ptw. */ + ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + break; + + case ARMMMUIdx_E10_0: + s1_mmu_idx = ARMMMUIdx_Stage1_E0; + goto do_twostage; + case ARMMMUIdx_E10_1: + s1_mmu_idx = ARMMMUIdx_Stage1_E1; + goto do_twostage; + case ARMMMUIdx_E10_1_PAN: + s1_mmu_idx = ARMMMUIdx_Stage1_E1_PAN; + do_twostage: /* * Call ourselves recursively to do the stage 1 and then stage 2 * translations if mmu_idx is a two-stage regime, and stage2 enabled. */ + s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; if (arm_feature(env, ARM_FEATURE_EL2) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { + !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { return get_phys_addr_twostage(env, address, access_type, s1_mmu_idx, is_secure, result, fi); } + /* fall through */ + + default: + /* Single stage and second stage uses physical for ptw. */ + ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + break; } /* @@ -2583,18 +2618,17 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, /* Definitely a real MMU, not an MPU */ if (regime_translation_disabled(env, mmu_idx, is_secure)) { - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + goto do_disabled; } if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, - is_secure, false, result, fi); + ptw_idx, is_secure, false, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - is_secure, result, fi); + ptw_idx, is_secure, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - is_secure, result, fi); + ptw_idx, is_secure, result, fi); } } From patchwork Sun Jul 3 08:24:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586830 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2925512mab; Sun, 3 Jul 2022 02:00:26 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sHZbyU01N42PUJWILlpqQUVnqgwaCvOKUFEWohIkEUEukR+oXBFnhdVyTY94iZZqFMlonD X-Received: by 2002:a05:6602:148b:b0:657:c59b:f336 with SMTP id a11-20020a056602148b00b00657c59bf336mr12363957iow.141.1656838826269; Sun, 03 Jul 2022 02:00:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656838826; cv=none; d=google.com; s=arc-20160816; b=uKcXsp5VsFfQcHgDNxR0nCk/3CJDZ1m7y76P3OrybUP6g9fkew3pIcXuo/MuM6+DDN reSb2gmJ3QJtoO14n3BEPLJrpMHSLYvVBmtX3zRgrHRFTVUmjbYk1sUSLd1rPSCVwtg3 f2UCqpLZgWe0J/ZNfxzmAxQMEpkm973kcILQ2mCNjAZNFSm5xZ1jDBjwdId5LLvSlKHF l2SfRNzS7iOhB1RCs+DU9tqiJy+9vNHHP8GGjqZGXxy1dj6JPj7gRWqH9X/7hJFrMF5B CKUu/WbqGpHZBBnZI2xwWOoZOO7indyZAtrtzhlXkcxTtAmUyZv8FMJpjvgDh0swpWvo JLvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xDKyQFWitNBJWXzXzZdHuAgrjnn69YMfQIBCMUU20+g=; b=pRFblIUO71laSlxLRcOGJlx7TgXsGYLav1TOPzg2VCXzq3+FVNB0SPjbwcfxcmrLYz DGFf3hHbi98kbFGpTRe0jqDTDrJyGKfxX4uNQlZyQpO1mCMWATA1pTRy6EpkVfVk7QYY bqVALrUbDziyY6b2rSgyvKAzeKkQJR58WtVgxoGVhcQiO/Q7SpTZR4QRtOP/3cBkxw89 yIHz/h+d8eoygcQBVvJ/Vsd19aeIuYCwdmNyNObCRpqjXbCtAb251hRG1JcAVNs/TayB rbv/SPmzEr4dX5yNytsI6wupRbBjbFu8PnQe6k7Jyb4AJSV9IPPaS2rlhqjhiFGUte0x 9LJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Jji1TAl/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 52/62] target/arm: Add isar predicates for FEAT_HAFDBS Date: Sun, 3 Jul 2022 13:54:09 +0530 Message-Id: <20220703082419.770989-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The MMFR1 field may indicate support for hardware update of access flag alone, or access flag and dirty bit. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e5e3084ec9..6484abcf1f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4034,6 +4034,16 @@ static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; } +static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; +} + +static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; +} + static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; From patchwork Sun Jul 3 08:24:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586847 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2936658mab; Sun, 3 Jul 2022 02:21:27 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tFdE3qYtt178TU9JWMQ1DG9rDKZ+Dc9LdVlpgsSHk/K9kYT/b9oFg3/CCSulDERFGh7E8H X-Received: by 2002:a81:3841:0:b0:31b:c5fe:ffbc with SMTP id f62-20020a813841000000b0031bc5feffbcmr26217007ywa.200.1656840087731; Sun, 03 Jul 2022 02:21:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656840087; cv=none; d=google.com; s=arc-20160816; b=LVkZHcjZebZ02VpQGsJMlsmu9g0Grc/g4MQ3ITs4kVJNPiXxwgOEIqwjh4elhDMyba 9bDWewRw67P3sfeeF1C7dBGBsloIXLtbCw6zZHBH+ySK3zI1jcBHcymCYYdhXyRJNGa6 0DLNuj6Jf1nf5azexE+t+r3MzTFcomcea0AL73L1jBFH06E9PcvTrP/Zd7gtZGOwHnZk LuY+hplvrc9EXlfimPzfa0HoLXURJHOUTkwknyITCp1mn+GF9W/gVsduEIS6TVit/gD+ Y3ZysR5oNEmjrWGP29Db1aqRX4jtSpbVQjNqvWF4XL7zTtTm70RzULkTI7a+P/uvLRDj lAXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vXjecf38qLWvkQbYd8UNuP/WXCTyajLWLbhxCGCynp8=; b=GwEuS2fwasiIDDND7tko3MS0kaiv2ROnwpXdoMo/MxwsmRiV80EadqwaSJjS4ouKOE zJpYiryt5Qss9yo/lRPzWk05QwuwqNAXFvLk6FHlq34N4Nh+E2Dm/Rsl+sN7IoFythb+ PdKafXsmCqW9lRicqNuvl8lkNNCs92IqDyqkuvNZLgKBH0jqsjjQeLX2DvtzpoOrflIl QwuXUImIkBZU8YDlEZMRIJtHMCLFD/1kpvGPEhTzbcev8eKiei/n59LB0jh78v9B9A1l 0VhAg2RAYt70pjRsYhAup+PUwR9uUuYJXV1OUu9+M+V+APIfpUJ8jE48/VTiBepBRRjr Zgaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IYIgnSva; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 53/62] target/arm: Extract HA and HD in aa64_va_parameters Date: Sun, 3 Jul 2022 13:54:10 +0530 Message-Id: <20220703082419.770989-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1bbe4d950e..f2a421972e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1004,6 +1004,8 @@ typedef struct ARMVAParameters { bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ bool ds : 1; + bool ha : 1; + bool hd : 1; } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index 499577f24e..9aea6ad5f4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10626,7 +10626,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k, tsz_oob, ds; + bool epd, hpd, using16k, using64k, tsz_oob, ds, ha, hd; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu = env_archcpu(env); @@ -10644,6 +10644,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, epd = false; sh = extract32(tcr, 12, 2); ps = extract32(tcr, 16, 3); + ha = extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd = extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds = extract64(tcr, 32, 1); } else { /* @@ -10668,6 +10670,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract64(tcr, 42, 1); } ps = extract64(tcr, 32, 3); + ha = extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd = extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds = extract64(tcr, 59, 1); } @@ -10739,6 +10743,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .using64k = using64k, .tsz_oob = tsz_oob, .ds = ds, + .ha = ha, + .hd = ha & hd, }; } From patchwork Sun Jul 3 08:24:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586843 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2935217mab; Sun, 3 Jul 2022 02:18:18 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vV/MGpX3da4jGN+CP1Yd9I+LC7dYN3T/dreguHni1fflq427e8Du3lmNxWPuzTZF/jK63Y X-Received: by 2002:a81:19d6:0:b0:313:551a:8e85 with SMTP id 205-20020a8119d6000000b00313551a8e85mr27542486ywz.136.1656839897984; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 54/62] target/arm: Split out S1TranslateResult type Date: Sun, 3 Jul 2022 13:54:11 +0530 Message-Id: <20220703082419.770989-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Consolidate the results of S1_ptw_translate in one struct. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 60 ++++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6eb61849d3..32937ec7db 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -190,13 +190,18 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } +typedef struct { + bool is_secure; + void *hphys; + hwaddr gphys; +} S1TranslateResult; + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, ARMMMUIdx s2_mmu_idx, hwaddr addr, - bool *is_secure_ptr, void **hphys, hwaddr *gphys, + bool is_secure, S1TranslateResult *res, ARMMMUFaultInfo *fi) { - bool is_secure = *is_secure_ptr; MemTxAttrs attrs = {}; PageEntryExtra extra; int flags; @@ -204,7 +209,7 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, env->tlb_fi = fi; flags = probe_access_extra(env, addr, MMU_DATA_LOAD, arm_to_core_mmu_idx(s2_mmu_idx), - true, hphys, &attrs, &extra, 0); + true, &res->hphys, &attrs, &extra, 0); env->tlb_fi = NULL; if (unlikely(flags & TLB_INVALID_MASK)) { @@ -250,14 +255,13 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, } } - if (is_secure) { - /* Check if page table walk is to secure or non-secure PA space. */ - *is_secure_ptr = !(attrs.secure - ? env->cp15.vstcr_el2.raw_tcr & VSTCR_SW - : env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); - } + /* Check if page table walk is to secure or non-secure PA space. */ + res->is_secure = (is_secure && + !(attrs.secure + ? env->cp15.vstcr_el2.raw_tcr & VSTCR_SW + : env->cp15.vtcr_el2.raw_tcr & VTCR_NSW)); - *gphys = extra.x & R_PAGEENTRYEXTRA_PA_MASK; + res->gphys = extra.x & R_PAGEENTRYEXTRA_PA_MASK; return true; } @@ -267,36 +271,34 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - void *hphys; - hwaddr gphys; + S1TranslateResult s1; uint32_t data; bool be; - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, - &hphys, &gphys, fi)) { + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)) { /* Failure. */ assert(fi->s1ptw); return 0; } be = regime_translation_big_endian(env, mmu_idx); - if (likely(hphys)) { + if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ if (be) { - data = ldl_be_p(hphys); + data = ldl_be_p(s1.hphys); } else { - data = ldl_le_p(hphys); + data = ldl_le_p(s1.hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = is_secure }; + MemTxAttrs attrs = { .secure = s1.is_secure }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; if (be) { - data = address_space_ldl_be(as, gphys, attrs, &result); + data = address_space_ldl_be(as, s1.gphys, attrs, &result); } else { - data = address_space_ldl_le(as, gphys, attrs, &result); + data = address_space_ldl_le(as, s1.gphys, attrs, &result); } if (unlikely(result != MEMTX_OK)) { fi->type = ARMFault_SyncExternalOnWalk; @@ -312,36 +314,34 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - void *hphys; - hwaddr gphys; + S1TranslateResult s1; uint64_t data; bool be; - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, - &hphys, &gphys, fi)) { + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)) { /* Failure. */ assert(fi->s1ptw); return 0; } be = regime_translation_big_endian(env, mmu_idx); - if (likely(hphys)) { + if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ if (be) { - data = ldq_be_p(hphys); + data = ldq_be_p(s1.hphys); } else { - data = ldq_le_p(hphys); + data = ldq_le_p(s1.hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = is_secure }; + MemTxAttrs attrs = { .secure = s1.is_secure }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; if (be) { - data = address_space_ldq_be(as, gphys, attrs, &result); + data = address_space_ldq_be(as, s1.gphys, attrs, &result); } else { - data = address_space_ldq_le(as, gphys, attrs, &result); + data = address_space_ldq_le(as, s1.gphys, attrs, &result); } if (unlikely(result != MEMTX_OK)) { fi->type = ARMFault_SyncExternalOnWalk; From patchwork Sun Jul 3 08:24:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586848 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2936731mab; Sun, 3 Jul 2022 02:21:40 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sakkvlSIyTQsD7eii4e7L2K4ERZNU02gsUFHv9C2MeWbVT1MmOt6bi3HV3sradwha8hsqJ X-Received: by 2002:a25:42d5:0:b0:66e:2cc8:c8e7 with SMTP id p204-20020a2542d5000000b0066e2cc8c8e7mr5297423yba.5.1656840100868; Sun, 03 Jul 2022 02:21:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656840100; cv=none; d=google.com; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult Date: Sun, 3 Jul 2022 13:54:12 +0530 Message-Id: <20220703082419.770989-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 32937ec7db..b5105a2e92 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -192,6 +192,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, typedef struct { bool is_secure; + bool be; void *hphys; hwaddr gphys; } S1TranslateResult; @@ -261,6 +262,7 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, ? env->cp15.vstcr_el2.raw_tcr & VSTCR_SW : env->cp15.vtcr_el2.raw_tcr & VTCR_NSW)); + res->be = regime_translation_big_endian(env, mmu_idx); res->gphys = extra.x & R_PAGEENTRYEXTRA_PA_MASK; return true; } @@ -273,7 +275,6 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, CPUState *cs = env_cpu(env); S1TranslateResult s1; uint32_t data; - bool be; if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)) { /* Failure. */ @@ -281,10 +282,9 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, return 0; } - be = regime_translation_big_endian(env, mmu_idx); if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (be) { + if (s1.be) { data = ldl_be_p(s1.hphys); } else { data = ldl_le_p(s1.hphys); @@ -295,7 +295,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; - if (be) { + if (s1.be) { data = address_space_ldl_be(as, s1.gphys, attrs, &result); } else { data = address_space_ldl_le(as, s1.gphys, attrs, &result); @@ -316,7 +316,6 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, CPUState *cs = env_cpu(env); S1TranslateResult s1; uint64_t data; - bool be; if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)) { /* Failure. */ @@ -324,10 +323,9 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, return 0; } - be = regime_translation_big_endian(env, mmu_idx); if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (be) { + if (s1.be) { data = ldq_be_p(s1.hphys); } else { data = ldq_le_p(s1.hphys); @@ -338,7 +336,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; - if (be) { + if (s1.be) { data = address_space_ldq_be(as, s1.gphys, attrs, &result); } else { data = address_space_ldq_le(as, s1.gphys, attrs, &result); From patchwork Sun Jul 3 08:24:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586850 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2937892mab; Sun, 3 Jul 2022 02:24:45 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sH/PX557lM+A2Cm6tvOpFtODi6Dm1MDU4B07rwqdPP+cGv4UxPiXt6QLmP6W6kwSQFMUYW X-Received: by 2002:a25:bb82:0:b0:66b:b066:1a9f with SMTP id y2-20020a25bb82000000b0066bb0661a9fmr24318189ybg.83.1656840285792; Sun, 03 Jul 2022 02:24:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656840285; cv=none; d=google.com; s=arc-20160816; b=ndt2mBCvBl3j4V4t9pFsnTHG4cgi8wV5mP+F+j0zJo5MgozWYVm+UrEnIi4EcEVdV5 Y5H+U88jZQeC2U3AklVaB6ygdxgDdztKpkdIEnnaO6pdY4rFvKgA9ZeGm64cOEyG08Sc IWZ7FYlnkMVyKZPptnFgRHrYMb4TBLd+qQNhe8Ibms9nB6GptEBEOE7Nj7mtOgCjcMyg o58PO/A09brU67RSMa90dKEOWYIf5vS0lLJ8ByvUhypnZzMp7/b3i7wiSln45z1YBIHA u1+HyDeSDnChbgg9KtgJ79aTrfITYHuyJCnhxuyq7h/MLaGdT7AALfwbjS7FvWhG4kFk v2lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wSNR2kbAW9oQa+mDxGRThKTDiu+IXYao0zmFIiXWIZ0=; b=K6Y7UX9uLXrGWBogYQgj5e+MaHzsxZmWCA7h6omqZbBN4aQDN9MtKq1M6oBxRZjhnI BuofeiVddyNsyVSwaE895DE+ifxW6GOXORu3efC5GYcUxHtjWCluckJJLX8i1VetKGNl B4C/tmPAnoxVTHclquT6q4W7Tp094AuObjpwO9YUxcJ0zbxM+hdrz6w5lGFLaQiEEgCH kuVnMLYJXP8Tk2SI56Gy5qofIlu+48TGzs3AYyHQyRt12QcAkjHcU4Uy8my/0kB1gB9/ M3fj4qaT9hzhiPISi2sZm7Mxy4dPZxd1nxeIU0LTj9H43ddf48mGZ6oQujcUeYh53QdZ 4WlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="T4ce/4Rj"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 56/62] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw Date: Sun, 3 Jul 2022 13:54:13 +0530 Message-Id: <20220703082419.770989-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Separate S1 translation from the actual lookup. Will enable lpae hardware updates. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 83 +++++++++++++++++++++++++----------------------- 1 file changed, 44 insertions(+), 39 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b5105a2e92..dee857ae89 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -268,37 +268,29 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, } /* All loads done in the course of a page table walk go through here. */ -static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, +static uint32_t arm_ldl_ptw(CPUARMState *env, const S1TranslateResult *s1, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - S1TranslateResult s1; uint32_t data; - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)) { - /* Failure. */ - assert(fi->s1ptw); - return 0; - } - - if (likely(s1.hphys)) { + if (likely(s1->hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (s1.be) { - data = ldl_be_p(s1.hphys); + if (s1->be) { + data = ldl_be_p(s1->hphys); } else { - data = ldl_le_p(s1.hphys); + data = ldl_le_p(s1->hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = s1.is_secure }; + MemTxAttrs attrs = { .secure = s1->is_secure }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; - if (s1.be) { - data = address_space_ldl_be(as, s1.gphys, attrs, &result); + if (s1->be) { + data = address_space_ldl_be(as, s1->gphys, attrs, &result); } else { - data = address_space_ldl_le(as, s1.gphys, attrs, &result); + data = address_space_ldl_le(as, s1->gphys, attrs, &result); } if (unlikely(result != MEMTX_OK)) { fi->type = ARMFault_SyncExternalOnWalk; @@ -309,37 +301,29 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, return data; } -static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, +static uint64_t arm_ldq_ptw(CPUARMState *env, const S1TranslateResult *s1, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - S1TranslateResult s1; uint64_t data; - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)) { - /* Failure. */ - assert(fi->s1ptw); - return 0; - } - - if (likely(s1.hphys)) { + if (likely(s1->hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (s1.be) { - data = ldq_be_p(s1.hphys); + if (s1->be) { + data = ldq_be_p(s1->hphys); } else { - data = ldq_le_p(s1.hphys); + data = ldq_le_p(s1->hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = s1.is_secure }; + MemTxAttrs attrs = { .secure = s1->is_secure }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; - if (s1.be) { - data = address_space_ldq_be(as, s1.gphys, attrs, &result); + if (s1->be) { + data = address_space_ldq_be(as, s1->gphys, attrs, &result); } else { - data = address_space_ldq_le(as, s1.gphys, attrs, &result); + data = address_space_ldq_le(as, s1->gphys, attrs, &result); } if (unlikely(result != MEMTX_OK)) { fi->type = ARMFault_SyncExternalOnWalk; @@ -467,6 +451,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, int domain = 0; int domain_prot; hwaddr phys_addr; + S1TranslateResult s1; uint32_t dacr; /* Pagetable walk. */ @@ -476,7 +461,10 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, fi->type = ARMFault_Translation; goto do_fault; } - desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, is_secure, &s1, fi)) { + goto do_fault; + } + desc = arm_ldl_ptw(env, &s1, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -514,7 +502,11 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* Fine pagetable. */ table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, + is_secure, &s1, fi)) { + goto do_fault; + } + desc = arm_ldl_ptw(env, &s1, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -590,6 +582,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, int domain_prot; hwaddr phys_addr; uint32_t dacr; + S1TranslateResult s1; bool ns; /* Pagetable walk. */ @@ -599,7 +592,10 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, fi->type = ARMFault_Translation; goto do_fault; } - desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, is_secure, &s1, fi)) { + goto do_fault; + } + desc = arm_ldl_ptw(env, &s1, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -652,7 +648,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, ns = extract32(desc, 3, 1); /* Lookup l2 entry. */ table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, + is_secure, &s1, fi)) { + goto do_fault; + } + desc = arm_ldl_ptw(env, &s1, fi); if (fi->type != ARMFault_None) { goto do_fault; } @@ -1228,13 +1228,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, */ tableattrs = is_secure ? 0 : (1 << 4); for (;;) { + S1TranslateResult s1; uint64_t descriptor; bool nstable; descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; nstable = extract32(tableattrs, 4, 1); - descriptor = arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, + !nstable, &s1, fi)) { + goto do_fault; + } + descriptor = arm_ldq_ptw(env, &s1, fi); if (fi->type != ARMFault_None) { goto do_fault; } From patchwork Sun Jul 3 08:24:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586855 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2942074mab; Sun, 3 Jul 2022 02:33:32 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sBfoT0m7DFFNu32h9qjj+uoNN/Da2D8tINkmJixo7E9XXHHZXtP0qoiDRszocFTXJ2Ffe2 X-Received: by 2002:a25:9f87:0:b0:669:4345:a8c0 with SMTP id u7-20020a259f87000000b006694345a8c0mr25237068ybq.472.1656840812866; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 57/62] target/arm: Add ARMFault_UnsuppAtomicUpdate Date: Sun, 3 Jul 2022 13:54:14 +0530 Message-Id: <20220703082419.770989-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fault type is to be used with FEAT_HAFDBS when the guest enables hw updates, but places the tables in memory where atomic updates are unsupported. Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index f2a421972e..b1a5219aa3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -344,6 +344,7 @@ typedef enum ARMFaultType { ARMFault_AsyncExternal, ARMFault_Debug, ARMFault_TLBConflict, + ARMFault_UnsuppAtomicUpdate, ARMFault_Lockdown, ARMFault_Exclusive, ARMFault_ICacheMaint, @@ -530,6 +531,9 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) case ARMFault_TLBConflict: fsc = 0x30; break; + case ARMFault_UnsuppAtomicUpdate: + fsc = 0x31; + break; case ARMFault_Lockdown: fsc = 0x34; break; From patchwork Sun Jul 3 08:24:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586858 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2943279mab; Sun, 3 Jul 2022 02:35:51 -0700 (PDT) X-Google-Smtp-Source: AGRyM1v2eDipqCaPKFVvTG2rPzyYC0kRfhpz+jLpJxXZlkI1eupwlMz5yPSuyyXmwK4C8BABXTj0 X-Received: by 2002:a81:4ed0:0:b0:31b:a0f1:31bd with SMTP id c199-20020a814ed0000000b0031ba0f131bdmr27557753ywb.22.1656840951354; Sun, 03 Jul 2022 02:35:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656840951; cv=none; d=google.com; s=arc-20160816; b=BuomejZGL9iioEvIjes8/zgirCabYTQkHSu9ov4sKdngeDpjJXlS+jyIn48vLXjWZM iSw+4oSX1B8fvsdlk/u1Ylvoa8J28RS9JUiKETse+nGREMGS1jnK4vW+GibUzuafD7Hb ER5e+oAK42IxiIvgAGuHoRBmfh7AEGY/MdaCek1tI8Kp+h3Rop0MvCGFuh/JLeus/vUM hzP7ndo1/Uo+ziB8tJ2FlYLp59p9iwyUJ7+R3w7Z4grRNU93KXYNcVtsyjZLILk6yYtA ivkkUF+WqkdeDLndcvaEMTYZpPTKVyBGjMzeKZ/u1MXGU1R0qbjatb/SZ59GhkgUXpIz mLlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RvxjhA/zJ6a4ine35bxeLnau/UxZrJIIYMcq6hlNPcQ=; b=PMqkUcJoVIjeHEb1WT3vzO6bos2/wYrfHwaOAHh6neLTRWtDrGJ182VdkmlmyhLg36 CQZ8umLu6xEA6x5aPTzLvP1QxYei8bioTNA6ysQd1CrzhrfkDnVaIgnrnb/c6moyliGe cbp2mR6KLuhYEb1O//QkV0WV4VxlkA4Nqn/F6mMk3BTGNVOVZjvwojtmZCE0GFmZkXVd IuZwHIcPBqI1fBAeSf2LDU0g/pIXAbgug47cEsJdTcNwiulh2sUn6uEr4yKuVFOTVW/O h1U/UUJ3HSjLzAT0OZqcDmU+8TI5fIS3BUbTw7X/bOwHELwdit4M7A8rk6N/QZvLmhRE OYww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wqccFChJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 58/62] target/arm: Remove loop from get_phys_addr_lpae Date: Sun, 3 Jul 2022 13:54:15 +0530 Message-Id: <20220703082419.770989-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The unconditional loop was used both to iterate over levels and to control parsing of attributes. Use an explicit goto in both cases. While this appears less clean for iterating over levels, we will need to jump back into the middle of this loop for atomic updates, which is even uglier. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 176 +++++++++++++++++++++++------------------------ 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index dee857ae89..a3f063e0bc 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1029,6 +1029,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; + S1TranslateResult s1; + uint64_t descriptor; + bool nstable; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1227,96 +1230,93 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * bits at each step. */ tableattrs = is_secure ? 0 : (1 << 4); - for (;;) { - S1TranslateResult s1; - uint64_t descriptor; - bool nstable; - descaddr |= (address >> (stride * (4 - level))) & indexmask; - descaddr &= ~7ULL; - nstable = extract32(tableattrs, 4, 1); - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, - !nstable, &s1, fi)) { - goto do_fault; - } - descriptor = arm_ldq_ptw(env, &s1, fi); - if (fi->type != ARMFault_None) { - goto do_fault; - } - - if (!(descriptor & 1) || - (!(descriptor & 2) && (level == 3))) { - /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; - } - - descaddr = descriptor & descaddrmask; - - /* - * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] - * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of - * descaddr are in [9:8]. Otherwise, if descaddr is out of range, - * raise AddressSizeFault. - */ - if (outputsize > 48) { - if (param.ds) { - descaddr |= extract64(descriptor, 8, 2) << 50; - } else { - descaddr |= extract64(descriptor, 12, 4) << 48; - } - } else if (descaddr >> outputsize) { - fault_type = ARMFault_AddressSize; - goto do_fault; - } - - if ((descriptor & 2) && (level < 3)) { - /* - * Table entry. The top five bits are attributes which may - * propagate down through lower levels of the table (and - * which are all arranged so that 0 means "no effect", so - * we can gather them up by ORing in the bits at each level). - */ - tableattrs |= extract64(descriptor, 59, 5); - level++; - indexmask = indexmask_grainsize; - continue; - } - /* - * Block entry at level 1 or 2, or page entry at level 3. - * These are basically the same thing, although the number - * of bits we pull in from the vaddr varies. Note that although - * descaddrmask masks enough of the low bits of the descriptor - * to give a correct page or table address, the address field - * in a block descriptor is smaller; so we need to explicitly - * clear the lower bits here before ORing in the low vaddr bits. - */ - page_size = (1ULL << ((stride * (4 - level)) + 3)); - descaddr &= ~(page_size - 1); - descaddr |= (address & (page_size - 1)); - /* Extract attributes from the descriptor */ - attrs = extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); - - if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { - /* Stage 2 table descriptors do not include any attribute fields */ - break; - } - /* Merge in attributes from table descriptors */ - attrs |= nstable << 3; /* NS */ - guarded = extract64(descriptor, 50, 1); /* GP */ - if (param.hpd) { - /* HPD disables all the table attributes except NSTable. */ - break; - } - attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - /* - * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 - * means "force PL1 access only", which means forcing AP[1] to 0. - */ - attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ - attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ - break; + next_level: + descaddr |= (address >> (stride * (4 - level))) & indexmask; + descaddr &= ~7ULL; + nstable = extract32(tableattrs, 4, 1); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, + !nstable, &s1, fi)) { + goto do_fault; } + descriptor = arm_ldq_ptw(env, &s1, fi); + if (fi->type != ARMFault_None) { + goto do_fault; + } + + if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { + /* Invalid, or the Reserved level 3 encoding */ + goto do_fault; + } + + descaddr = descriptor & descaddrmask; + + /* + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, + * raise AddressSizeFault. + */ + if (outputsize > 48) { + if (param.ds) { + descaddr |= extract64(descriptor, 8, 2) << 50; + } else { + descaddr |= extract64(descriptor, 12, 4) << 48; + } + } else if (descaddr >> outputsize) { + fault_type = ARMFault_AddressSize; + goto do_fault; + } + + if ((descriptor & 2) && (level < 3)) { + /* + * Table entry. The top five bits are attributes which may + * propagate down through lower levels of the table (and + * which are all arranged so that 0 means "no effect", so + * we can gather them up by ORing in the bits at each level). + */ + tableattrs |= extract64(descriptor, 59, 5); + level++; + indexmask = indexmask_grainsize; + goto next_level; + } + + /* + * Block entry at level 1 or 2, or page entry at level 3. + * These are basically the same thing, although the number + * of bits we pull in from the vaddr varies. Note that although + * descaddrmask masks enough of the low bits of the descriptor + * to give a correct page or table address, the address field + * in a block descriptor is smaller; so we need to explicitly + * clear the lower bits here before ORing in the low vaddr bits. + */ + page_size = (1ULL << ((stride * (4 - level)) + 3)); + descaddr &= ~(page_size - 1); + descaddr |= (address & (page_size - 1)); + /* Extract attributes from the descriptor */ + attrs = extract64(descriptor, 2, 10) + | (extract64(descriptor, 52, 12) << 10); + + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + /* Stage 2 table descriptors do not include any attribute fields */ + goto skip_attrs; + } + /* Merge in attributes from table descriptors */ + attrs |= nstable << 3; /* NS */ + guarded = extract64(descriptor, 50, 1); /* GP */ + if (param.hpd) { + /* HPD disables all the table attributes except NSTable. */ + goto skip_attrs; + } + attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + /* + * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 + * means "force PL1 access only", which means forcing AP[1] to 0. + */ + attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ + attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ + skip_attrs: + /* * Here descaddr is the final physical address, and attributes * are all in attrs. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae Date: Sun, 3 Jul 2022 13:54:16 +0530 Message-Id: <20220703082419.770989-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Always overriding fi->type was incorrect, as we would not properly propagate the fault type from S1_ptw_translate, or arm_ldq_ptw. Simplify things by providing a new label for reporting a translation fault. For other faults, store into fi directly. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a3f063e0bc..678ad2ac0c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1012,8 +1012,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); - /* Read an LPAE long-descriptor translation table. */ - ARMFaultType fault_type = ARMFault_Translation; uint32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1051,8 +1049,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * so our choice is to always raise the fault. */ if (param.tsz_oob) { - fault_type = ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } addrsize = 64 - 8 * param.tbi; @@ -1089,8 +1086,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, addrsize - inputsize); if (-top_bits != param.select) { /* The gap between the two regions is a Translation fault */ - fault_type = ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } } @@ -1122,7 +1118,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * Translation table walk disabled => Translation fault on TLB miss * Note: This is always 0 on 64-bit EL2 and EL3. */ - goto do_fault; + goto do_translation_fault; } if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { @@ -1153,8 +1149,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, if (param.ds && stride == 9 && sl2) { if (sl0 != 0) { level = 0; - fault_type = ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } startlevel = -1; } else if (!aarch64 || stride == 9) { @@ -1173,8 +1168,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, ok = check_s2_mmu_setup(cpu, aarch64, startlevel, inputsize, stride, outputsize); if (!ok) { - fault_type = ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } level = startlevel; } @@ -1196,7 +1190,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr |= extract64(ttbr, 2, 4) << 48; } else if (descaddr >> outputsize) { level = 0; - fault_type = ARMFault_AddressSize; + fi->type = ARMFault_AddressSize; goto do_fault; } @@ -1246,7 +1240,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; + goto do_translation_fault; } descaddr = descriptor & descaddrmask; @@ -1264,7 +1258,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr |= extract64(descriptor, 12, 4) << 48; } } else if (descaddr >> outputsize) { - fault_type = ARMFault_AddressSize; + fi->type = ARMFault_AddressSize; goto do_fault; } @@ -1321,9 +1315,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * Here descaddr is the final physical address, and attributes * are all in attrs. */ - fault_type = ARMFault_AccessFlag; if ((attrs & (1 << 8)) == 0) { /* Access flag */ + fi->type = ARMFault_AccessFlag; goto do_fault; } @@ -1340,8 +1334,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); } - fault_type = ARMFault_Permission; if (!(result->prot & (1 << access_type))) { + fi->type = ARMFault_Permission; goto do_fault; } @@ -1385,8 +1379,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, result->page_size = page_size; return false; -do_fault: - fi->type = fault_type; + do_translation_fault: + fi->type = ARMFault_Translation; + do_fault: fi->level = level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 || From patchwork Sun Jul 3 08:24:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586835 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2931020mab; Sun, 3 Jul 2022 02:09:54 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uWnFQc5WrgwGZQ9OCLuPT89OYUyxPI94r6fF1svdK8IGb9CSi2Hjcx5ZWVzdSytAo86f39 X-Received: by 2002:a25:580b:0:b0:66d:466c:fa79 with SMTP id m11-20020a25580b000000b0066d466cfa79mr23980546ybb.9.1656839394376; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 60/62] target/arm: Don't shift attrs in get_phys_addr_lpae Date: Sun, 3 Jul 2022 13:54:17 +0530 Message-Id: <20220703082419.770989-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Leave the upper and lower attributes in the place they originate from in the descriptor. Shifting them around is confusing, since one cannot read the bit numbers out of the manual. Also, new attributes have been added which would alter the shifts. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 678ad2ac0c..e7569ece33 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1018,7 +1018,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; target_ulong page_size; - uint32_t attrs; + uint64_t attrs; int32_t stride; int addrsize, inputsize, outputsize; TCR *tcr = regime_tcr(env, mmu_idx); @@ -1288,49 +1288,48 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr &= ~(page_size - 1); descaddr |= (address & (page_size - 1)); /* Extract attributes from the descriptor */ - attrs = extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); + attrs = descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 12)); if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { /* Stage 2 table descriptors do not include any attribute fields */ goto skip_attrs; } /* Merge in attributes from table descriptors */ - attrs |= nstable << 3; /* NS */ + attrs |= nstable << 5; /* NS */ guarded = extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ goto skip_attrs; } - attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ - attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ - attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ + attrs &= ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] => AP[1] */ + attrs |= extract32(tableattrs, 3, 1) << 7; /* APT[1] => AP[2] */ skip_attrs: /* * Here descaddr is the final physical address, and attributes * are all in attrs. */ - if ((attrs & (1 << 8)) == 0) { + if ((attrs & (1 << 10)) == 0) { /* Access flag */ fi->type = ARMFault_AccessFlag; goto do_fault; } - ap = extract32(attrs, 4, 2); + ap = extract32(attrs, 6, 2); if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { ns = mmu_idx == ARMMMUIdx_Stage2; - xn = extract32(attrs, 11, 2); + xn = extract64(attrs, 54, 2); result->prot = get_S2prot(env, ap, xn, s1_is_el0); } else { - ns = extract32(attrs, 3, 1); - xn = extract32(attrs, 12, 1); - pxn = extract32(attrs, 11, 1); + ns = extract32(attrs, 5, 1); + xn = extract64(attrs, 54, 1); + pxn = extract64(attrs, 53, 1); result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); } @@ -1354,10 +1353,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { result->cacheattrs.is_s2_format = true; - result->cacheattrs.attrs = extract32(attrs, 0, 4); + result->cacheattrs.attrs = extract32(attrs, 2, 4); } else { /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 0, 3); + uint8_t attrindx = extract32(attrs, 2, 3); uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <= 7); result->cacheattrs.is_s2_format = false; @@ -1372,7 +1371,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, if (param.ds) { result->cacheattrs.shareability = param.sh; } else { - result->cacheattrs.shareability = extract32(attrs, 6, 2); + result->cacheattrs.shareability = extract32(attrs, 8, 2); } result->phys = descaddr; From patchwork Sun Jul 3 08:24:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586852 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2939807mab; Sun, 3 Jul 2022 02:28:27 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uA8VU9t6P+J69a3meeNG34Fw4Hw1USf/MVZ1TD6j5CLwKHk9JsI2IZ25QJAh9WE4oaApTs X-Received: by 2002:a25:84c1:0:b0:668:cce5:42ce with SMTP id x1-20020a2584c1000000b00668cce542cemr25031717ybm.456.1656840507707; Sun, 03 Jul 2022 02:28:27 -0700 (PDT) ARC-Seal: i=1; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 61/62] target/arm: Consider GP an attribute in get_phys_addr_lpae Date: Sun, 3 Jul 2022 13:54:18 +0530 Message-Id: <20220703082419.770989-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both GP and DBM are in the upper attribute block. Extend the computation of attrs to include them, then simplify the setting of guarded. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e7569ece33..07ed49bd70 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1026,7 +1026,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, uint32_t el = regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); - bool guarded = false; S1TranslateResult s1; uint64_t descriptor; bool nstable; @@ -1288,7 +1287,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr &= ~(page_size - 1); descaddr |= (address & (page_size - 1)); /* Extract attributes from the descriptor */ - attrs = descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 12)); + attrs = descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { /* Stage 2 table descriptors do not include any attribute fields */ @@ -1296,7 +1295,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 5; /* NS */ - guarded = extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ goto skip_attrs; @@ -1348,7 +1346,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->cacheattrs.guarded = guarded; + result->cacheattrs.guarded = extract64(attrs, 50, 1); /* GP */ } if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { From patchwork Sun Jul 3 08:24:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 586864 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2945606mab; Sun, 3 Jul 2022 02:40:46 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uc2nEe47nQ3m7OyRVOjKEQH/ufCAkQ3fL8DIlGXtZQv+EiQD600TLX7iJjxPaJ1RwLfAwW X-Received: by 2002:a25:df07:0:b0:66c:93d4:a52c with SMTP id w7-20020a25df07000000b0066c93d4a52cmr25382723ybg.6.1656841246115; Sun, 03 Jul 2022 02:40:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656841246; cv=none; d=google.com; s=arc-20160816; b=nkC6MtgNlq2lOv4zyEo2gLHW5ptQdE/eJTTNyHaWj0YOU74sASk3lhGcPT4Mw+aYMz yWmcbss7FolwE/uI/LpXIfcaNlE0dgY4b+EFDWL9+aqXX7FzmLLHxbnsXxo0bd56Ayk/ QXVhYq0uNIsoKZdd/6zfJ/jGEczMNaIKnEFGm6w+KeVxODTV8mxYlJyAMcu+Dub3tVPx gZGRJbbQpKfweZieUTLKrGgvuraCvIgEs34cq8NbX14k4IV0meH9n7yOc7u6Gv/Z3tSw wX53rWbrxnTuyWQ0UHsCJCBmGvIpfft2VJSuMqnY+Cj8fh3MQDfUMee4wyXXs/V544Kn Y/0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7/Z8gbQenSvpu+j6hmlZ/8di1MxPW1VxNbRQmZjhvR4=; b=Ix999nMXieCyhwWpRsTCam6NrgLTrdeZfgV2FFbNJFPZjQ2/X6LJajHh/DA5b5+flZ g7LvCORXhjdsg2xjWwsplyW5wZEZTTBvWy7kEmoRRlivSrpZ86aRT35Ja9mqx4rbMSfn QhehBSLQUN6BlN8db/t8jUml30zjpKPa5OT0e/khBmg4+QTmKgbdWYHj4o1YT7/uXotg k2Rst1kxTPNT57xRWUl3G7jgMERlRVUtmhhIrqhaz4rhOLsxBikJ+I/yxlqinaoso3Dw mcO6EG7aW1oBEP/2MfJbp44jikRN01lN9mFBY5kOVhbtbB6mW3811ckv4UK5n4AnpxiA f5zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fkRvBdXw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 62/62] target/arm: Implement FEAT_HAFDBS Date: Sun, 3 Jul 2022 13:54:19 +0530 Message-Id: <20220703082419.770989-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Perform the atomic update for hardware management of the access flag and the dirty bit. A limitation of the implementation so far is that the page table must itself be writable. This is allowed because it is CONSTRAINED UNPREDICTABLE whether any atomic update happens at all. Any implementation is allowed to simply fall back on software update at any time. Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/ptw.c | 128 ++++++++++++++++++++++++++++++++-- 3 files changed, 123 insertions(+), 7 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 83b4410065..ccbb61feb1 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -30,6 +30,7 @@ the following architecture extensions: - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) +- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) - FEAT_HCX (Support for the HCRX_EL2 register) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 19188d6cc2..0eb2e46bbc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1030,6 +1030,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; + t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 07ed49bd70..608956bee6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -193,6 +193,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, typedef struct { bool is_secure; bool be; + bool rw; void *hphys; hwaddr gphys; } S1TranslateResult; @@ -205,11 +206,12 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, { MemTxAttrs attrs = {}; PageEntryExtra extra; - int flags; + CPUTLBEntry *entry; + int flags, s2_core_idx; env->tlb_fi = fi; - flags = probe_access_extra(env, addr, MMU_DATA_LOAD, - arm_to_core_mmu_idx(s2_mmu_idx), + s2_core_idx = arm_to_core_mmu_idx(s2_mmu_idx); + flags = probe_access_extra(env, addr, MMU_DATA_LOAD, s2_core_idx, true, &res->hphys, &attrs, &extra, 0); env->tlb_fi = NULL; @@ -222,6 +224,14 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, return false; } + /* + * The page must be in the tlb, because we just probed it. + * Remember if the page is also writable, for FEAT_HAFDBS. + */ + entry = tlb_entry(env, s2_core_idx, addr); + assert(tlb_hit(entry->addr_read, addr)); + res->rw = tlb_hit(tlb_addr_write(entry), addr); + if (s2_mmu_idx == ARMMMUIdx_Stage2 || s2_mmu_idx == ARMMMUIdx_Stage2_S) { uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); uint8_t s2attrs = FIELD_EX64(extra.x, PAGEENTRYEXTRA, ATTRS); @@ -334,6 +344,56 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, const S1TranslateResult *s1, return data; } +static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, + uint64_t new_val, const S1TranslateResult *s1, + ARMMMUFaultInfo *fi) +{ + uint64_t cur_val; + + if (unlikely(!s1->hphys)) { + fi->type = ARMFault_UnsuppAtomicUpdate; + fi->s1ptw = true; + return 0; + } + +#ifndef CONFIG_ATOMIC64 + /* + * We can't support the atomic operation on the host. We should be + * running in round-robin mode though, which means that we would only + * race with dma i/o. + */ + qemu_mutex_lock_iothread(); + if (s1->be) { + cur_val = ldq_be_p(s1->hphys); + if (cur_val == old_val) { + stq_be_p(s1->hphys, new_val); + } + } else { + cur_val = ldq_le_p(s1->hphys); + if (cur_val == old_val) { + stq_le_p(s1->hphys, new_val); + } + } + qemu_mutex_unlock_iothread(); +#else + if (s1->be) { + old_val = cpu_to_be64(old_val); + new_val = cpu_to_be64(new_val); + cur_val = qatomic_cmpxchg__nocheck((uint64_t *)s1->hphys, + old_val, new_val); + cur_val = be64_to_cpu(cur_val); + } else { + old_val = cpu_to_le64(old_val); + new_val = cpu_to_le64(new_val); + cur_val = qatomic_cmpxchg__nocheck((uint64_t *)s1->hphys, + old_val, new_val); + cur_val = le64_to_cpu(cur_val); + } +#endif + + return cur_val; +} + static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { @@ -1237,6 +1297,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, goto do_fault; } + restart_atomic_update: if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { /* Invalid, or the Reserved level 3 encoding */ goto do_translation_fault; @@ -1314,8 +1375,26 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, */ if ((attrs & (1 << 10)) == 0) { /* Access flag */ - fi->type = ARMFault_AccessFlag; - goto do_fault; + uint64_t new_des, old_des; + + /* + * If HA is disabled, or if the pte is not writable, + * pass on the access fault to software. + */ + if (!param.ha || !s1.rw) { + fi->type = ARMFault_AccessFlag; + goto do_fault; + } + + old_des = descriptor; + new_des = descriptor | (1 << 10); /* AF */ + descriptor = arm_casq_ptw(env, old_des, new_des, &s1, fi); + if (fi->type != ARMFault_None) { + goto do_fault; + } + if (old_des != descriptor) { + goto restart_atomic_update; + } } ap = extract32(attrs, 6, 2); @@ -1332,8 +1411,43 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, } if (!(result->prot & (1 << access_type))) { - fi->type = ARMFault_Permission; - goto do_fault; + uint64_t new_des, old_des; + + /* Writes may set dirty if DBM attribute is set. */ + if (!param.hd + || access_type != MMU_DATA_STORE + || !extract64(attrs, 51, 1) /* DBM */ + || !s1.rw) { + fi->type = ARMFault_Permission; + goto do_fault; + } + + old_des = descriptor; + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + new_des = descriptor | (1ull << 7); /* S2AP[1] */ + } else { + new_des = descriptor & ~(1ull << 7); /* AP[2] */ + } + + /* + * If the descriptor didn't change, then attributes weren't the + * reason for the permission fault, so deliver it. + */ + if (old_des == new_des) { + fi->type = ARMFault_Permission; + goto do_fault; + } + + descriptor = arm_casq_ptw(env, old_des, new_des, &s1, fi); + if (fi->type != ARMFault_None) { + goto do_fault; + } + if (old_des != descriptor) { + goto restart_atomic_update; + } + + /* Success: the page is now writable. */ + result->prot |= 1 << MMU_DATA_STORE; } if (ns) {