From patchwork Wed Jul 6 06:02:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Lew X-Patchwork-Id: 588244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1077C433EF for ; Wed, 6 Jul 2022 06:02:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229530AbiGFGC4 (ORCPT ); Wed, 6 Jul 2022 02:02:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229479AbiGFGCz (ORCPT ); Wed, 6 Jul 2022 02:02:55 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 082D322290; Tue, 5 Jul 2022 23:02:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657087373; x=1688623373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=0kW1VSyqTJhDf3jEF4wZYjvbzY3W1A1738qYXvtRQDk=; b=IwbJKK9apoeUO16Kvibb34WyM4stG+NRvvTzxvr+6fKZRv74svDryGD4 F5nY0Cvy22hZ/6LG+7gcpyDec0pdzpS5T45lVReZePT5xV6OzojFJAxgf VXuMAMJ433ak9gDpHOXDX94GNPRL9+n59lSqUQy8B9u0SJQhP8lSGulYC g=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 05 Jul 2022 23:02:52 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2022 23:02:52 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Jul 2022 23:02:52 -0700 Received: from hu-clew-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Jul 2022 23:02:51 -0700 From: Chris Lew To: , , CC: , , Subject: [PATCH 1/4] soc: qcom: smp2p: Introduce pending state for virtual irq Date: Tue, 5 Jul 2022 23:02:08 -0700 Message-ID: <1657087331-32455-2-git-send-email-quic_clew@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1657087331-32455-1-git-send-email-quic_clew@quicinc.com> References: <1657087331-32455-1-git-send-email-quic_clew@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If a smp2p change occurs while a virtual interrupt is disabled, smp2p should be able to resend that interrupt on enablement. This functionality requires the CONFIG_HARDIRQS_SW_RESEND to be enabled to reschedule the interrupts. To ensure the mask and unmask functions are called during enabled and disable, set the flag to disable lazy IRQ state handling (IRQ_DISABLE_UNLAZY). Signed-off-by: Chris Lew --- drivers/soc/qcom/smp2p.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index 59dbf4b61e6c..1c3259fe98be 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -101,6 +101,7 @@ struct smp2p_entry { struct irq_domain *domain; DECLARE_BITMAP(irq_enabled, 32); + DECLARE_BITMAP(irq_pending, 32); DECLARE_BITMAP(irq_rising, 32); DECLARE_BITMAP(irq_falling, 32); @@ -146,6 +147,7 @@ struct qcom_smp2p { unsigned local_pid; unsigned remote_pid; + int irq; struct regmap *ipc_regmap; int ipc_offset; int ipc_bit; @@ -217,8 +219,8 @@ static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) { struct smp2p_smem_item *in; struct smp2p_entry *entry; + unsigned long status; int irq_pin; - u32 status; char buf[SMP2P_MAX_ENTRY_NAME]; u32 val; int i; @@ -247,19 +249,22 @@ static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) status = val ^ entry->last_value; entry->last_value = val; + status |= *entry->irq_pending; /* No changes of this entry? */ if (!status) continue; - for_each_set_bit(i, entry->irq_enabled, 32) { - if (!(status & BIT(i))) - continue; - + for_each_set_bit(i, &status, 32) { if ((val & BIT(i) && test_bit(i, entry->irq_rising)) || (!(val & BIT(i)) && test_bit(i, entry->irq_falling))) { irq_pin = irq_find_mapping(entry->domain, i); handle_nested_irq(irq_pin); + + if (test_bit(i, entry->irq_enabled)) + clear_bit(i, entry->irq_pending); + else + set_bit(i, entry->irq_pending); } } } @@ -365,6 +370,8 @@ static int smp2p_irq_map(struct irq_domain *d, irq_set_chip_data(irq, entry); irq_set_nested_thread(irq, 1); irq_set_noprobe(irq); + irq_set_parent(irq, entry->smp2p->irq); + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); return 0; } @@ -609,6 +616,7 @@ static int qcom_smp2p_probe(struct platform_device *pdev) /* Kick the outgoing edge after allocating entries */ qcom_smp2p_kick(smp2p); + smp2p->irq = irq; ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qcom_smp2p_intr, IRQF_ONESHOT, From patchwork Wed Jul 6 06:02:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Lew X-Patchwork-Id: 587799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A09FCCA473 for ; Wed, 6 Jul 2022 06:02:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229479AbiGFGC6 (ORCPT ); Wed, 6 Jul 2022 02:02:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229576AbiGFGC5 (ORCPT ); Wed, 6 Jul 2022 02:02:57 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F90122294; Tue, 5 Jul 2022 23:02:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657087373; x=1688623373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=X1Xeb7Fgnw4Fu+51DpHFBm7BDpOqou5CXewNC9Ul0sQ=; b=ibboQN6TkmJqw3li3yS7KzmHdgBOqIh7lAj7B9nbfbwC1NMJrJr35PFw VphiSRjU4agSmu0yZdHIh5waK+Wa2UPZtQOrT4s3LoLd0JghRbL2GlPxZ pKEhHHNYiOPexQhExXSaOCwQxmZl4x8z/FDw1YYfMzT35hTvWlOUQGtaZ U=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 05 Jul 2022 23:02:53 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2022 23:02:52 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Jul 2022 23:02:52 -0700 Received: from hu-clew-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Jul 2022 23:02:52 -0700 From: Chris Lew To: , , CC: , , Subject: [PATCH 2/4] soc: qcom: smp2p: Add proper retrigger detection Date: Tue, 5 Jul 2022 23:02:09 -0700 Message-ID: <1657087331-32455-3-git-send-email-quic_clew@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1657087331-32455-1-git-send-email-quic_clew@quicinc.com> References: <1657087331-32455-1-git-send-email-quic_clew@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently, smp2p relies on the hwirq resend feature to retrigger irqs that were missed because the irq was disabled at the time of receiving it. The hwirq resend feature will retrigger the parent smp2p interrupt. In order to keep track of what children needed to be retriggered, the pending bitmap was added. After calling handle_nested_irq, smp2p checks if the interrupt is enabled and sets the pending bit if the interrupt is not enabled. There is a small window where a client can enable the interrupt between calling handle_nested_irq and checking if the interrupt is enabled. If this happens, the interrupt is never called when the parent smp2p interrupt is retriggered. Add the irq_retrigger callback so smp2p can know which child interrupts need to be retriggered. Set the pending bits accordingly. Signed-off-by: Chris Lew --- drivers/soc/qcom/smp2p.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index 1c3259fe98be..a94cddcb0298 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -260,11 +260,7 @@ static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) (!(val & BIT(i)) && test_bit(i, entry->irq_falling))) { irq_pin = irq_find_mapping(entry->domain, i); handle_nested_irq(irq_pin); - - if (test_bit(i, entry->irq_enabled)) - clear_bit(i, entry->irq_pending); - else - set_bit(i, entry->irq_pending); + clear_bit(i, entry->irq_pending); } } } @@ -353,11 +349,22 @@ static int smp2p_set_irq_type(struct irq_data *irqd, unsigned int type) return 0; } +static int smp2p_retrigger_irq(struct irq_data *irqd) +{ + struct smp2p_entry *entry = irq_data_get_irq_chip_data(irqd); + irq_hw_number_t irq = irqd_to_hwirq(irqd); + + set_bit(irq, entry->irq_pending); + + return 0; +} + static struct irq_chip smp2p_irq_chip = { .name = "smp2p", .irq_mask = smp2p_mask_irq, .irq_unmask = smp2p_unmask_irq, .irq_set_type = smp2p_set_irq_type, + .irq_retrigger = smp2p_retrigger_irq, }; static int smp2p_irq_map(struct irq_domain *d, From patchwork Wed Jul 6 06:02:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Lew X-Patchwork-Id: 588242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C09ACCA47F for ; Wed, 6 Jul 2022 06:02:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229628AbiGFGC5 (ORCPT ); Wed, 6 Jul 2022 02:02:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229484AbiGFGCz (ORCPT ); Wed, 6 Jul 2022 02:02:55 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26BD822295; Tue, 5 Jul 2022 23:02:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657087374; x=1688623374; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=2bdejReHpno5cbtrQjXdLhWumUnQnqp1aTK4h3lAwec=; b=CPxIN/bBi6CtTYd7KITPNolHfqVj9HEapBCfb0voY+B1FAjgWsBy5brP 8Bx1dzyO2DQ1zFvkrGO+vNihlP2wv9xdb/HdsEJvWyh1FzJM1jAfSTe/r mfjhYWptGPn3QPgbzCuydon0boVKnZp2oCcnpf0VenVsRk7wkDU38rJGy c=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 05 Jul 2022 23:02:53 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2022 23:02:53 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Jul 2022 23:02:52 -0700 Received: from hu-clew-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Jul 2022 23:02:52 -0700 From: Chris Lew To: , , CC: , , Subject: [PATCH 3/4] soc: qcom: smp2p: Add memory barrier for irq_pending Date: Tue, 5 Jul 2022 23:02:10 -0700 Message-ID: <1657087331-32455-4-git-send-email-quic_clew@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1657087331-32455-1-git-send-email-quic_clew@quicinc.com> References: <1657087331-32455-1-git-send-email-quic_clew@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is a very tight race where the irq_retrigger function is run on one cpu and the actual retrigger softirq is running on a second cpu. When this happens, there may be a chance that the second cpu will not see the updated irq_pending value from first cpu. Add a memory barrier to ensure that irq_pending is read correctly. Signed-off-by: Chris Lew --- drivers/soc/qcom/smp2p.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index a94cddcb0298..a1ea5f55c228 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -249,6 +249,9 @@ static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) status = val ^ entry->last_value; entry->last_value = val; + + /* Ensure irq_pending is read correctly */ + mb(); status |= *entry->irq_pending; /* No changes of this entry? */ @@ -356,6 +359,11 @@ static int smp2p_retrigger_irq(struct irq_data *irqd) set_bit(irq, entry->irq_pending); + /* Ensure irq_pending is visible to all cpus that retried interrupt + * can run on + */ + mb(); + return 0; } From patchwork Wed Jul 6 06:02:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Lew X-Patchwork-Id: 588243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 197BACCA481 for ; Wed, 6 Jul 2022 06:02:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229672AbiGFGC6 (ORCPT ); Wed, 6 Jul 2022 02:02:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229502AbiGFGC4 (ORCPT ); Wed, 6 Jul 2022 02:02:56 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 887C222298; Tue, 5 Jul 2022 23:02:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657087375; x=1688623375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=x69ZXl0q6YPIjoY3r38mvBjwXx/dRoW5Meq0IZxS9z0=; b=N7FF+YvAh83YLCpHxasi6CWXJ0yMnIF9QDOOdjtXzcUrx1zO6NiH+xgw mqR6mzdLiZGbtq1wYP6wKCmKT4/T3SjVpoJ3kFGD6ctMiNyhVpw5/ZuPc gTvJ24yV87gnwahZBbNWJXjEbfHeMEalLXDFRbyABRpl6HOZJf+v50usU c=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 05 Jul 2022 23:02:53 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2022 23:02:53 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Jul 2022 23:02:53 -0700 Received: from hu-clew-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Jul 2022 23:02:52 -0700 From: Chris Lew To: , , CC: , , , Tao Zhang Subject: [PATCH 4/4] soc: qcom: smp2p: Add remote_id into irq name Date: Tue, 5 Jul 2022 23:02:11 -0700 Message-ID: <1657087331-32455-5-git-send-email-quic_clew@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1657087331-32455-1-git-send-email-quic_clew@quicinc.com> References: <1657087331-32455-1-git-send-email-quic_clew@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Tao Zhang Changed smp2p irq devname from "smp2p" to "smp2p_", which makes the wakeup source distinguishable in irq wakeup prints. Signed-off-by: Tao Zhang Signed-off-by: Chris Lew --- drivers/soc/qcom/smp2p.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index a1ea5f55c228..21a0e84b16f4 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -541,6 +541,7 @@ static int qcom_smp2p_probe(struct platform_device *pdev) struct device_node *node; struct qcom_smp2p *smp2p; const char *key; + char *name; int irq; int ret; @@ -632,10 +633,16 @@ static int qcom_smp2p_probe(struct platform_device *pdev) qcom_smp2p_kick(smp2p); smp2p->irq = irq; + name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smp2p_%d", + smp2p->remote_pid); + if (!name) { + ret = -ENOMEM; + goto unwind_interfaces; + } ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qcom_smp2p_intr, IRQF_ONESHOT, - "smp2p", (void *)smp2p); + name, (void *)smp2p); if (ret) { dev_err(&pdev->dev, "failed to request interrupt\n"); goto unwind_interfaces;