From patchwork Thu Jul 7 08:15:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Satya Priya Kakitapalli \(Temp\)" X-Patchwork-Id: 588208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E617C43334 for ; Thu, 7 Jul 2022 08:18:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235202AbiGGISz (ORCPT ); Thu, 7 Jul 2022 04:18:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234919AbiGGISA (ORCPT ); Thu, 7 Jul 2022 04:18:00 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED7F14F188; Thu, 7 Jul 2022 01:16:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657181788; x=1688717788; h=from:to:cc:subject:date:message-id:mime-version; bh=pK51D6/KCwtEn5SHEF/Xv6jcS3+colyLJ58dPARzfUo=; b=cxcilQOVnEKZZ2/buX8s4HciTC4d0flRA3S95co9JgqWQYnagCEhjV/x /5jdat9odiYuWFquys7/8+UUgf3UnHXKljWFgTfziSZXFJ/Y0WNWTNOjs ZuXj43jOYKkUc9HiUy4f2EoItAY8JQoeK/Jc4Q/byF96fE4zlKKGfwhQJ g=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 07 Jul 2022 01:16:28 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2022 01:16:28 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 7 Jul 2022 01:16:27 -0700 Received: from c-skakit-linux.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 7 Jul 2022 01:16:23 -0700 From: Satya Priya To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: Konrad Dybcio , Stephen Boyd , Taniya Das , , , , , Taniya Das , "Satya Priya" Subject: [PATCH V2] arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resets Date: Thu, 7 Jul 2022 13:45:39 +0530 Message-ID: <1657181739-32052-1-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Taniya Das The lpass audio supports TX/RX/WSA block resets. Disable the LPASS PIL clock by default, boards can enable it if needed. Also to keep consistency update lpasscore to lpass_core. Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers") Signed-off-by: Taniya Das Signed-off-by: Satya Priya --- Changes since V1: - Updated the phandle reference in lpass_aon node. - As per Matthias' comment updated the commit text. arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 40e700c..73dddca 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2174,6 +2174,7 @@ clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; #clock-cells = <1>; + status = "disabled"; }; lpass_audiocc: clock-controller@3300000 { @@ -2185,6 +2186,7 @@ power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; #clock-cells = <1>; #power-domain-cells = <1>; + #reset-cells = <1>; }; lpass_aon: clock-controller@3380000 { @@ -2192,13 +2194,13 @@ reg = <0 0x03380000 0 0x30000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&lpasscore LPASS_CORE_CC_CORE_CLK>; + <&lpass_core LPASS_CORE_CC_CORE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; #clock-cells = <1>; #power-domain-cells = <1>; }; - lpasscore: clock-controller@3900000 { + lpass_core: clock-controller@3900000 { compatible = "qcom,sc7280-lpasscorecc"; reg = <0 0x03900000 0 0x50000>; clocks = <&rpmhcc RPMH_CXO_CLK>;