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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id f2-20020aa79682000000b0052ab7144de8sm6040776pfk.10.2022.07.11.23.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 23:20:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Shaobo Song , qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PULL 1/2] tcg: Fix returned type in alloc_code_gen_buffer_splitwx_memfd() Date: Tue, 12 Jul 2022 11:50:24 +0530 Message-Id: <20220712062025.197634-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712062025.197634-1-richard.henderson@linaro.org> References: <20220712062025.197634-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shaobo Song This fixes a bug in POSIX-compliant environments. Since we had allocated a buffer named 'tcg-jit' with read-write access protections we need a int type to combine these access flags and return it, whereas we had inexplicably return a bool type. It may cause an unnecessary protection change in tcg_region_init(). Cc: qemu-stable@nongnu.org Fixes: 7be9ebcf924c ("tcg: Return the map protection from alloc_code_gen_buffer") Signed-off-by: Shaobo Song Reviewed-by: Alex Bennée Message-Id: <20220624150216.3627-1-shnusongshaobo@gmail.com> Signed-off-by: Richard Henderson --- tcg/region.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/region.c b/tcg/region.c index 71ea81d671..88d6bb273f 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -548,7 +548,7 @@ static int alloc_code_gen_buffer_anon(size_t size, int prot, #ifdef CONFIG_POSIX #include "qemu/memfd.h" -static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) +static int alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) { void *buf_rw = NULL, *buf_rx = MAP_FAILED; int fd = -1; From patchwork Tue Jul 12 06:20:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 589784 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp3920443mab; Mon, 11 Jul 2022 23:42:23 -0700 (PDT) X-Google-Smtp-Source: AGRyM1up6du9hUtNbKXqO7sPWX/x+/Y2qrqyrLb2XAjIzfLTXyG6yonzh5iabUpd4TxJFujj76d1 X-Received: by 2002:a05:622a:1451:b0:31d:24ee:1ad3 with SMTP id v17-20020a05622a145100b0031d24ee1ad3mr16886381qtx.215.1657608142932; Mon, 11 Jul 2022 23:42:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657608142; cv=none; d=google.com; s=arc-20160816; b=cpapD5Xeg625S+pFA+l0ivwhLRMKrKxOFTKstFzx6PMqGXZohxRV5hnFhmYWPPV00O 8QJC+SinMuNbFqrnat8pW+pH6cGzGWH48CqNIDDaC68hvp2PWWVnlNYHDsZ5G4drv9gl qwbd8T4yAb7q6PD3QCfCEEYMCykAps/G5TGrI766dnZjPonx0wKopjZboFY1xDI543UF G6WcOQa8ND/OoTWcXxQ/MnvC9RXgV8Acb1rqGIXwrMe+j1CDmihrcY5vrIWGIWyCGV9u 6LrDPrg0Wk/xUcr709m0M2vzspAI7uUUGsqYLbwYvR0TlhjsgjDciS1uR54j1Pg46Hl+ BugQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ameaOYTaejX0n/etuEC9PIIeVKsPKESqsBuicmuydr8=; b=Kv/TQFrWXdyA87inganhpV8AyPOiW2xfOmE1L3B//vdyJQzYn7hwyMNGgzpFVlZx5g 0eHzAKJaGny3rdLhEOhaJy+5y9bXXngOdD6k0Bb+tgIPDmjKqQlMv0U0MF0msasjDzsy 2yZGOEE0oWBuGQvBBsq2vFLYMi2Suk0SdMFDBGed0sOBXrr0N8lXC4iXqE6mRQYjtMqX TYYStLA0vRCMXUYxqsXhqdHGAHSzZeOR6W2RApWNrnTk4ZazSN0/nihzhYeb62TGO40e wVTz/zzn/A5pNy6VXwYRlOMkMe7xsc3fJuTlgaVTnzw5hWng/W4N9zsKGFln2tLM9Mtx heBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IsMnhkWb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id f2-20020aa79682000000b0052ab7144de8sm6040776pfk.10.2022.07.11.23.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 23:20:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PULL 2/2] accel/tcg: Fix unaligned stores to s390x low-address-protected lowcore Date: Tue, 12 Jul 2022 11:50:25 +0530 Message-Id: <20220712062025.197634-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712062025.197634-1-richard.henderson@linaro.org> References: <20220712062025.197634-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Ilya Leoshkevich If low-address-protection is active, unaligned stores to non-protected parts of lowcore lead to protection exceptions. The reason is that in such cases tlb_fill() call in store_helper_unaligned() covers [0, addr + size) range, which contains the protected portion of lowcore. This range is too large. The most straightforward fix would be to make sure we stay within the original [addr, addr + size) range. However, if an unaligned access affects a single page, we don't need to call tlb_fill() in store_helper_unaligned() at all, since it would be identical to the previous tlb_fill() call in store_helper(), and therefore a no-op. If an unaligned access covers multiple pages, this situation does not occur. Therefore simply skip TLB handling in store_helper_unaligned() if we are dealing with a single page. Fixes: 2bcf018340cb ("s390x/tcg: low-address protection support") Signed-off-by: Ilya Leoshkevich Message-Id: <20220711185640.3558813-2-iii@linux.ibm.com> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f90f4312ea..a46f3a654d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2248,7 +2248,7 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, const size_t tlb_off = offsetof(CPUTLBEntry, addr_write); uintptr_t index, index2; CPUTLBEntry *entry, *entry2; - target_ulong page2, tlb_addr, tlb_addr2; + target_ulong page1, page2, tlb_addr, tlb_addr2; MemOpIdx oi; size_t size2; int i; @@ -2256,15 +2256,17 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, /* * Ensure the second page is in the TLB. Note that the first page * is already guaranteed to be filled, and that the second page - * cannot evict the first. + * cannot evict the first. An exception to this rule is PAGE_WRITE_INV + * handling: the first page could have evicted itself. */ + page1 = addr & TARGET_PAGE_MASK; page2 = (addr + size) & TARGET_PAGE_MASK; size2 = (addr + size) & ~TARGET_PAGE_MASK; index2 = tlb_index(env, mmu_idx, page2); entry2 = tlb_entry(env, mmu_idx, page2); tlb_addr2 = tlb_addr_write(entry2); - if (!tlb_hit_page(tlb_addr2, page2)) { + if (page1 != page2 && !tlb_hit_page(tlb_addr2, page2)) { if (!victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) { tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, mmu_idx, retaddr);