From patchwork Wed Jul 13 06:23:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: quic_ddhamara@quicinc.com X-Patchwork-Id: 590107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B59EAC43334 for ; Wed, 13 Jul 2022 06:24:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230218AbiGMGYa (ORCPT ); Wed, 13 Jul 2022 02:24:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbiGMGY3 (ORCPT ); Wed, 13 Jul 2022 02:24:29 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8EE7CB46E for ; Tue, 12 Jul 2022 23:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657693468; x=1689229468; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GpgJm2w11HDT9HLV7pwaUKNml2YdL/gwGxII+D3gRSU=; b=mgFr1EjUcPfwnxAqCnviz/8jB4TZfJpO1vnCgAXJ0lSyXZTeyCWW2o2/ UBDFsogshDoVQjpTr+n0hBekYMixDQ8F0Z4ZKp++tR6N/xu5n4Nf26U38 gfr6coH8L6tBz0XKGf2QDR/BsUSyJkuyEJUgXpWefGP/qE41KnObnM6J5 s=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Jul 2022 23:24:28 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2022 23:24:28 -0700 Received: from hu-ddhamara-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Jul 2022 23:24:26 -0700 From: To: CC: , , , , ddhamara Subject: [PATCH 1/1] drm/msm/a6xx: Fix null pointer access in a6xx_get_indexed_registers Date: Wed, 13 Jul 2022 11:53:55 +0530 Message-ID: <20220713062355.6846-2-quic_ddhamara@quicinc.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220713062355.6846-1-quic_ddhamara@quicinc.com> References: <20220713062355.6846-1-quic_ddhamara@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Akhil P Oommen Fix a null pointer access when memory allocation fails in a6xx_get_indexed_registers(). Signed-off-by: Akhil P Oommen Signed-off-by: ddhamara --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 55f443328d8e..507074f6222c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -952,6 +952,12 @@ static void a6xx_get_indexed_registers(struct msm_gpu *gpu, a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed, &a6xx_state->indexed_regs[i]); + if (!a6xx_state->indexed_regs[i].data) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size); + a6xx_state->nr_indexed_regs = count - 1; + return; + } + /* * Offset 0x2000 in the mempool is the size - copy the saved size over * so the data is consistent