From patchwork Thu Jul 14 13:22:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 590381 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp1574719max; Thu, 14 Jul 2022 06:25:41 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sXI14s+algCgCcpmvfu14oCSe3fwTAmxpfiMZ/yp84hC1YAyjBgmnUxzYnGm8ypRb4qfIe X-Received: by 2002:a05:622a:1c3:b0:317:93d8:c041 with SMTP id t3-20020a05622a01c300b0031793d8c041mr8075680qtw.101.1657805141237; Thu, 14 Jul 2022 06:25:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657805141; cv=none; d=google.com; s=arc-20160816; b=h0eFTJnNUHX1zGW5agnR5AqA7KH5r2YjT7ZpE6+yRnujCEripiOGh6ZQ1etTEunjtF nE4Deko4vu/UfBXFoCrkdOrosKbrZhPqBdCJWFw8xuiYQJ3reW9hUKflPeG2kqIDRquk KO7bPnvyFDfaXcPo9so/FE02GSuJmYRSbTEYCkDDLwLNfzv23gqU/T5EOqDQOAihuvjs /G8bWW3CN5Fup0JMjEv6mKtCsTwQ+od5OuNZ4pD9vUB/a9CXMzbqTP+1/Q3Fh6BLJZRc PiHMAWMKRHPlxDP9qb5MrtTKd7vTgEaZ1OVHvah7b6r0/Z3GZVdXS/Ye3bMl35h6tKpt cHow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gSC4PvbkoAcYZyiRlv4heZM9qLY+Ka++bw/hOuy6a5U=; b=mbChBu3lREmJPaE1moNHkYjPDsxolTwTaQG6MEMPYDDlgu5Lmjbs5wh1533xELIy0f 8MHJ/mjt5IdP7a4V/p3Zzd8/e71OqcBH2m5yfXySB9yrob53A7qGJ9E4SG4FWi0nWzX2 lyNAI1MUUpMstXrlQYWXqNQHAQi92WAZw9fuQs9+3nKJgteQlSOkazI8OVQztBj4kHRW /fjulYxpzdg2ZnEnuMjEovYIGrTk1ryyGTtg+xSBfECRHp92P4hqFB7ZXf55qtQaJlzc AqUBr+PLSWXB7Ans6ZNc+g+FBYWd6kXa3psXY9vUWuJ6oki/Wqn/MFbri88YqViNgiId X+Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XEt+GqKS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bw18-20020a05622a099200b0031ed3da91d1si557393qtb.443.2022.07.14.06.25.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Jul 2022 06:25:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XEt+GqKS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oByqa-0002HP-Qg for patch@linaro.org; Thu, 14 Jul 2022 09:25:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oByoA-0002Bx-Vi for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:11 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:43599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oByo8-0004o5-2I for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:10 -0400 Received: by mail-wr1-x429.google.com with SMTP id d16so2533436wrv.10 for ; Thu, 14 Jul 2022 06:23:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gSC4PvbkoAcYZyiRlv4heZM9qLY+Ka++bw/hOuy6a5U=; b=XEt+GqKSrAVSLav/UkeFpZhjP6bfLISWGoj9HtNNKS3Msmi4zYcFXvy6R4Q6/2o2ta tRR29w77JWHTOHlSOxwS3ALmo8MEbJ7kVHMMUUpRQhX+gAy9p+8r8mQSfNPHUs/qKHV6 q8k9EJ1RVflq8suv0heHHGbkNrtLKIkV/LL9O/pVlmtAzpGVa0e/+ENMl6AZEvhMG7Cv DXj64zvRync7a5/3VRrNg3NYUI4t5QroMvdG7iMNi48ZNVc0AQTCLEZDhX+U1RPUurms NR2u76cP/wGx51Jm6HOGBmNQOV3HFq9IgIGYquudSAhj6HTOxFcaJMWoHvvuzUZ4uJie RuCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gSC4PvbkoAcYZyiRlv4heZM9qLY+Ka++bw/hOuy6a5U=; b=UBsGhC+vTOM7EcLIzFqRk0Ie6bQLC898DXaPmrfcYKAlt+S/WAjCZ72G5uRvAXQOVN RkUE2hxuKgDINUnFO/uRlgVGdO7nUs1plg5+NjF4vkVApmQRyJLPMbM/C5RAfn9IqiaB oFxA3ZE6asI5oDzVanBsvekE1eWqd53+VbcCUS3ADKFTjIrV0857DxEcv1xGqAhlYofV UnUIO9RP/FKlr7vGP+8p9yCwJG2sjEzgw7VgSy5cLIU+QpIUe9gpl7i74zasTJckY/lZ 4WOx+Sp2WU2WE9oISb6jfxydZIlCZT7RbqqZUbq75fZv34QexhUZL2ZAD/TBoQ8r6yip QY0A== X-Gm-Message-State: AJIora9088vXX4qt+MMT06AElFeNCDCufxN8ZY4CpkX1jFgBeFMWdp5o XaO2PjEa6rjW/A9oG2PMtK0FYg== X-Received: by 2002:a05:6000:887:b0:21d:4fca:44fc with SMTP id ca7-20020a056000088700b0021d4fca44fcmr8413446wrb.495.1657804986815; Thu, 14 Jul 2022 06:23:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 1/7] target/arm: Define and use new regime_tcr_value() function Date: Thu, 14 Jul 2022 14:22:57 +0100 Message-Id: <20220714132303.1287193-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714132303.1287193-1-peter.maydell@linaro.org> References: <20220714132303.1287193-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The regime_tcr() function returns a pointer to a struct TCR corresponding to the TCR controlling a translation regime. The struct TCR has the raw value of the register, plus two fields mask and base_mask which are used as a small optimization in the case of 32-bit short-descriptor lookups. Almost all callers of regime_tcr() only want the raw register value. Define and use a new regime_tcr_value() function which returns only the raw 64-bit register value. This is a preliminary to removing the 32-bit short descriptor optimization -- it only saves a handful of bit operations, which is tiny compared to the overhead of doing a page table walk at all, and the TCR struct is awkward and makes fixing https://gitlab.com/qemu-project/qemu/-/issues/1103 unnecessarily difficult. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 6 ++++++ target/arm/helper.c | 6 +++--- target/arm/ptw.c | 8 ++++---- target/arm/tlb_helper.c | 2 +- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 00e2e710f6c..fa046124fa8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -793,6 +793,12 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } +/* Return the raw value of the TCR controlling this translation regime */ +static inline uint64_t regime_tcr_value(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + return regime_tcr(env, mmu_idx)->raw_tcr; +} + /** * arm_num_brps: Return number of implemented breakpoints. * Note that the ID register BRPS field is "number of bps - 1", diff --git a/target/arm/helper.c b/target/arm/helper.c index cfcad97ce07..b45c81c714c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4216,7 +4216,7 @@ static int vae1_tlbmask(CPUARMState *env) static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) { - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr = regime_tcr_value(env, mmu_idx); int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); int select = extract64(addr, 55, 1); @@ -10158,7 +10158,7 @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr = regime_tcr_value(env, mmu_idx); bool epd, hpd, using16k, using64k, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu = env_archcpu(env); @@ -10849,7 +10849,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, { CPUARMTBFlags flags = {}; ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr = regime_tcr_value(env, mmu_idx); uint64_t sctlr; int tbii, tbid; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e71fc1f4293..0d7e8ffa41b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -820,7 +820,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr = regime_tcr_value(env, mmu_idx); uint32_t el = regime_el(env, mmu_idx); int select, tsz; bool epd, hpd; @@ -994,7 +994,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, uint32_t attrs; int32_t stride; int addrsize, inputsize, outputsize; - TCR *tcr = regime_tcr(env, mmu_idx); + uint64_t tcr = regime_tcr_value(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); uint64_t descaddrmask; @@ -1112,8 +1112,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * For stage 2 translations the starting level is specified by the * VTCR_EL2.SL0 field (whose interpretation depends on the page size) */ - uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); - uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); + uint32_t sl0 = extract32(tcr, 6, 2); + uint32_t sl2 = extract64(tcr, 33, 1); uint32_t startlevel; bool ok; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7d8a86b3c45..a2f87a5042d 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -20,7 +20,7 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) return true; } if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { + && (regime_tcr_value(env, mmu_idx) & TTBCR_EAE)) { return true; } return false; From patchwork Thu Jul 14 13:22:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 590380 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp1574631max; Thu, 14 Jul 2022 06:25:36 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uYF0b/Jmi2v3WDtQNFAUAyWykNGJkTjhysO4aXaua6AlBFuer4ubhi6q0o9F5zroWwIkEM X-Received: by 2002:a05:622a:50c:b0:31e:c29d:16fd with SMTP id l12-20020a05622a050c00b0031ec29d16fdmr7890051qtx.427.1657805136602; Thu, 14 Jul 2022 06:25:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657805136; cv=none; d=google.com; s=arc-20160816; b=WrgQzdj1zvu6GMeHI+I/EfKgZkRRon4fpyKbkjn/AvOSFdMpKUsNy/o9XYp8gL3aK9 Yddidatl9CoQUkw0L5f6EPs6Z4h8svNfRyZbzmMqjJLi4LA/5VJwhk1kasR6nt5uL6T7 mxftSrI7iUjm8zXmu5/uhSqw+K43vrI9cX26t+QvtvqfVn2EziSI7aMX/K+hiWkvzSQ3 5FnoI8cZ3i+ozfpt/nsTcVJvh51BzMZ6DW4fOU76ZjKSXCgziJieaLZmdWBhqooJrb/e Ob0JCQAvmaR9/4vhLEiUKsUvIq3+wUW9BhZQUWkrlQXWdpN/I6oTxtZt4KwNM6Un7g2C CmVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7fzrSUgKfikFHeNFkh9/TCh+g92276JL8XDKKltgm70=; b=MpXdbGwDor4KmdvN+rVvAYW+cFig+JTMz3ykQ0mZs6YJrTrRFK8vKlg8YHKT2Dlwgf +O+BXxN/FHASU+S8oNsP75JrR3uFzuVBkUN7phnsktvOe/jWRQP8nA7taySOJzKeN3zB rLzXhToPaGYtbmhaEr799wAyAI56VOMOOTbWbRsTSHlh/J5snBPqOgBrvUlJFyg+PfrB 8skJ+l3s2UXVEvX3Qyr9oeiS8uKdOPOhsLQSS8FFZQfVmjUa3io5kZMPbIENNbf6dQXD 4JMiar4wuTntESKIAcgbFPOUMZbhyj8tDPM97lrpncTxqmqR7g09YvhkK6qG6VkAsNdv gg3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fkbNBOPc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c11-20020a05622a058b00b0031eb8a3d373si1232026qtb.182.2022.07.14.06.25.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Jul 2022 06:25:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fkbNBOPc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oByqW-0002F2-4y for patch@linaro.org; Thu, 14 Jul 2022 09:25:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oByoA-0002BZ-OE for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:10 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:34639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oByo9-0004oK-5b for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:10 -0400 Received: by mail-wr1-x435.google.com with SMTP id r14so2575997wrg.1 for ; Thu, 14 Jul 2022 06:23:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7fzrSUgKfikFHeNFkh9/TCh+g92276JL8XDKKltgm70=; b=fkbNBOPc7mP/VK9xdZU8F3BO+d1w6JTnZoYVjmgahER7FgebSBBX/wMsiJ0VyK5g/u aJ4F8HdZ7jFPW73PMRb0TvzCC+pWSDlFf1C10itfaFs3xtvLP86W6Wtzhr9NbBo4cvLt vpGAf/NFYyopFed7HEdFG/kxQq++MbtHN3GjvCNYEmzfy7An7ApyRySuy5sFZxtaZER5 Cn9eDOjPU/ilgI6gfvFWC6BVnxOa3k8dru77KNHjui8KW/O7ZUL5EBbLEbUcQaJHk8wp 5GwDz6+AbDxdV9j5xlDc3HE47aS2m1XHns/Crwvr3EEDFBrJ918X84Cxci63fjed9L7A g9Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7fzrSUgKfikFHeNFkh9/TCh+g92276JL8XDKKltgm70=; b=1gzWz876dlxGM7tVq4GzJ+QEn2jvsOGgmKFDSy16+X3u53PH5UKNk85WggW3T5NYXv DpCt4X+7BmjQrsAwK2cIKUK2iWTolyyLZdambbu7Z0+tyCKaj0STyV4cT21aOkwMs2Ml ZIeCJVWUnaZ133AOAt+Sx4R86owtQKOjDD05E1czETdFausuXupb4ktjGeX/yTD+aGJn aj8/2yHVXV34SreametQeuh8KwJpmFIkLIo/N7J/U3wLRUnspIARu7dxiWG/ebntvHLw 334molgwl7m3hF5N2MskXrEa5bGF16dDpA5DiZwdxjhiO4afyrtFbSKFNhOVEE6yytoa kfMA== X-Gm-Message-State: AJIora8svNBTLjdgExys8xx+Zx+MZdfBtpULKdBbScCfuooKdmnRw8tj v62Y7pfrGc2q9xVgfvsH/75oAkRcC1mFDg== X-Received: by 2002:a05:6000:885:b0:21b:a423:172c with SMTP id ca5-20020a056000088500b0021ba423172cmr8323973wrb.98.1657804987582; Thu, 14 Jul 2022 06:23:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 2/7] target/arm: Calculate mask/base_mask in get_level1_table_address() Date: Thu, 14 Jul 2022 14:22:58 +0100 Message-Id: <20220714132303.1287193-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714132303.1287193-1-peter.maydell@linaro.org> References: <20220714132303.1287193-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In get_level1_table_address(), instead of using precalculated values of mask and base_mask from the TCR struct, calculate them directly (in the same way we currently do in vmsa_ttbcr_raw_write() to populate the TCR struct fields). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0d7e8ffa41b..16226d14233 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -315,20 +315,24 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - TCR *tcr = regime_tcr(env, mmu_idx); + uint64_t tcr = regime_tcr_value(env, mmu_idx); + int maskshift = extract32(tcr, 0, 3); + uint32_t mask = ~(((uint32_t)0xffffffffu) >> maskshift); + uint32_t base_mask; - if (address & tcr->mask) { - if (tcr->raw_tcr & TTBCR_PD1) { + if (address & mask) { + if (tcr & TTBCR_PD1) { /* Translation table walk disabled for TTBR1 */ return false; } *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; } else { - if (tcr->raw_tcr & TTBCR_PD0) { + if (tcr & TTBCR_PD0) { /* Translation table walk disabled for TTBR0 */ return false; } - *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; + base_mask = ~((uint32_t)0x3fffu >> maskshift); + *table = regime_ttbr(env, mmu_idx, 0) & base_mask; } *table |= (address >> 18) & 0x3ffc; return true; From patchwork Thu Jul 14 13:22:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 590383 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp1581349max; Thu, 14 Jul 2022 06:32:57 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sZi2r3F6acfQ1SmFquGG3fOpmH0W84/maGBvmnyzN4XLkBLy73+TAb84doQGtH0FdZhRtd X-Received: by 2002:a0c:df0c:0:b0:472:fbf6:7ab4 with SMTP id g12-20020a0cdf0c000000b00472fbf67ab4mr7503856qvl.30.1657805577419; Thu, 14 Jul 2022 06:32:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657805577; cv=none; d=google.com; s=arc-20160816; b=kyKe/xs5o3dNdEtc+doR0VjPBo3lcCL4yLfBr2W7tVlNnX68cawDwius0tgCd7f5hv ZKZOdx6IoNFgUXB9vs2pgSeilUcoc9VXvYPvI/xK04p6DAX2aJz7TFQ3WpyXvGd1WmdW gl47u8YjjbeNMSkLLTkCXslv9TNtHVOBvvT0sCwTvqcxusgs4wf6VlwAgbrF6teut8zc dr9GmoeaBf9wyG4jg3iUogUzgLgZUEUvuNdnVr49URZV7NfckvXYTBILgJjm8EmRBcid jqJsfGdVc0/SmPRsSghzfCNv1b8o+Y13Pq+91rdXJyvtUvDtskrrm5mUD6LX76mBvUpR 5GPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8lzArpcOjZMSjl2m0I/x5eGooz1zUQPNck3NBcXjI1Q=; b=CBMUVssNpsJLowwzPkmpvt9uPJDF4eWDz2BVBfPqW+ra0isOlXCRBW2flWjNPrMn1v UBx3CajzQW0/x36tdmdfYem5qjDQlVP7qvkgFG2GUsFISWZrar5zZCwiqkj/cXzNw1PX GVuQvv1dlwLbIx59dNlkv+bjYYjxchpNHud9PzLp15LXRhy/tQooHuVYhsZmyUiTbnlX WNebLOa38tB7xb/VaSVPjFW4cVIrAJgclQhzbcXGk7If0mgoOQRvVraO1Q0OTREVgCq/ lmei/AeB/pt8YdX0whFbx3XuHrS69cMQg4ltp78Mfl++8Wauqxc6zTviDUWXpgLOKlFM 10vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BrjAqag8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bl7-20020a05622a244700b0031ece085783si1040255qtb.20.2022.07.14.06.32.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Jul 2022 06:32:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BrjAqag8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oByxc-0000l6-Ub for patch@linaro.org; Thu, 14 Jul 2022 09:32:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oByoC-0002F8-6L for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:12 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:52028) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oByo9-0004oW-Qt for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:11 -0400 Received: by mail-wm1-x335.google.com with SMTP id ay25so1042546wmb.1 for ; Thu, 14 Jul 2022 06:23:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8lzArpcOjZMSjl2m0I/x5eGooz1zUQPNck3NBcXjI1Q=; b=BrjAqag8TfFNwDzjmNFumQ1LZsQKKQxNXdNLUcOPxo3ikfcVsnyPrrvXI48DZoW9I7 F7dPUeBpLgJbz+qdd+yhFvkw6+mrQ9sNMFLJ6P21mKtAHF6/GxT5lbUkyivqDiTpeOBi TzJD9Us0kxNRkz7KST5IU67ljwV8Pkof1gNF/9fsKF+TIh2rjm9YT9woULMvC4giMhXm P+k8v9jI6jLozWyF4+y2/vbDUqinGYBXfuIheRn6BybhQp3QtqKEIOSsHrfI4TIEDStp uAbdvnIDCkGDw2UKEBThIsFVyIt0Ly1zFnHgEqnoGKBWLYEn3vi6p7g7JWiIcvbI/00K Hzpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8lzArpcOjZMSjl2m0I/x5eGooz1zUQPNck3NBcXjI1Q=; b=qwOE6AkSBFrmdK901Hi/PZ1XZursXEhe6S28GucwcCgC4EiWSocLJ218soX4rv2cQi 2pMpA4/9ey8jnHu6OPbjk0P65pOut7ifLN0kgDXWZAG7YI8u4h+vggw1jrlyDEpeCaw9 i/cyVjLE5nhQVWmd9Cm8B/mrP6A4KpP0YU7QhDMhYHyKbgit5NSf+eboSlDr0dInA+XM d+156Jhx4/dyjWP3xxs255zrxTkuaWz7BS1/dCr7q8nrLRdmN1eACYvPOWqPDMQ92odt +B05Mu4TeJMgbUnJ7Tdb+pEoCVO2NrEBjnQ5FlmZarc0xDjoVOaRjSzJRuKVAsnes/zh PXrQ== X-Gm-Message-State: AJIora+sQoR3W82Pw1j7ziQnLmAwFWTz0G5uQsqtH9c5MveBA6FVWBWa t1oyrgqvPmF7iMXP4dmyHofbpg== X-Received: by 2002:a1c:4487:0:b0:3a2:fb76:7981 with SMTP id r129-20020a1c4487000000b003a2fb767981mr8703283wma.98.1657804988565; Thu, 14 Jul 2022 06:23:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 3/7] target/arm: Fold regime_tcr() and regime_tcr_value() together Date: Thu, 14 Jul 2022 14:22:59 +0100 Message-Id: <20220714132303.1287193-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714132303.1287193-1-peter.maydell@linaro.org> References: <20220714132303.1287193-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The only caller of regime_tcr() is now regime_tcr_value(); fold the two together, and use the shorter and more natural 'regime_tcr' name for the new function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 16 +++++----------- target/arm/helper.c | 6 +++--- target/arm/ptw.c | 6 +++--- target/arm/tlb_helper.c | 2 +- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fa046124fa8..0a1eb20afce 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -777,26 +777,20 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; } -/* Return the TCR controlling this translation regime */ -static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) +/* Return the value of the TCR controlling this translation regime */ +static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { if (mmu_idx == ARMMMUIdx_Stage2) { - return &env->cp15.vtcr_el2; + return env->cp15.vtcr_el2.raw_tcr; } if (mmu_idx == ARMMMUIdx_Stage2_S) { /* * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but * those are not currently used by QEMU, so just return VSTCR_EL2. */ - return &env->cp15.vstcr_el2; + return env->cp15.vstcr_el2.raw_tcr; } - return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; -} - -/* Return the raw value of the TCR controlling this translation regime */ -static inline uint64_t regime_tcr_value(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return regime_tcr(env, mmu_idx)->raw_tcr; + return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; } /** diff --git a/target/arm/helper.c b/target/arm/helper.c index b45c81c714c..3d4317c4c85 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4216,7 +4216,7 @@ static int vae1_tlbmask(CPUARMState *env) static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) { - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); int select = extract64(addr, 55, 1); @@ -10158,7 +10158,7 @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); bool epd, hpd, using16k, using64k, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu = env_archcpu(env); @@ -10849,7 +10849,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, { CPUARMTBFlags flags = {}; ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); uint64_t sctlr; int tbii, tbid; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 16226d14233..e9959848d88 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -315,7 +315,7 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); int maskshift = extract32(tcr, 0, 3); uint32_t mask = ~(((uint32_t)0xffffffffu) >> maskshift); uint32_t base_mask; @@ -824,7 +824,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); uint32_t el = regime_el(env, mmu_idx); int select, tsz; bool epd, hpd; @@ -998,7 +998,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, uint32_t attrs; int32_t stride; int addrsize, inputsize, outputsize; - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); uint64_t descaddrmask; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index a2f87a5042d..5a709eab56f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -20,7 +20,7 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) return true; } if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr_value(env, mmu_idx) & TTBCR_EAE)) { + && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { return true; } return false; From patchwork Thu Jul 14 13:23:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 590382 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp1576292max; Thu, 14 Jul 2022 06:27:36 -0700 (PDT) X-Google-Smtp-Source: AGRyM1t0j0YX17CE/S9ekhGWeKrJUTdgvzlUoOmiT1lmspT0F4JYKuXjpTSUUJSE50uWoVF1Hj4h X-Received: by 2002:a05:620a:458a:b0:6b5:9c24:b24d with SMTP id bp10-20020a05620a458a00b006b59c24b24dmr5634772qkb.369.1657805256612; Thu, 14 Jul 2022 06:27:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657805256; cv=none; d=google.com; s=arc-20160816; b=nHgKRaXuupCLnPLMyrgDKmP2u9OPCI9AS4F7WCM725b9e62VZNof6u8qN+XrtVa9yv TfVBl1gKHyrwCeJQAy9Z+QT+xA1g32FHxtklSRzJU4I9+roaMjwIK4pqF/ZunZvBKeNg BU1YpdHe5R45wBcSJ+idL9XQWYM4L0CVIehhNFLsKFV+r4xI2IAwB7RnOuqkPpd/hdFj lyonsD+3zedSKufuUMLszmb2TYid13Z/VsP7c0e4uw6ePnC5yG6JD67lNZBl+nZwrQMm VmrenfvYPsazR02KJ001KXaSVyqkGMU7CMof9XhE/o626wnYZgN5DM9EsSbdbQzYbNQl WbEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bMOS0wQ3/jAb1bU1b2bDXRVo7/duCbF4KRhimcopz70=; b=Tw67XokyroydgUjuFPR6tb1bFLbOHUZ/u8BKLaQl0MhBfmVrpIjBtIcKHis+79VKAn CxXIAhNYdu97kSBih4H7fh11yLTocmZ6M0ZrB0oo46l3PeVCL6/YIgLOHQ4l+ybVjcoK FlQHJlU2gHQPy/L3VSnqr3Asyp0aVOVux4SRBGgC6Jo1gKEhqIgfQoyckWuB/saSMRi7 SgdZ1GnY3TrrA0+tkPdYhvzjLovCgNsc8jid7OujowBbycf8KOrvsyR4oNUCVOuHyKpH uiYrZ7PY+f+LymUqr9UnpzjAMKDgUYSW9oMus3N8drQ2QJnx+4VZabqj4CFf7jhz5J5q NF7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E1Ogb8AT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jt1-20020a05621427e100b00473a3e622fbsi778979qvb.192.2022.07.14.06.27.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Jul 2022 06:27:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E1Ogb8AT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBysR-0002xa-2m for patch@linaro.org; Thu, 14 Jul 2022 09:27:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oByoC-0002FT-9I for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:12 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:43611) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oByoA-0004op-Kc for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:11 -0400 Received: by mail-wr1-x435.google.com with SMTP id d16so2533608wrv.10 for ; Thu, 14 Jul 2022 06:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bMOS0wQ3/jAb1bU1b2bDXRVo7/duCbF4KRhimcopz70=; b=E1Ogb8ATOmPtoZcZwHIWyu8jm4DPdWr54lFLGgTjP803agCv+IcXOPBNhVxfx/FDcv v4PJfuZQHfTO5s2JdcgTv2SEUmCjepkYyTzMLTgdL2qM49tQ11sgB9X3Z5Fu54Akhs6z 4qFmWrlwa8kp7hoTJE7XKF7MGHYpw4P/frJEv4kDvjC/7yeY5kxfqClRLx0VSPP76JVn 486VDT5WES7g4z+rXCfI7q5n2IZFp1yQhD/pRAYWfIaX/m3kFK0Hy6+GhNPb9crq1zBB FMsBYv+Jf9fS9f+PhzFuV1h7dVIuJVh67lhJ2TG+2DzZ247jt34i1E8VluUrtYnEbaXX Orjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bMOS0wQ3/jAb1bU1b2bDXRVo7/duCbF4KRhimcopz70=; b=Ps6E2W1lg1+80BLjbavDjT2WkbSRGvhaJQx2VDuqvCWprk90oL0cikyHeYHTOPz+Ps UPk7wf+B2HGFK7vrorS5QCCFGKcemHqJu9FPYizdNsSArnizYbhWxB+JySUs7B3snLVI tNlbqmfuh2IsMC8hacg8SZpLh4eIZio9XLC/B/93sZibBdcCsDo9cg4alWzKL8+EVG9b 8EZl9InjCsbew6QOKpR4D/g/M57LYKx0DAF7PxMZukbmJWE7ujQ5oOLFX4bPw2br5cmi dRL0tGpy9UqZ0sIl7taPsEeMU3DoAFLXbhAAy29CPwLkmlUW/fbiAvLcQLLx/e7BZKO+ xSwA== X-Gm-Message-State: AJIora9x3OJ37ET0awaQWYtGbkEiu5q/ckPqaNO+Ca1EP2u5kk6CbPhF fgtApa3bBn7Bs0XRV1q/y6h5MA== X-Received: by 2002:a05:6000:1cc:b0:21d:a352:116b with SMTP id t12-20020a05600001cc00b0021da352116bmr7944120wrx.418.1657804989372; Thu, 14 Jul 2022 06:23:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 4/7] target/arm: Fix big-endian host handling of VTCR Date: Thu, 14 Jul 2022 14:23:00 +0100 Message-Id: <20220714132303.1287193-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714132303.1287193-1-peter.maydell@linaro.org> References: <20220714132303.1287193-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have a bug in our handling of accesses to the AArch32 VTCR register on big-endian hosts: we were not adjusting the part of the uint64_t field within TCR that the generated code would access. That can be done with offsetoflow32(), by using an ARM_CP_STATE_BOTH cpreg struct, or by defining a full set of read/write/reset functions -- the various other TCR cpreg structs used one or another of those strategies, but for VTCR we did not, so on a big-endian host VTCR accesses would touch the wrong half of the register. Use offsetoflow32() in the VTCR register struct. This works even though the field in the CPU struct is currently a struct TCR, because the first field in that struct is the uint64_t raw_tcr. None of the other TCR registers have this bug -- either they are AArch64 only, or else they define resetfn, writefn, etc, and expect to be passed the full struct pointer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Actually I'm not 100% sure that TTBCR is handled correctly for big-endian hosts. But it's going to go away shortly anyway. --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3d4317c4c85..7eee2007a0e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5409,7 +5409,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .type = ARM_CP_ALIAS, .access = PL2_RW, .accessfn = access_el3_aa32ns, - .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, + .fieldoffset = offsetoflow32(CPUARMState, cp15.vtcr_el2) }, { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .access = PL2_RW, From patchwork Thu Jul 14 13:23:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 590385 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp1581723max; Thu, 14 Jul 2022 06:33:20 -0700 (PDT) X-Google-Smtp-Source: AGRyM1txu/j/FQq6FU+hmEGWz7RpjTu91dgXy6zt1KOYsdZbQcxPtWsdTjPxXqdshaPccUZ0+Eis X-Received: by 2002:a05:622a:1208:b0:31e:7b14:9bf4 with SMTP id y8-20020a05622a120800b0031e7b149bf4mr8147493qtx.393.1657805600209; Thu, 14 Jul 2022 06:33:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657805600; cv=none; d=google.com; s=arc-20160816; b=OElB2OLA4Pd7nZ7d1m5kHoTFZwR7GNeIFf3ZkHxXFN3DAL4bHvbk+p34SnDk3RvIIn Fve/L/6otLduu0zWIzI5U6Yesd7cWdUL3seyL7CXWOMfrNl9yfvIGwNgor2zjYcV2RHb cEvmSfJ/Adt3PXnlaa5M4S3cf+wnsVqZSgnXffRDfQCUp16bX+sQjccQAwYYKQVe2kpj A0/BktkEm9q7j+P0AMyHXi3Jki7b6r9wHzncFqTCnsr+SUoLfhPiRzrtTN8FCeGBqPNY Ql0bUEYAK45Q5HKsf+QI7vIaOBIvBfZLwwe8JVGrEi2nNe9iRPS18DT2Tn7tDcybxetk 7xaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wAKemPdqPQXfGwjlKzJeGaRkjIPujLLaF6bX3+dsuqo=; b=jeZKmCzkAHWBG4AGYzUp7XT8qJgGXj5S6ghJ2xNxkYlHNVvskZ03coOQ1N0yKojsNn vy+3b0KqtGEKIWGdcSZYnI2WcldSj/pdVO1d+OZIZmzvqYoIdFpzbJvh5/qw0h60eEXQ 84NgmPaPuDoIAd0RaQEDxaBbEyjf/VvqmAdKDP0DgP8H6j2EkScNa4sH82n3woOWiiOR tcDVr+m7SFbsqU5c+Z1MQ2McbqISqZ+gbQXeekJV1HUUE/S+PHQ2PSchB7qHrw30KBAt 2jxvNAK4fM+N7oPnxC5IzybbaJn6IyIA4B5m3L1BMEhVs4K2AosyKXMlH+Shtq3MKAPy RE0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TuBgYljp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l7-20020a37f907000000b006b48ac65a3esi985918qkj.495.2022.07.14.06.33.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Jul 2022 06:33:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TuBgYljp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oByxz-0002Ch-Mh for patch@linaro.org; Thu, 14 Jul 2022 09:33:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45902) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oByoE-0002Ke-Kf for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:14 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:36842) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oByoB-0004qI-Nd for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:13 -0400 Received: by mail-wr1-x42f.google.com with SMTP id r2so1524010wrs.3 for ; Thu, 14 Jul 2022 06:23:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wAKemPdqPQXfGwjlKzJeGaRkjIPujLLaF6bX3+dsuqo=; b=TuBgYljp1BPSf4BCcqHCV2gAyEQl7q33Qw35pbW1IGo8DQzpT0m2a05xiJRK+y8d5g AvWN1ILLlaBsYl48JFALZZARJ5tzQby6OT2MyNUQ5TlnFNJaaHJtWeK71ritIDp6NTJe cYPsY0aCApLbeizzmGw2eQwjyu8bQCpx5Gv6cdWgqaHNzDzH566LXsHk00zpWMFeedjS UwZTOtRwipdPI6jKC28gV+9mQHznWNToPmVxdA2N043UQy4j8gE/U1K1lVJlrCYLxkMA aqHwyQ0c+0l24W78RlhZsfZNkrJVq/lSTTdTielCIsdgwBMJ5t+QLS91v2HkSV/Co/id td9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wAKemPdqPQXfGwjlKzJeGaRkjIPujLLaF6bX3+dsuqo=; b=jeCCwespdq7O5FBNA2doliUaLfoap9q+BJIR91bmGeRabliMwohAoVh7RUkeH/OVEs ygYUtbNbgTvbJfrX8GqXt39Z4ArA4Fu+2oLKHXswpkIbqMTZgM0+apVn+PLty8lOHfMi Pa60oNt0VtKDy243ertLJK1t+5nqj7dn4sFpgxwhc3khCTwYWkSI0jEi41xPG5Pzcxbh Gcgcgxr4COYphP4hFB6dSuDAHYKpZQZX903uy3nYJqMN7TF4YlxyoAha6T77M9oUNz7E wBeZiK5VnAjXtrNkeMw3pqMm7xXb+m1N5MKv3/B+weseb55PEVcQg8jAO3gEzMN+V6ro KlhA== X-Gm-Message-State: AJIora92wPj27Gc/TPy4Bm7qJKvZv1VywIX5/w1z17YyRJDjc6tF2jo3 dOHDjaqVHQjP9AVQ8zQU7Kh/H/u0nSx6uA== X-Received: by 2002:a05:6000:888:b0:21b:b950:f4bd with SMTP id ca8-20020a056000088800b0021bb950f4bdmr8369221wrb.253.1657804990350; Thu, 14 Jul 2022 06:23:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 5/7] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t Date: Thu, 14 Jul 2022 14:23:01 +0100 Message-Id: <20220714132303.1287193-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714132303.1287193-1-peter.maydell@linaro.org> References: <20220714132303.1287193-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change the representation of the VSTCR_EL2 and VTCR_EL2 registers in the CPU state struct from struct TCR to uint64_t. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 4 ++-- target/arm/helper.c | 4 +--- target/arm/ptw.c | 14 +++++++------- 4 files changed, 12 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e36a839ee4..445e477c710 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -340,8 +340,8 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ TCR tcr_el[4]; - TCR vtcr_el2; /* Virtualization Translation Control. */ - TCR vstcr_el2; /* Secure Virtualization Translation Control. */ + uint64_t vtcr_el2; /* Virtualization Translation Control. */ + uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register diff --git a/target/arm/internals.h b/target/arm/internals.h index 0a1eb20afce..9f654b12cea 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -781,14 +781,14 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { if (mmu_idx == ARMMMUIdx_Stage2) { - return env->cp15.vtcr_el2.raw_tcr; + return env->cp15.vtcr_el2; } if (mmu_idx == ARMMMUIdx_Stage2_S) { /* * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but * those are not currently used by QEMU, so just return VSTCR_EL2. */ - return env->cp15.vstcr_el2.raw_tcr; + return env->cp15.vstcr_el2; } return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 7eee2007a0e..eaf6521c615 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5413,9 +5413,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .access = PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + /* no .writefn needed as this can't cause an ASID change */ .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, { .name = "VTTBR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 6, .crm = 2, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e9959848d88..8049c67f039 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -241,9 +241,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, if (arm_is_secure_below_el3(env)) { /* Check if page table walk is to secure or non-secure PA space. */ if (*is_secure) { - *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + *is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + *is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); } } else { assert(!*is_secure); @@ -2341,9 +2341,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ipa_secure = attrs->secure; if (arm_is_secure_below_el3(env)) { if (ipa_secure) { - attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + attrs->secure = !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + attrs->secure = !(env->cp15.vtcr_el2 & VTCR_NSW); } } else { assert(!ipa_secure); @@ -2385,11 +2385,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, if (arm_is_secure_below_el3(env)) { if (ipa_secure) { attrs->secure = - !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); } else { attrs->secure = - !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) - || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); + !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) + || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); } } return 0; From patchwork Thu Jul 14 13:23:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 590384 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp1581518max; Thu, 14 Jul 2022 06:33:08 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tjOO6BjYTBGuvDD0uWrMHDWfgL7rtSk0+tFy0d1uY07jPMhKws79EISN+slfkmiNsDZ0v4 X-Received: by 2002:a0c:db0e:0:b0:473:5450:b8a4 with SMTP id d14-20020a0cdb0e000000b004735450b8a4mr7736781qvk.125.1657805587891; Thu, 14 Jul 2022 06:33:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657805587; cv=none; d=google.com; s=arc-20160816; b=GrCkDC4OmUlDb+jQGBgZYZrspLb64LdQAvxA/rkHsBnz1LKx2FoISu5iX6yDhFV4TQ n4fqOhD5q2yTIoTEu+4OBcA55jGGmrplhrWVAyb0Vc7HcdzQXLMBZ9aFbrGJdKMKb0mk mfLfOjRDgKXiuTEPyNzlI8n25zZeNgVMV1RS0+w9toQGhu9LT4gDEoqVVRE17hz4iRSl MonqvWTqoAjykKMtuMoqPdbw5GH+pkR92ESRKP81LJ0aGovGTCTqmN1u2QhbkwkuZINk OYPsZ8oaN9WXuTHCKH1+6SdajODX2yfuiD53DRXWRv0W8Do+5dcpdKxEqcAJHrFu9Cfd cnhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QSNYIq4mNazZyNNrOkyrVy+ZP+gbwqcNvnTFnG/hGfA=; b=SZwd6Yj1thd4pAe9S7PaXCYPXA4F2PRoTZOwrPRWxMlWeVYcxPmjM2c94tGzTst0pR qjNEmPHfhVWdMGD7w5KF2CVPfYHm68H3TN7r0ewmUMZKauYUrmDeKI1x1JYaCi5RliiV FqszNxc/cTV/xV9SOT7UYbxP054XzcHqqSXg/g5f7i0o1cziE4WiHn/zjJFOXo0UaX7E KljcFcrIYTfqn5yqRoM2h4PcNylbhETL6GMnvM1hHXN+hndKC6wSIYmirx0+wqWZF3Et 82Uq3oDAIBXEPDOU8XIZyAhJGa6+X/aNuvom5RNcIUtK7HMMiUQur6/FpzU1hx1ZA1Dk T1Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G+NrcPJ4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gg15-20020a056214252f00b0047312fac5a0si939889qvb.587.2022.07.14.06.33.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Jul 2022 06:33:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G+NrcPJ4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43518 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oByxn-0001OE-FZ for patch@linaro.org; Thu, 14 Jul 2022 09:33:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oByoF-0002Lw-Vf for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:16 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:40464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oByoC-0004qh-SP for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:14 -0400 Received: by mail-wr1-x42a.google.com with SMTP id z12so2549505wrq.7 for ; Thu, 14 Jul 2022 06:23:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QSNYIq4mNazZyNNrOkyrVy+ZP+gbwqcNvnTFnG/hGfA=; b=G+NrcPJ4dxnDQ+FSAvMSyc3vP7LoNkFOFeV5OcV9JRmHqFo3bZ7FDAl8RayUsaTEVg WYWqZDsJK6rPMGVA1D739PdOKbvLh+lvXWF8paFTx1lJDJ0LzqT0YJoW9Q56kOHCE98b MmBE+PkU3WFKNFjFPaO4QrUr0g127ktiWbaNJXzbgQYEF30DvX16pRcdp7+JJEk3z2tr SKRdvpNSUW13AXGc6yAW0e8/qeUeOQFssQps6ERBjQ6uWofQg2Koqn/L4LCorlzyDJM0 IHs7T8YueHZ4G8Bzs76Tp/VmFM3wkrXIBd9QO3W9xM1xjZTKiVqa4MxQ9AWogL/w3DO/ ulig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QSNYIq4mNazZyNNrOkyrVy+ZP+gbwqcNvnTFnG/hGfA=; b=Y20srluVRb1wtar7J6ytlarUaVKV7a3QGBU/yNsIprE0BOcs/KRdxjmkCv5at77vb9 6dpCLrN5yTAF9aw28TqZrcALW45VvFJ7K9HnMxKGyGQVNj7Foaw1VmyNJmOU4N0rg031 LeDSu66XTzxsU0iKBtovt6fyMHCChQXBFUmLCxZYwQcriyoNOKixuWwzrCu/HjrsOo1R BLMt+DQ6E9vRK/kc4Pe+PxCmOFSRk57oisjS6PhmbZdWDqnAKK5uF/fPy4+TiMY2EIqc DZn15pcmyWT1aiw+cLnoGbrfSrBSeo+ydx64c8rlyxvGAskQN8NVaylbrXOaRZ7+eqck yGfA== X-Gm-Message-State: AJIora+K20BXXn7FiQQs5ZUcqs+NNnK+IfpxnyECwROscBPkUX171m2N WxbCSjMlRKmDwuuhsOEWNyHoDw== X-Received: by 2002:a5d:4304:0:b0:21b:9b2c:be34 with SMTP id h4-20020a5d4304000000b0021b9b2cbe34mr8627753wrq.577.1657804991353; Thu, 14 Jul 2022 06:23:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 6/7] target/arm: Store TCR_EL* registers as uint64_t Date: Thu, 14 Jul 2022 14:23:02 +0100 Message-Id: <20220714132303.1287193-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714132303.1287193-1-peter.maydell@linaro.org> References: <20220714132303.1287193-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change the representation of the TCR_EL* registers in the CPU state struct from struct TCR to uint64_t. This allows us to drop the custom vmsa_ttbcr_raw_write() function, moving the "enforce RES0" checks to their more usual location in the writefn vmsa_ttbcr_write(). We also don't need the resetfn any more. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 8 +---- target/arm/internals.h | 6 ++-- target/arm/cpu.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/helper.c | 75 +++++++++++---------------------------- target/arm/ptw.c | 2 +- 6 files changed, 27 insertions(+), 68 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 445e477c710..bbd1afa6251 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -166,12 +166,6 @@ typedef struct ARMGenericTimer { #define GTIMER_HYPVIRT 4 #define NUM_GTIMERS 5 -typedef struct { - uint64_t raw_tcr; - uint32_t mask; - uint32_t base_mask; -} TCR; - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW @@ -339,7 +333,7 @@ typedef struct CPUArchState { uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ - TCR tcr_el[4]; + uint64_t tcr_el[4]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 9f654b12cea..742135ef146 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -252,9 +252,9 @@ unsigned int arm_pamax(ARMCPU *cpu); */ static inline bool extended_addresses_enabled(CPUARMState *env) { - TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; + uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; return arm_el_is_aa64(env, 1) || - (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); + (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE)); } /* Update a QEMU watchpoint based on the information the guest has set in the @@ -790,7 +790,7 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) */ return env->cp15.vstcr_el2; } - return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; + return env->cp15.tcr_el[regime_el(env, mmu_idx)]; } /** diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5de7e097e9b..1b7b3d76bb3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -226,7 +226,7 @@ static void arm_cpu_reset(DeviceState *dev) * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); + env->cp15.tcr_el[1] = 5 | (1ULL << 37); /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index d09fccb0a4f..c21739242c5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -439,7 +439,7 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env) using_lpae = true; } else { if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { using_lpae = true; } } diff --git a/target/arm/helper.c b/target/arm/helper.c index eaf6521c615..51e58e08468 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3606,19 +3606,21 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, }; -static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - TCR *tcr = raw_ptr(env, ri); - int maskshift = extract32(value, 0, 3); + ARMCPU *cpu = env_archcpu(env); if (!arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { - /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when - * using Long-desciptor translation table format */ + /* + * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when + * using Long-descriptor translation table format + */ value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); } else if (arm_feature(env, ARM_FEATURE_EL3)) { - /* In an implementation that includes the Security Extensions + /* + * In an implementation that includes the Security Extensions * TTBCR has additional fields PD0 [4] and PD1 [5] for * Short-descriptor translation table format. */ @@ -3628,55 +3630,23 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, } } - /* Update the masks corresponding to the TCR bank being written - * Note that we always calculate mask and base_mask, but - * they are only used for short-descriptor tables (ie if EAE is 0); - * for long-descriptor tables the TCR fields are used differently - * and the mask and base_mask values are meaningless. - */ - tcr->raw_tcr = value; - tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); - tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); -} - -static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu = env_archcpu(env); - TCR *tcr = raw_ptr(env, ri); - if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ tlb_flush(CPU(cpu)); } - /* Preserve the high half of TCR_EL1, set via TTBCR2. */ - value = deposit64(tcr->raw_tcr, 0, 32, value); - vmsa_ttbcr_raw_write(env, ri, value); -} - -static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - TCR *tcr = raw_ptr(env, ri); - - /* Reset both the TCR as well as the masks corresponding to the bank of - * the TCR being reset. - */ - tcr->raw_tcr = 0; - tcr->mask = 0; - tcr->base_mask = 0xffffc000u; + raw_write(env, ri, value); } static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); - TCR *tcr = raw_ptr(env, ri); /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ tlb_flush(CPU(cpu)); - tcr->raw_tcr = value; + raw_write(env, ri, value); } static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3780,15 +3750,15 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tvm_trvm, .writefn = vmsa_tcr_el12_write, - .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, + .raw_writefn = raw_write, + .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, - .raw_writefn = vmsa_ttbcr_raw_write, - /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ - .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), - offsetof(CPUARMState, cp15.tcr_el[1])} }, + .raw_writefn = raw_write, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), + offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, }; /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing @@ -3799,8 +3769,8 @@ static const ARMCPRegInfo ttbcr2_reginfo = { .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, .bank_fieldoffsets = { - offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), - offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), + offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]), }, }; @@ -5403,7 +5373,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .writefn = vmsa_tcr_el12_write, - /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */ .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name = "VTCR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, @@ -5643,12 +5612,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, .access = PL3_RW, - /* no .writefn needed as this can't cause an ASID change; - * we must provide a .raw_writefn and .resetfn because we handle - * reset and migration for the AArch32 TTBCR(S), which might be - * using mask and base_mask. - */ - .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, + /* no .writefn needed as this can't cause an ASID change */ + .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8049c67f039..3261039d93a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2466,7 +2466,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, int r_el = regime_el(env, mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax = arm_pamax(env_archcpu(env)); - uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; + uint64_t tcr = env->cp15.tcr_el[r_el]; int addrtop, tbi; tbi = aa64_va_parameter_tbi(tcr, mmu_idx); From patchwork Thu Jul 14 13:23:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 590386 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp1584237max; Thu, 14 Jul 2022 06:35:54 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uce0kYTS5AeA50vI1eN+HA0cZrOkyh/4T3HgBy73nYy2XGJ9KqkojiQxmCiYsjQpaUXcaa X-Received: by 2002:a05:6214:1c4a:b0:473:2e4a:8e30 with SMTP id if10-20020a0562141c4a00b004732e4a8e30mr7889338qvb.32.1657805754244; Thu, 14 Jul 2022 06:35:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657805754; cv=none; d=google.com; s=arc-20160816; b=RJzSGjE8p5TRx6FSTXk7PNo5kFcZXKHBstWSxElqnMn+ZjiZIjG0TsUZVHZVUrn9Ho XyuWDmW4owZnVtMrb9d7KuJ/RfyiD359KyQR/QeNku2HOu6PfK+ZXBG+8O3WmqwYeRfr RHj+2gtKaYb955etdXzf1rGv9uonHpqko9gn6FwDcNM1cFYtb4+aPbzCK6gWgCRuRR3/ uCdOSKRC0ylIZVqvMK7tWIOME/g0m2mQSkVdmh5Hlpus7wWA3feBd13sj/5f6TPFub8Q hHj1cYg/SShR0dplJxuJj7uDW5dZusrZO31v8Db2rVEEiL9DJp24oEk58iWttg0pAaTD 0DuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zah1h9cYjHaav0SyBc/T7cche/sTMGE+QsjhBy4+l4c=; b=CeaxMJs8WvC8eigl3Z8zcAMvWQ9OVNZJRERADdPz5F4J+7bfCjHFA0qTD0q6jDEibH hECU41nW1lrAvrtfyi4wNhntvcpxN/p+IE7SAv+Op/HTySlsWjNPY2l6+E7KFkqoe2Et H4yzv4aQWM88oHsvO58b3FsewaUNllEGzF3aojkK+rqlZkVwYQPs4J3yBoIQvH6Pg9aV w+r+aINH+tEEiMks7aaesupI75t5O8n1rJ6+/mlbB2vW2VZpu5zP4w0C7bKvPADa2BDp 4Ep2lMkWWG0EwZAU5qvMf/bKkK52gBd8US3P9996+xY0GW1pGKZBPAIEOWT4ykVuCH21 CnWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QT3Qjpb+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g21-20020ac842d5000000b00304ffcd39eesi1073754qtm.488.2022.07.14.06.35.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Jul 2022 06:35:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QT3Qjpb+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBz0T-0007B3-PO for patch@linaro.org; Thu, 14 Jul 2022 09:35:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oByoG-0002P4-Eu for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:16 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:33716) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oByoE-0004r7-KQ for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:16 -0400 Received: by mail-wr1-x432.google.com with SMTP id h17so2615480wrx.0 for ; Thu, 14 Jul 2022 06:23:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zah1h9cYjHaav0SyBc/T7cche/sTMGE+QsjhBy4+l4c=; b=QT3Qjpb+nlLUtIoH5rQOnEQAyHNy4wvxkMYAd0nRGkOvdL/dDtVqs6cf7xf+KAw1fI zbjp91j+jyI/YGN904df0zfgel7YSPcbud5SsZ1muj2fRrqmzRDD+2Re31KuOuM8E0Bk VO95wrw5vLOPZgoAYjDyOcKUfP7xmmTRK+4RyLmkvy81NEfFx1IW+qI8eR38T5y62pZq c15EtMMFIA259jTJs7jpV3ftq9eRDFA6Dk+FvGfV93HwUeSrfQcQrGn0QGHY5KT2ehVA cHyMcBFxoQ9J6B3+KxhWZiDdsfnIjWZbpf5881kxIPEnFCSkgE+VJOOSerSE85j7+lMw j6DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zah1h9cYjHaav0SyBc/T7cche/sTMGE+QsjhBy4+l4c=; b=PDwYMMVvHFR9byw4/bllNkGHBoXko7UZJp+KEHsc4oW0s9S8g+MLTEOHKK05trLAuk fDgM64EoWNkTpSRrUp4jABDUYPdwMTAenFJDeh0TJXPt/K/9Ld4xH/DutKToc0tfHyG3 H0a3avy3u48wvf0gM9XmRCdrQox0Uyy0BeII/RFGeorU5tYA2QxANRf7oimDbwK6vwUJ EndJZi3X0g+En36rq/o89Mra4XvjQ8ckZqmsOC+sLwkAyU3iYr0MbAWfwYVJvv+4V22r /E6VweLLjU36yppr2SpYFDYOKnXLUpHsQ4vM/SPxxEMzVz2fAag+iHb3A15Iry/YKrPI R6rQ== X-Gm-Message-State: AJIora9XsdMB+0V9Z/XADl7ZK9V87PgaKLpdtlmIQW4+KPWlhjhqzGJK cCpUQNBmda5ZEGb3AIVjVR+rKA== X-Received: by 2002:a5d:5989:0:b0:21d:b2bd:d712 with SMTP id n9-20020a5d5989000000b0021db2bdd712mr8557460wri.698.1657804992250; Thu, 14 Jul 2022 06:23:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 7/7] target/arm: Honour VTCR_EL2 bits in Secure EL2 Date: Thu, 14 Jul 2022 14:23:03 +0100 Message-Id: <20220714132303.1287193-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714132303.1287193-1-peter.maydell@linaro.org> References: <20220714132303.1287193-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In regime_tcr() we return the appropriate TCR register for the translation regime. For Secure EL2, we return the VSTCR_EL2 value, but in this translation regime some fields that control behaviour are in VTCR_EL2. When this code was originally written (as the comment notes), QEMU didn't care about any of those fields, but we have since added support for features such as LPA2 which do need the values from those fields. Synthesize a TCR value by merging in the relevant VTCR_EL2 fields to the VSTCR_EL2 value. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1103 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 19 +++++++++++++++++++ target/arm/internals.h | 22 +++++++++++++++++++--- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bbd1afa6251..57b5dd1f70b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1412,6 +1412,25 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define TTBCR_SH1 (1U << 28) #define TTBCR_EAE (1U << 31) +FIELD(VTCR, T0SZ, 0, 6) +FIELD(VTCR, SL0, 6, 2) +FIELD(VTCR, IRGN0, 8, 2) +FIELD(VTCR, ORGN0, 10, 2) +FIELD(VTCR, SH0, 12, 2) +FIELD(VTCR, TG0, 14, 2) +FIELD(VTCR, PS, 16, 3) +FIELD(VTCR, VS, 19, 1) +FIELD(VTCR, HA, 21, 1) +FIELD(VTCR, HD, 22, 1) +FIELD(VTCR, HWU59, 25, 1) +FIELD(VTCR, HWU60, 26, 1) +FIELD(VTCR, HWU61, 27, 1) +FIELD(VTCR, HWU62, 28, 1) +FIELD(VTCR, NSW, 29, 1) +FIELD(VTCR, NSA, 30, 1) +FIELD(VTCR, DS, 32, 1) +FIELD(VTCR, SL2, 33, 1) + /* Bit definitions for ARMv8 SPSR (PSTATE) format. * Only these are valid when in AArch64 mode; in * AArch32 mode SPSRs are basically CPSR-format. diff --git a/target/arm/internals.h b/target/arm/internals.h index 742135ef146..b8fefdff675 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -777,6 +777,16 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; } +/* + * These are the fields in VTCR_EL2 which affect both the Secure stage 2 + * and the Non-Secure stage 2 translation regimes (and hence which are + * not present in VSTCR_EL2). + */ +#define VTCR_SHARED_FIELD_MASK \ + (R_VTCR_IRGN0_MASK | R_VTCR_ORGN0_MASK | R_VTCR_SH0_MASK | \ + R_VTCR_PS_MASK | R_VTCR_VS_MASK | R_VTCR_HA_MASK | R_VTCR_HD_MASK | \ + R_VTCR_DS_MASK) + /* Return the value of the TCR controlling this translation regime */ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -785,10 +795,16 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) } if (mmu_idx == ARMMMUIdx_Stage2_S) { /* - * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but - * those are not currently used by QEMU, so just return VSTCR_EL2. + * Secure stage 2 shares fields from VTCR_EL2. We merge those + * in with the VSTCR_EL2 value to synthesize a single VTCR_EL2 format + * value so the callers don't need to special case this. + * + * If a future architecture change defines bits in VSTCR_EL2 that + * overlap with these VTCR_EL2 fields we may need to revisit this. */ - return env->cp15.vstcr_el2; + uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK; + v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; + return v; } return env->cp15.tcr_el[regime_el(env, mmu_idx)]; }