From patchwork Thu Jul 14 16:55:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 593238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 106E7C43334 for ; Thu, 14 Jul 2022 16:56:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239382AbiGNQz6 (ORCPT ); Thu, 14 Jul 2022 12:55:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239171AbiGNQz4 (ORCPT ); Thu, 14 Jul 2022 12:55:56 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 523C84BD2A for ; Thu, 14 Jul 2022 09:55:55 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id a5so3334154wrx.12 for ; Thu, 14 Jul 2022 09:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ay55aei4xTrkHOP8ZwisRNILeuMCaqkFFuCni3Xut2k=; b=n/n3e8j6bJWOXrP95ItdWQVXPuQ0bCFwqzgIEykBYyxN3XjVeTR1h2M0DL/r3D8+I3 /wlwQamJPhfWq2SMEaES+gscw97bq95Af/SwrUZ2xpihPH0LoDtjSyx5KZ6OX7VHh74Y 2ThjifUbf5gBCXdAxi6cnn/9ECyQgHcx/tFyUwbKgSYON23z/QjPXt+UL4mCPvkiiaZB BfzF+kdEOK7IsC22SKqdZgxtyODLUH00aerRHytO8EVmLyMQvKNSH8tlkSRlFMtdPxel VtKnZSYceBp0ZlmE4s7lh/U+Mu4GNt0iBnfIIbXLxlDhGzjC/okAk+Tc/d5AcgkHDnqB b8Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ay55aei4xTrkHOP8ZwisRNILeuMCaqkFFuCni3Xut2k=; b=cpytjsbxWi1J6johqYaU6JQCF0N98GFlnpzbsQMAsPRo/zmasOCguOKTrxN86KZ/6R pJb5RameTuPhf26WeEBR8wXQMohReUbVlZP0DsCKJTy5CdqJr5jEmI0V+DI+SKyrE7qY UR9lX7SbYyP23TPL1WKpQeA9wQMl9EipyQYUzzkPT1aD9+EsMSAjW0kqMLP9lvXxJT+5 idw818YBktza30fmIJ4Vml/BK1a7A0jkux0590i1Sg9zM9sBUgcdDd/iUmQagGj1Cj0J uXcXBLYSD8QgaCH91MFk2wQXrX/qm9w2cGyfqzeA/+cqVryzOTOOctuVkQmXq69D7UCq /BNw== X-Gm-Message-State: AJIora8WE593GGiDnTme2p+p/fzG8sAKp5WxzD+pS5WgBkqmOIA6Tw9E KasEEeacymJ35g0MKf1b0W8IFA== X-Google-Smtp-Source: AGRyM1vl2oDUNW33308hydkFGVWAVq3Dvpg9TwiwSGovoYQ89wJOF+Z1+82DoJM6Mkt65ij0+18yVw== X-Received: by 2002:a05:6000:381:b0:21d:bb54:ae2c with SMTP id u1-20020a056000038100b0021dbb54ae2cmr8677229wrf.222.1657817753512; Thu, 14 Jul 2022 09:55:53 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id j9-20020a05600c190900b0039db31f6372sm7440915wmq.2.2022.07.14.09.55.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:53 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/6] iommu/exynos: Reuse SysMMU constants for page size and order Date: Thu, 14 Jul 2022 19:55:45 +0300 Message-Id: <20220714165550.8884-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Using SZ_4K in context of SysMMU driver is better than using PAGE_SIZE, as PAGE_SIZE might have different value on different platforms. Though it would be even better to use more specific constants, already existing in SysMMU driver. Make the code more strict by using SPAGE_ORDER and SPAGE_SIZE constants. It also makes sense, as __sysmmu_tlb_invalidate_entry() also uses SPAGE_* constants for further calculations with num_inv param, so it's logical that num_inv should be previously calculated using also SPAGE_* values. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Acked-by: Marek Szyprowski --- Changes in v3: - Added Marek's Acked-by tag - Added Krzysztof's R-b tag Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 79729892eb48..8f80aaa35092 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -340,7 +340,7 @@ static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) if (MMU_MAJ_VER(data->version) < 5) writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); else - writel(pgd / SZ_4K, data->sfrbase + REG_V5_PT_BASE_PFN); + writel(pgd >> SPAGE_ORDER, data->sfrbase + REG_V5_PT_BASE_PFN); __sysmmu_tlb_invalidate(data); } @@ -550,7 +550,7 @@ static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, * 64KB page can be one of 16 consecutive sets. */ if (MMU_MAJ_VER(data->version) == 2) - num_inv = min_t(unsigned int, size / SZ_4K, 64); + num_inv = min_t(unsigned int, size / SPAGE_SIZE, 64); if (sysmmu_block(data)) { __sysmmu_tlb_invalidate_entry(data, iova, num_inv); From patchwork Thu Jul 14 16:55:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 590730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FB78CCA47C for ; Thu, 14 Jul 2022 16:56:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239238AbiGNQz7 (ORCPT ); Thu, 14 Jul 2022 12:55:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238677AbiGNQz5 (ORCPT ); Thu, 14 Jul 2022 12:55:57 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AB9A4E851 for ; Thu, 14 Jul 2022 09:55:56 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id r14so3390982wrg.1 for ; Thu, 14 Jul 2022 09:55:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S2fOwRS7PBfoQ/JKwgWoKuZEaYFo7PU9A3pBuSjiPrw=; b=FJYTZoClCTlgrArGKeLYT8JUYfT6a60vzX4X3MgwAp51q4tyoTeo+z3gFLcTsZ2bEo j5hT5ULynZb3pQJxareXMpi7f4RSaQGIqIRmviSi/4Xus+TNZzAs7hp452FuzBLFcg7w ywRqEzWxw2c5kKbfm7iRwREbZpU/D9Jbff+gcPJmQI20iQSSqv+5mKOSIMME1uH6Csqf 4IHfl34HFOIAJvzJabWhKe77UZiHWzC+CtPvYvqQXckMhS4zPEQZF4UX1Zw1vDU0/CAt dPiIkVHGtob3+NZ66Xeonz4SYNmBVvCx8iC2hnD+CoOV7FIha5uMQbJ52A7oHmZvbs3I 60LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S2fOwRS7PBfoQ/JKwgWoKuZEaYFo7PU9A3pBuSjiPrw=; b=XBW2WiRduJKmSsvVLlLLJ2j8A30j4e/yPJy269hXXFfrg0ZI5p374NynX7/96/Rft3 ukKX7PgBd3f9Zz+ejXXe3TJTVv6z42yIwnTuKHJEPL3k8lPZJTz8N8UYqMKLtxcnpAq+ igOU02T9j9AU7Zhjm+Xvv+29qiTI1VEi2nU7m3nIvsLRVyUyPu5Nzf/UnXbzd9j9xpix PoQ2m+YYoZbjjOO5zU1QF1ZxLQrKG2OIvNv+zS4xvcyV5DWFF7XGPZDrJtoTKBRaAAqF ukY84YxWYjOelRsUdeaWYWG/1flQHrGZt2KdES4rJYRgvew3JDpaIYbA8NKLZLiVFcJg ajtQ== X-Gm-Message-State: AJIora/fng5+kKydJ4vf9k8qnwPiTnsCOGahaqiwScVikIltgzad/pqf D6yGTsw9VNUTF9h+6MHch+2ECw== X-Google-Smtp-Source: AGRyM1uOCE0ebi2E5Ao34myU6FQDDLS+28S7amW2//dWGnRsQjZ0isNECaLLQ5j97W3z0Vyo//ZQ7g== X-Received: by 2002:a5d:6489:0:b0:21d:a9a1:3511 with SMTP id o9-20020a5d6489000000b0021da9a13511mr8725414wri.626.1657817754857; Thu, 14 Jul 2022 09:55:54 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id z8-20020a1c4c08000000b003942a244f40sm5706762wmf.25.2022.07.14.09.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:54 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/6] iommu/exynos: Handle failed IOMMU device registration properly Date: Thu, 14 Jul 2022 19:55:46 +0300 Message-Id: <20220714165550.8884-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org If iommu_device_register() fails in exynos_sysmmu_probe(), the previous calls have to be cleaned up. In this case, the iommu_device_sysfs_add() should be cleaned up, by calling its remove counterpart call. Fixes: d2c302b6e8b1 ("iommu/exynos: Make use of iommu_device_register interface") Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Acked-by: Marek Szyprowski --- Changes in v3: - Added Marek's Acked-by tag - Added Krzysztof's R-b tag - Added "Fixes" tag, as suggested by Krzysztof Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 8f80aaa35092..c85db9dab851 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -629,7 +629,7 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) ret = iommu_device_register(&data->iommu, &exynos_iommu_ops, dev); if (ret) - return ret; + goto err_iommu_register; platform_set_drvdata(pdev, data); @@ -656,6 +656,10 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) pm_runtime_enable(dev); return 0; + +err_iommu_register: + iommu_device_sysfs_remove(&data->iommu); + return ret; } static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) From patchwork Thu Jul 14 16:55:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 593237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59CD5C43334 for ; Thu, 14 Jul 2022 16:56:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238905AbiGNQ4B (ORCPT ); Thu, 14 Jul 2022 12:56:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239359AbiGNQz6 (ORCPT ); Thu, 14 Jul 2022 12:55:58 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7AA454C99 for ; Thu, 14 Jul 2022 09:55:57 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id n185so1401965wmn.4 for ; Thu, 14 Jul 2022 09:55:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IZpjZAr4g1dpDBXrOrcfUkHPeUERh/JliRxp06JVucg=; b=W+Cm9cW/KqhsoUWLtK5lM2En6frOk3DnHTnfxJ1rLk8V1Yy7iqDT/XaD3KJvZtRB2s +wI1V2J9RGVol7di4+23oo12YHUhRPKldPKSV9YjJ5yjRhjrP2WaAN5WBs0dNPgnNpad HuJTHxC2yiT+rhVjRowuYazf0MbDsgo69VCsIM7HubxLF7kelLSkr0esfPhTrUxEUoAj qUDA/f2J+d74jP7aA8vMRl/XbZaIPTTn4CP/4jHqkfLZl09qcxuI9UEK/0ESchYUL1Bo wEKWTz5GNh1u+XnfmJpCtUYZJu5ERLefGE8Eh3Pylxz82X29Qo84Fi4d8pzdT2NYw5FK AGwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZpjZAr4g1dpDBXrOrcfUkHPeUERh/JliRxp06JVucg=; b=1SCIWrgitiXDqSjbjKrGdqBy4/TL0HnHHCHA7hEPHn2zAEYCxyxlKE4QLwuzgRa/yO 4moVvtQCgohRS6u4PXf/Fp7hRrdC17Ol49HpfiVCQbK+XOZ/LnNGfRSU1rUB5NYoC8b4 0GLi1zozihZ5iMaZfvzjg5Mq+/0e1EPCcbcAjK/c9kdMvhGXeqJMtQcKiZbb9JLYOZtD G6oGvB6oOUKLD0eSM0uYk634DYl1ibtE4CCP1g1Layhi9QskIsvUhBb8fQ5KG5IGzN69 CTwV5XeypwaippqlpklLrfxhCRfLENf7JKUE7alOH0oIsUhckVTmIb+E5g/Gq9VUklfy e4UA== X-Gm-Message-State: AJIora+7h1JWjPBKenUYUEwee57H1Ooo1Wr0n5NpvWmMbjfROBWRopx6 N2CLLhij3iCgsND6Nv6qsJfZQQ== X-Google-Smtp-Source: AGRyM1s5SKEFz/1UdqSHlysek2UsdEyn9+B60Wl05LPjeSEpx2hr6sr3sPBM4eoFrT1tNuALszo/rg== X-Received: by 2002:a05:600c:1e87:b0:3a2:fd16:5934 with SMTP id be7-20020a05600c1e8700b003a2fd165934mr9028538wmb.25.1657817756378; Thu, 14 Jul 2022 09:55:56 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id l13-20020a05600c2ccd00b003a2f2bb72d5sm5516033wmc.45.2022.07.14.09.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:55 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] iommu/exynos: Set correct dma mask for SysMMU v5+ Date: Thu, 14 Jul 2022 19:55:47 +0300 Message-Id: <20220714165550.8884-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org SysMMU v5+ supports 36 bit physical address space. Set corresponding DMA mask to avoid falling back to SWTLBIO usage in dma_map_single() because of failed dma_capable() check. The original code for this fix was suggested by Marek. Signed-off-by: Sam Protsenko Co-developed-by: Marek Szyprowski Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- Changes in v3: - Added Krzysztof's Acked-by tag Changes in v2: - Handled failed dma_set_mask() call - Replaced "Originally-by" tag by "Co-developed-by" + SoB tags drivers/iommu/exynos-iommu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index c85db9dab851..494f7d7aa9c5 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -646,6 +646,14 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) } } + if (MMU_MAJ_VER(data->version) >= 5) { + ret = dma_set_mask(dev, DMA_BIT_MASK(36)); + if (ret) { + dev_err(dev, "Unable to set DMA mask: %d\n", ret); + goto err_dma_set_mask; + } + } + /* * use the first registered sysmmu device for performing * dma mapping operations on iommu page tables (cpu cache flush) @@ -657,6 +665,8 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) return 0; +err_dma_set_mask: + iommu_device_unregister(&data->iommu); err_iommu_register: iommu_device_sysfs_remove(&data->iommu); return ret; From patchwork Thu Jul 14 16:55:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 590729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C760C433EF for ; Thu, 14 Jul 2022 16:56:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239973AbiGNQ4I (ORCPT ); Thu, 14 Jul 2022 12:56:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239480AbiGNQ4B (ORCPT ); Thu, 14 Jul 2022 12:56:01 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D38C4D4F8 for ; Thu, 14 Jul 2022 09:55:59 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id ay11-20020a05600c1e0b00b003a3013da120so1449653wmb.5 for ; Thu, 14 Jul 2022 09:55:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ABbzKk/sxz3POb/Xov9eiP5fUgIWe8jtTJuKOXitFhI=; b=ksSS2xxwNkmUX9p310Z0U9LSRA5cdiAu/XA/HO6LifqxJjYqzLajAN16cai+U8KyfZ Z954IRliopxFweXjmk4TJjz+bnRBrHBhZuMRik4H3U38WYtJ9ONz6QnEKVTbrrJ1kBkI Cr5Aqh6Xd1SDSuo7BVSeekBDQNxggADVXRuqHB0raotCYzBYNzjlCBBhSZIlmrJFbQXE EdJPlOZDPQmkwPMFmil8kFZM14o1j9cX3j3L6nYgoQ/R4vAH2betfrXE/DjIQd4mgTX0 j7EA3ME2aqPCPdY2lsOOCigdcNDdZFQR6q5giFSW+6wWjTwLExeRNDNrZW1DcI9rw7FB eARg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ABbzKk/sxz3POb/Xov9eiP5fUgIWe8jtTJuKOXitFhI=; b=59+DMJCzY2OdGNMuNvC8nG3ly5afFmqqhIBfaCjjglQvs7nBw+B6kG4qmsMfCk1DUb 9unJToDM2bvTaoO6bxyU1JToWNWWtrj6HePE1rNsRSiU0LF3jdZwYa21qD+ChRwz0W7c k6G2Ei80vziPWHX31cgu0zjPq8rNwELrt3WIsPHeCLOZCZaMLXELo0vpnTGnwGfqr4EG OLYhMChRdv+gvy/ESCNggz9/2eQMrr69/C4MY5PqerKv5+01VjpSZdQZ/ChtKRNNGye8 myOOKoDbhw4MN7+ob6gwX45YIYwBFdiUhnwyDQ0T4Xdm0xYPn7rEemihvyimkhHK3+Y/ eugQ== X-Gm-Message-State: AJIora+SoC6gse6a86z/5ttOny9xdjaI3Olh/OxkxgR1u84VqBMz7vqF k9nBjgMlLFGNzUo/nL7fRjPwhA== X-Google-Smtp-Source: AGRyM1tJIIY8m1U5Jj1xzKMCWd0QWpH+Rbh3z+j1akm/N/3A1wloek2Honra7mfm8CDl+4dSWMofMQ== X-Received: by 2002:a05:600c:2258:b0:3a1:8cba:646 with SMTP id a24-20020a05600c225800b003a18cba0646mr10224837wmm.7.1657817757705; Thu, 14 Jul 2022 09:55:57 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id k9-20020a05600c1c8900b003974cb37a94sm6209144wms.22.2022.07.14.09.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:57 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/6] iommu/exynos: Abstract non-common registers on different variants Date: Thu, 14 Jul 2022 19:55:48 +0300 Message-Id: <20220714165550.8884-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org At the moment the driver supports SysMMU v1..v5 versions. SysMMU v5 has different register layout than SysMMU v1..v3. Instead of checking the version each time before reading/writing the registers, let's create corresponding register structure for each SysMMU version and set the needed structure on init, checking the SysMMU version one single time. This way is faster and more elegant. No behavior changes from the user's point of view, it's only a refactoring patch. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski --- Changes in v3: - Added Marek's Acked-by tag - Removed abstracting common regs, used plain readl/writel to access those instead - Used variant struct instead of array to keep non-common register offsets - Removed 0x1 value used as an offset for missing registers - Merged __sysmmu_hw_info() into __sysmmu_get_version() - Refactored __sysmmu_tlb_invalidate_entry() for "num_inv == 1" case - Reworked the commit message w.r.t. all changes Changes in v2: - Reworked existing code (SysMMU v1..v5) to use this approach - Extracted v7 registers to the separate patches - Replaced MMU_REG() with corresponding SysMMU read/write functions - Improved the comment for 0x1 offsets triggering an unaligned access exception - Removed support for VMID number, as only VMID=0 (default) is used for now - Renamed register index names to reflect the old SysMMU version register names drivers/iommu/exynos-iommu.c | 100 +++++++++++++++++++++-------------- 1 file changed, 60 insertions(+), 40 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 494f7d7aa9c5..6a0299fe1722 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -148,26 +148,12 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) /* v1.x - v3.x registers */ -#define REG_MMU_FLUSH 0x00C -#define REG_MMU_FLUSH_ENTRY 0x010 -#define REG_PT_BASE_ADDR 0x014 -#define REG_INT_STATUS 0x018 -#define REG_INT_CLEAR 0x01C - #define REG_PAGE_FAULT_ADDR 0x024 #define REG_AW_FAULT_ADDR 0x028 #define REG_AR_FAULT_ADDR 0x02C #define REG_DEFAULT_SLAVE_ADDR 0x030 /* v5.x registers */ -#define REG_V5_PT_BASE_PFN 0x00C -#define REG_V5_MMU_FLUSH_ALL 0x010 -#define REG_V5_MMU_FLUSH_ENTRY 0x014 -#define REG_V5_MMU_FLUSH_RANGE 0x018 -#define REG_V5_MMU_FLUSH_START 0x020 -#define REG_V5_MMU_FLUSH_END 0x024 -#define REG_V5_INT_STATUS 0x060 -#define REG_V5_INT_CLEAR 0x064 #define REG_V5_FAULT_AR_VA 0x070 #define REG_V5_FAULT_AW_VA 0x080 @@ -250,6 +236,21 @@ struct exynos_iommu_domain { struct iommu_domain domain; /* generic domain data structure */ }; +/* + * SysMMU version specific data. Contains offsets for the registers which can + * be found in different SysMMU variants, but have different offset values. + */ +struct sysmmu_variant { + u32 pt_base; /* page table base address (physical) */ + u32 flush_all; /* invalidate all TLB entries */ + u32 flush_entry; /* invalidate specific TLB entry */ + u32 flush_range; /* invalidate TLB entries in specified range */ + u32 flush_start; /* start address of range invalidation */ + u32 flush_end; /* end address of range invalidation */ + u32 int_status; /* interrupt status information */ + u32 int_clear; /* clear the interrupt */ +}; + /* * This structure hold all data of a single SYSMMU controller, this includes * hw resources like registers and clocks, pointers and list nodes to connect @@ -274,6 +275,30 @@ struct sysmmu_drvdata { unsigned int version; /* our version */ struct iommu_device iommu; /* IOMMU core handle */ + const struct sysmmu_variant *variant; /* version specific data */ +}; + +#define SYSMMU_REG(data, reg) ((data)->sfrbase + (data)->variant->reg) + +/* SysMMU v1..v3 */ +static const struct sysmmu_variant sysmmu_v1_variant = { + .flush_all = 0x0c, + .flush_entry = 0x10, + .pt_base = 0x14, + .int_status = 0x18, + .int_clear = 0x1c, +}; + +/* SysMMU v5 */ +static const struct sysmmu_variant sysmmu_v5_variant = { + .pt_base = 0x0c, + .flush_all = 0x10, + .flush_entry = 0x14, + .flush_range = 0x18, + .flush_start = 0x20, + .flush_end = 0x24, + .int_status = 0x60, + .int_clear = 0x64, }; static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) @@ -304,10 +329,7 @@ static bool sysmmu_block(struct sysmmu_drvdata *data) static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) { - if (MMU_MAJ_VER(data->version) < 5) - writel(0x1, data->sfrbase + REG_MMU_FLUSH); - else - writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); + writel(0x1, SYSMMU_REG(data, flush_all)); } static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, @@ -315,33 +337,30 @@ static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, { unsigned int i; - if (MMU_MAJ_VER(data->version) < 5) { + if (MMU_MAJ_VER(data->version) < 5 || num_inv == 1) { for (i = 0; i < num_inv; i++) { writel((iova & SPAGE_MASK) | 1, - data->sfrbase + REG_MMU_FLUSH_ENTRY); + SYSMMU_REG(data, flush_entry)); iova += SPAGE_SIZE; } } else { - if (num_inv == 1) { - writel((iova & SPAGE_MASK) | 1, - data->sfrbase + REG_V5_MMU_FLUSH_ENTRY); - } else { - writel((iova & SPAGE_MASK), - data->sfrbase + REG_V5_MMU_FLUSH_START); - writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, - data->sfrbase + REG_V5_MMU_FLUSH_END); - writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE); - } + writel(iova & SPAGE_MASK, SYSMMU_REG(data, flush_start)); + writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, + SYSMMU_REG(data, flush_end)); + writel(0x1, SYSMMU_REG(data, flush_range)); } } static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) { + u32 pt_base; + if (MMU_MAJ_VER(data->version) < 5) - writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); + pt_base = pgd; else - writel(pgd >> SPAGE_ORDER, data->sfrbase + REG_V5_PT_BASE_PFN); + pt_base = pgd >> SPAGE_ORDER; + writel(pt_base, SYSMMU_REG(data, pt_base)); __sysmmu_tlb_invalidate(data); } @@ -378,6 +397,11 @@ static void __sysmmu_get_version(struct sysmmu_drvdata *data) dev_dbg(data->sysmmu, "hardware version: %d.%d\n", MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); + if (MMU_MAJ_VER(data->version) < 5) + data->variant = &sysmmu_v1_variant; + else + data->variant = &sysmmu_v5_variant; + __sysmmu_disable_clocks(data); } @@ -405,19 +429,14 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) const struct sysmmu_fault_info *finfo; unsigned int i, n, itype; sysmmu_iova_t fault_addr; - unsigned short reg_status, reg_clear; int ret = -ENOSYS; WARN_ON(!data->active); if (MMU_MAJ_VER(data->version) < 5) { - reg_status = REG_INT_STATUS; - reg_clear = REG_INT_CLEAR; finfo = sysmmu_faults; n = ARRAY_SIZE(sysmmu_faults); } else { - reg_status = REG_V5_INT_STATUS; - reg_clear = REG_V5_INT_CLEAR; finfo = sysmmu_v5_faults; n = ARRAY_SIZE(sysmmu_v5_faults); } @@ -426,7 +445,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) clk_enable(data->clk_master); - itype = __ffs(readl(data->sfrbase + reg_status)); + itype = __ffs(readl(SYSMMU_REG(data, int_status))); for (i = 0; i < n; i++, finfo++) if (finfo->bit == itype) break; @@ -443,7 +462,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) /* fault is not recovered by fault handler */ BUG_ON(ret != 0); - writel(1 << itype, data->sfrbase + reg_clear); + writel(1 << itype, SYSMMU_REG(data, int_clear)); sysmmu_unblock(data); @@ -622,6 +641,8 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) data->sysmmu = dev; spin_lock_init(&data->lock); + __sysmmu_get_version(data); + ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, dev_name(data->sysmmu)); if (ret) @@ -633,7 +654,6 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, data); - __sysmmu_get_version(data); if (PG_ENT_SHIFT < 0) { if (MMU_MAJ_VER(data->version) < 5) { PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; From patchwork Thu Jul 14 16:55:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 590728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5179ACCA47B for ; Thu, 14 Jul 2022 16:56:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239739AbiGNQ4Q (ORCPT ); Thu, 14 Jul 2022 12:56:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239712AbiGNQ4C (ORCPT ); Thu, 14 Jul 2022 12:56:02 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CE4E4B0E1 for ; Thu, 14 Jul 2022 09:56:00 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id j29-20020a05600c1c1d00b003a2fdafdefbso1577185wms.2 for ; Thu, 14 Jul 2022 09:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=55TJor/aCJoOF4UFT1NY5SUJ0CHcR5BKyA02/AHT5cA=; b=byRP/VN0EqKXhheJyOKz3lqTWrKNaT9JuVUOLLLCWecygrJz5FM+E/i8q8DMlThq6e Ixc0EA9Qe2ffbdpY9lvTl5gcr8ws7Szeag2UHmhxb6V72ykanixC5tPpgohQFBYTag8o Epb4T+hw2QFVaENvVDZJF2CmI7ipwyRwrobXZGRX0LnZDCN6gMNbDgChPk/bTZqICXD7 7RDMRE6VsKtDGJrd28oq0UybVqVKMo7UIT4Idtm09O2b4pSIdjJDYK/Lb9jdj7fcLGHL kFQRBhko2FwlI1Ox8QbiiKLTrfnB2haQFB8Irrapx2jH1bWc8pC0qdrnfktZvEcvmJc7 t3UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=55TJor/aCJoOF4UFT1NY5SUJ0CHcR5BKyA02/AHT5cA=; b=qzkpOt51X6OYMpKK669GLxVzzWtiOOaWfBJ96H9sZgXtfvZg5IXm4/Wpts4jMvUakn VBfMEYiu0HLJU1VhyiJfTjAlCWsef7MqthKAyRdce2wqmKZwJnAb7K5Cci2uupfawTB+ ov9K0nqCa3fN+LqerQ3XP1liXxuZPNo8BPbY3Qq/NKm8nEffdH8WIUIFYLQVvY+eeJh5 cYi14BVFaRKo7U3460oOF58B5ehgGwbBza9NKKUGnlg6BdgMKC1eBKCy4jrauVS4EXvd FJy+LUiqTdqptbJfrmrSAdnWohKBj9QDGKgcOmCJiZ2I9qkgXBTxvAkQr/1/3oz3ITeo p4fA== X-Gm-Message-State: AJIora8J0lIvKqdS/VoEDx1wOfkoKAwrFCwzlOoiUobrne2/yl9K59CA adBuowknSRyKbaOPL5jdUtZ+uA== X-Google-Smtp-Source: AGRyM1vvKu2kw7N9KRAEjNxUqHhJ2Bqucjaaf8iDnA3CwW9K5CvrPj01Y3rCAjO1g6YvCESEdQJl8g== X-Received: by 2002:a05:600c:1d9a:b0:3a3:34d:d6ac with SMTP id p26-20020a05600c1d9a00b003a3034dd6acmr2971190wms.206.1657817759428; Thu, 14 Jul 2022 09:55:59 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id z18-20020a5d4c92000000b0021d6d18a9f8sm1887563wrs.76.2022.07.14.09.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:58 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] iommu/exynos: Add SysMMU v7 register set Date: Thu, 14 Jul 2022 19:55:49 +0300 Message-Id: <20220714165550.8884-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org SysMMU v7 might have different register layouts (VM capable or non-VM capable). Virtual Machine registers (if present) implement multiple translation domains. If VM registers are not present, the driver shouldn't try to access those. Check which layout is implemented in current SysMMU module (by reading the capability registers) and prepare the corresponding variant structure for further usage. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski --- Changes in v3: - Merged "Check if SysMMU v7 has VM registers" patch into this patch - Reworked for using variant struct (instead of array) Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 50 +++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 6a0299fe1722..fc9ef3ff0057 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -135,6 +135,9 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ +#define CAPA0_CAPA1_EXIST BIT(11) +#define CAPA1_VCR_ENABLED BIT(14) + /* common registers */ #define REG_MMU_CTRL 0x000 #define REG_MMU_CFG 0x004 @@ -157,6 +160,10 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define REG_V5_FAULT_AR_VA 0x070 #define REG_V5_FAULT_AW_VA 0x080 +/* v7.x registers */ +#define REG_V7_CAPA0 0x870 +#define REG_V7_CAPA1 0x874 + #define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) static struct device *dma_dev; @@ -276,6 +283,9 @@ struct sysmmu_drvdata { struct iommu_device iommu; /* IOMMU core handle */ const struct sysmmu_variant *variant; /* version specific data */ + + /* v7 fields */ + bool has_vcr; /* virtual machine control register */ }; #define SYSMMU_REG(data, reg) ((data)->sfrbase + (data)->variant->reg) @@ -289,7 +299,7 @@ static const struct sysmmu_variant sysmmu_v1_variant = { .int_clear = 0x1c, }; -/* SysMMU v5 */ +/* SysMMU v5 and v7 (non-VM capable) */ static const struct sysmmu_variant sysmmu_v5_variant = { .pt_base = 0x0c, .flush_all = 0x10, @@ -301,6 +311,18 @@ static const struct sysmmu_variant sysmmu_v5_variant = { .int_clear = 0x64, }; +/* SysMMU v7: VM capable register set */ +static const struct sysmmu_variant sysmmu_v7_vm_variant = { + .pt_base = 0x800c, + .flush_all = 0x8010, + .flush_entry = 0x8014, + .flush_range = 0x8018, + .flush_start = 0x8020, + .flush_end = 0x8024, + .int_status = 0x60, + .int_clear = 0x64, +}; + static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) { return container_of(dom, struct exynos_iommu_domain, domain); @@ -380,6 +402,20 @@ static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) clk_disable_unprepare(data->clk_master); } +static bool __sysmmu_has_capa1(struct sysmmu_drvdata *data) +{ + u32 capa0 = readl(data->sfrbase + REG_V7_CAPA0); + + return capa0 & CAPA0_CAPA1_EXIST; +} + +static void __sysmmu_get_vcr(struct sysmmu_drvdata *data) +{ + u32 capa1 = readl(data->sfrbase + REG_V7_CAPA1); + + data->has_vcr = capa1 & CAPA1_VCR_ENABLED; +} + static void __sysmmu_get_version(struct sysmmu_drvdata *data) { u32 ver; @@ -397,10 +433,18 @@ static void __sysmmu_get_version(struct sysmmu_drvdata *data) dev_dbg(data->sysmmu, "hardware version: %d.%d\n", MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); - if (MMU_MAJ_VER(data->version) < 5) + if (MMU_MAJ_VER(data->version) < 5) { data->variant = &sysmmu_v1_variant; - else + } else if (MMU_MAJ_VER(data->version) < 7) { data->variant = &sysmmu_v5_variant; + } else { + if (__sysmmu_has_capa1(data)) + __sysmmu_get_vcr(data); + if (data->has_vcr) + data->variant = &sysmmu_v7_vm_variant; + else + data->variant = &sysmmu_v5_variant; + } __sysmmu_disable_clocks(data); } From patchwork Thu Jul 14 16:55:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 593236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9D81C43334 for ; Thu, 14 Jul 2022 16:56:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239150AbiGNQ4P (ORCPT ); Thu, 14 Jul 2022 12:56:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239841AbiGNQ4D (ORCPT ); Thu, 14 Jul 2022 12:56:03 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55BCC55097 for ; Thu, 14 Jul 2022 09:56:02 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id z12so3369263wrq.7 for ; Thu, 14 Jul 2022 09:56:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nU0WVVbdgEc789G5a6s5LocA0QeCbC2E3DQ5sHk48Y8=; b=IYzHDmH6TgdKlf033EfO1Bg7jNq4Zm8uLryO7o6yzv6Ii23qReYyoXEWZNdJN4wNBz 91CunxhQuK2D4gOwqIQIPlvaMskTJn7ZqteC4EL4/6gPBvpJkKZAGc3wGrtaJG9IxL1a CB6noJky+hMahbL7giTw4QO2UCSHzu3CTOHUm7EF2V1L2UClKHK+r40pTMyRCWXgwEcC +5R7j+/v2Xc3nW2EhkvgoQgVYu7cXbbRPBdQJqhy0NF2Ua1NcIxp2VMipbNQTsSp1Lfy 2DWAETiTz1VZ9n+vIBEjZlwLH54b4etHBnO4sCojLtvP+erRugR8wUTqVr8wd9Mi967+ yWTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nU0WVVbdgEc789G5a6s5LocA0QeCbC2E3DQ5sHk48Y8=; b=OKVu3hzT534lbhB+kl9Nqx8Jvc5JwHdy6VtPybqy+CbBMg3fzBwP5g7KmybS7V99Xp Ai3cbg2mTOhFaW4QikZqYANUB849q34lSPjuLfgsyq2Q/5E1vqhL7+YkLyLN/kHJsman jRhnIoEMoIZbIFnSbCdqo1VCJ3JM0AChHCbPYLKdEkSL02Ufq95bn6rtbJu+48JmhyVa 7tA+rfTqz6nOGuBNgNHlle6/pGwEos1dzruWlDlbsewkHWyT9HqrpOqSNQZtisEg3SZB 1K6I+hCvoJND9+0GTFWjzVKQfg4RH6RKpaWusGsjiouGbalrRFH9EZsVWL+HQhkyYFvq TmQQ== X-Gm-Message-State: AJIora/s+UwsMzF7rXol1J6Vwd0hfZ9fal01l/Lfdbp7oNvaY9YGBLWd /l5LdwtwmYtWodNW/4LSaceSiQ== X-Google-Smtp-Source: AGRyM1s90qNS8RahfDcyAz6R2NLl80gXy4ylX6MoZ40JpBSVeuXHVLVvAuPqfZ3uGCFbPVq6lPH2Xw== X-Received: by 2002:a5d:6da3:0:b0:21d:cde7:cb7 with SMTP id u3-20020a5d6da3000000b0021dcde70cb7mr227704wrs.683.1657817760912; Thu, 14 Jul 2022 09:56:00 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id l29-20020a05600c1d1d00b003a2e27fc275sm2797092wms.12.2022.07.14.09.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:56:00 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/6] iommu/exynos: Enable default VM instance on SysMMU v7 Date: Thu, 14 Jul 2022 19:55:50 +0300 Message-Id: <20220714165550.8884-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In order to enable SysMMU v7 with VM register layout, at least the default VM instance (n=0) must be enabled, in addition to enabling the SysMMU itself. To do so, add corresponding write to MMU_CTRL_VM[0] register, before writing to MMU_CTRL register. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski --- Changes in v3: - Reworked for using plain writel() - Added Marek's Acked-by tag Changes in v2: - Extracted VM enabling code to the separate function - Used new SysMMU read/write functions to access the registers drivers/iommu/exynos-iommu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index fc9ef3ff0057..8e18984a0c4f 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -135,6 +135,8 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ +#define CTRL_VM_ENABLE BIT(0) +#define CTRL_VM_FAULT_MODE_STALL BIT(3) #define CAPA0_CAPA1_EXIST BIT(11) #define CAPA1_VCR_ENABLED BIT(14) @@ -163,6 +165,7 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) /* v7.x registers */ #define REG_V7_CAPA0 0x870 #define REG_V7_CAPA1 0x874 +#define REG_V7_CTRL_VM 0x8000 #define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) @@ -548,6 +551,18 @@ static void __sysmmu_init_config(struct sysmmu_drvdata *data) writel(cfg, data->sfrbase + REG_MMU_CFG); } +static void __sysmmu_enable_vid(struct sysmmu_drvdata *data) +{ + u32 ctrl; + + if (MMU_MAJ_VER(data->version) < 7 || !data->has_vcr) + return; + + ctrl = readl(data->sfrbase + REG_V7_CTRL_VM); + ctrl |= CTRL_VM_ENABLE | CTRL_VM_FAULT_MODE_STALL; + writel(ctrl, data->sfrbase + REG_V7_CTRL_VM); +} + static void __sysmmu_enable(struct sysmmu_drvdata *data) { unsigned long flags; @@ -558,6 +573,7 @@ static void __sysmmu_enable(struct sysmmu_drvdata *data) writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); __sysmmu_init_config(data); __sysmmu_set_ptbase(data, data->pgtable); + __sysmmu_enable_vid(data); writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); data->active = true; spin_unlock_irqrestore(&data->lock, flags);