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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/15] hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high Date: Mon, 18 Jul 2022 14:59:06 +0100 Message-Id: <20220718135920.13667-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the M-profile Arm ARM, rule R_CVJS defines when an interrupt should be set to the Pending state: A) when the input line is high and the interrupt is not Active B) when the input line transitions from low to high and the interrupt is Active (Note that the first of these is an ongoing condition, and the second is a point-in-time event.) This can be rephrased as: 1 when the line goes from low to high, set Pending 2 when Active goes from 1 to 0, if line is high then set Pending 3 ignore attempts to clear Pending when the line is high and Active is 0 where 1 covers both B and one of the "transition into condition A" cases, 2 deals with the other "transition into condition A" possibility, and 3 is "don't drop Pending if we're already in condition A". Transitions out of condition A don't affect Pending state. We handle case 1 in set_irq_level(). For an interrupt (as opposed to other kinds of exception) the only place where we clear Active is in armv7m_nvic_complete_irq(), where we handle case 2 by checking for whether we need to re-pend the exception. For case 3, the only places where we clear Pending state on an interrupt are in armv7m_nvic_acknowledge_irq() (where we are setting Active so it doesn't count) and for writes to NVIC_ICPRn. It is the "write to NVIC_ICPRn" case that we missed: we must ignore this if the input line is high and the interrupt is not Active. (This required behaviour is differently and perhaps more clearly stated in the v7M Arm ARM, which has pseudocode in section B3.4.1 that implies it.) Reported-by: Igor Kotrasiński Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220628154724.3297442-1-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 13df002ce4d..1f7763964c3 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2389,8 +2389,15 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { + /* + * Note that if the input line is still held high and the interrupt + * is not active then rule R_CVJS requires that the Pending state + * remains set; in that case we mustn't let it be cleared. + */ if (value & (1 << i) && - (attrs.secure || s->itns[startvec + i])) { + (attrs.secure || s->itns[startvec + i]) && + !(setval == 0 && s->vectors[startvec + i].level && + !s->vectors[startvec + i].active)) { s->vectors[startvec + i].pending = setval; } } From patchwork Mon Jul 18 13:59:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591457 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3039946max; Mon, 18 Jul 2022 07:07:31 -0700 (PDT) X-Google-Smtp-Source: AGRyM1v9OKwqZSw+5D/xOO1X7YK0ZMe9zyGSi4Nz94HPsjM3uttPW/3VLNjeQh+/FEe6UNdhsxY/ X-Received: by 2002:ac8:5f0a:0:b0:31e:b219:1d4b with SMTP id x10-20020ac85f0a000000b0031eb2191d4bmr21274569qta.640.1658153251773; Mon, 18 Jul 2022 07:07:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658153251; cv=none; d=google.com; s=arc-20160816; b=E2Qen7VAE0L96CSk/pfM9iioLvIzd1Ki1GuPADp1qG2ZAsSZzIt4eC6KIFntKxWP0T tObfJ0RQsLx31LNmmZB6q2slX5dzinqslGOFlXpS/jXsDUNfxqVCDsSSj3tPeFALkERm Rr33xr3EQgOXd6RdD5SKnhYCrTCIcVadBOiO7c6frR90cLOQ7uS1n46EnW7f4ph00jYA vlSBahr0kS58KZu5V1aS6aK8v784PUK7LqzdivEokiJY/W/tbKZqwoZ2f5JMryUiYhko jwEyr6yw127tW82pcD885+kUyxAu0tqVXx1lMjK9FA3TwPIMoCXH5ateg0Z7HWwYz5Gf GX5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NsboqJpMKAMO89QQrdUhOCnjGLwfFQBesnrYOdMQBAo=; b=Kb5lTHe1Czpg5ub9RifEuPLCXJTe/fOPvzrnkKx+IG6lgAqajLz8L8xmyncXZrvrq2 in+KrDu1tePRhG2vVdwi5ApXu7z5yv9zifLvCmVBUuhSVXPsUkuOS/gxlJBmYfXx8RF4 jFXMBO8y0jnaVESMJcuf5PtiVE7bKa/TL0a+QkKI2kLOHnButUhe91z6f+COqz2l+umd RPnsAefNR1BzusWcoJhAvLVnW85axec0t+AcENYZ4wkRkCNUVIFWhTRgqTGGjFZVRPPv 2Otad0WzI1m/WeSrByIyYagsteyybz4eDwcU7ZddtrRMp4H3MoJdvUym/Gicpz7iJPKT QJ8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HkEFlE6T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/15] target/arm: Fill in VL for tbflags when SME enabled and SVE disabled Date: Mon, 18 Jul 2022 14:59:07 +0100 Message-Id: <20220718135920.13667-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When PSTATE.SM, VL = SVL even if SVE is disabled. This is visible in kselftest ssve-test. Reported-by: Mark Brown Signed-off-by: Richard Henderson Message-id: 20220713045848.217364-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cfcad97ce07..6fff7fc64fd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10882,13 +10882,19 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { int sme_el = sme_exception_el(env, el); + bool sm = FIELD_EX64(env->svcr, SVCR, SM); DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); if (sme_el == 0) { /* Similarly, do not compute SVL if SME is disabled. */ - DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + int svl = sve_vqm1_for_el_sm(env, el, true); + DP_TBFLAG_A64(flags, SVL, svl); + if (sm) { + /* If SVE is disabled, we will not have set VL above. */ + DP_TBFLAG_A64(flags, VL, svl); + } } - if (FIELD_EX64(env->svcr, SVCR, SM)) { + if (sm) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); } From patchwork Mon Jul 18 13:59:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591461 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3055896max; Mon, 18 Jul 2022 07:22:51 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tvhdWTJnHY6lSBrS3xUBraFH4/fOa1dAJA3mrkp65IvTOY7zhxQZ1oUwGQfNyERgSIrfsM X-Received: by 2002:a05:6214:2aac:b0:473:421d:d457 with SMTP id js12-20020a0562142aac00b00473421dd457mr21209691qvb.61.1658154171327; Mon, 18 Jul 2022 07:22:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154171; cv=none; d=google.com; s=arc-20160816; b=Tn6QLlumEXXofFVdxYMBKg9vEDIAsJBEBVdlRG1xqmmj6e1C/DeKONPxWbrkM+046c /1RlKeKmZ7Jkg1lRv+2e5OJEU/naRRCQCE/tFC8D7Xun3F84rbnLt4fdWnE/LYVQMuOH qF9RtKZjLUoPtoH4RfkAuwaPNzPbs78aRTKoyP66viyob9EjzY1tZELoxhgj8XVFn+9l cZTGcGc+Tpn0SpJZTU7J1e2hBu+lHZKZ56WYn4eT8+GNxEbkBUEaZZrkRo1XbZG1VB2o t71rLkDUp427omJfUHWG9jG1pK/e2WcBOwSNi0AdN/cr6nme//BsfNnzAGLaSFbzuiVu SOhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jUzTz5s5zsxreDDQya4YCpzbBiN04ee02WSt0TzEGbo=; b=hhH1UK8XXYoPttVIqN3/1lYcJRf8jSt45AIRgxNxrFhBbuEVw0XU0LUTYxU41omvR4 v1AUdtzMCGCOeoINWG8I9hZowKFCut2y8ohU9iblzl2h0us0rsQYngVtVlRdXCRC7uu3 O9YuJb4BuOq+nqvrzgZlGwnrNhlW/06OKSLC3JwolO8anaqvl2IcRdbm3KDCkjLfrPDQ AXdAbdEVDBaJksDGltAKoo+qjUHjX0hXx4q2qgnnCM2cuG4agvXFKzUuPlMCHFz5s2cG EzYouLixLUDYWkz40oVFEBcSSI8IwB0FaxUmoCQ1eXftaUAfIoSYhSO1ix+6BBqQibxK Bgug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="eaOPIy9/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME Date: Mon, 18 Jul 2022 14:59:08 +0100 Message-Id: <20220718135920.13667-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We were only checking for SVE disabled and not taking into account PSTATE.SM to check SME disabled, which resulted in vectors being incorrectly truncated. Signed-off-by: Richard Henderson Message-id: 20220713045848.217364-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6fff7fc64fd..24c45a9bf31 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11228,6 +11228,21 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) } } +static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState *env, int el, bool sm) +{ + int exc_el; + + if (sm) { + exc_el = sme_exception_el(env, el); + } else { + exc_el = sve_exception_el(env, el); + } + if (exc_el) { + return 0; /* disabled */ + } + return sve_vqm1_for_el_sm(env, el, sm); +} + /* * Notice a change in SVE vector size when changing EL. */ @@ -11236,7 +11251,7 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, { ARMCPU *cpu = env_archcpu(env); int old_len, new_len; - bool old_a64, new_a64; + bool old_a64, new_a64, sm; /* Nothing to do if no SVE. */ if (!cpu_isar_feature(aa64_sve, cpu)) { @@ -11256,7 +11271,8 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, * invoke ResetSVEState when taking an exception from, or * returning to, AArch32 state when PSTATE.SM is enabled. */ - if (old_a64 != new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { + sm = FIELD_EX64(env->svcr, SVCR, SM); + if (old_a64 != new_a64 && sm) { arm_reset_sve_state(env); return; } @@ -11273,10 +11289,13 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_len = (old_a64 && !sve_exception_el(env, old_el) - ? sve_vqm1_for_el(env, old_el) : 0); - new_len = (new_a64 && !sve_exception_el(env, new_el) - ? sve_vqm1_for_el(env, new_el) : 0); + old_len = new_len = 0; + if (old_a64) { + old_len = sve_vqm1_for_el_sm_ena(env, old_el, sm); + } + if (new_a64) { + new_len = sve_vqm1_for_el_sm_ena(env, new_el, sm); + } /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { From patchwork Mon Jul 18 13:59:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591460 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3055852max; Mon, 18 Jul 2022 07:22:49 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uzQC1msnMvqroGq0mPKrwa8uKIg+NbCFZjYCrEl1xSudLMYfJ0HHLx2daqDN3bEgpCL7BY X-Received: by 2002:ac8:5f06:0:b0:31e:e2b8:67c3 with SMTP id x6-20020ac85f06000000b0031ee2b867c3mr9148486qta.620.1658154169220; Mon, 18 Jul 2022 07:22:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154169; cv=none; d=google.com; s=arc-20160816; b=oJhtVu97n7Dz+HAPJ0C5NynVjkVz7vhb/Yz5NXipfT9e76ncQrCuMlcdWRn0LLZoHG yzTyrOq+1bVrdkZoa4A8UBYnAR47bHB9/tzjylGMrIdmN5YjQVC+IMKB9EbnP8Dbs3oP KnDjZAMMC0mgovnuJKLkqC/nxGmQLZ16FOWSOhWHJaeqDJ5WhSwmxlDBnvJh2PGkZNm1 XSGt2gMOsD+kad3vFWKi5J5D2nhL0Iv/Vmq4le351nHmafmoo19YACPtEQfGtPRQRnQf vkQAYwoOHHX2O7v0t1yhBrRx0mlFCAOolxL5B1VzAY0ySXR63fOJkxRZzBqcCL3ODYgE tvYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oX0cz/UuX4deysfpkWLa72UX1jaFnIUFPBqr5lkXZCA=; b=S181jC/qrjBMjjcYrx+YWe67PHju5qvancsSBeIboXHFWkDjWQfDM+l2obwwQ5z1T6 87/YL1fXNhSE3hTMbiiZwO70JcTNR+8Dl+/cd/0jwrMP4hpoTgun71u6edI/S8hXXRAX a7gGUAqbIcah5eg8HqrvCPOZKxFG6svvg4cehb/kvBxBpX/j2EbHOWdhgK4mYMxeQss5 M+PrTjm8qMuDgj3Pn5cB0Xi8ns+FPh+KeQvRwt7lGbheYKvxzZ3JHT6hnUtLmW5amvgE OBOiJes2I/22OEyr16OjUCc4gxG3DKpIAgMA+DOiEy9ADTuHClZd7b/shUZdu0h9e9Or 5+Qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GyY+vccb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/15] linux-user/aarch64: Do not clear PROT_MTE on mprotect Date: Mon, 18 Jul 2022 14:59:09 +0100 Message-Id: <20220718135920.13667-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The documentation for PROT_MTE says that it cannot be cleared by mprotect. Further, the implementation of the VM_ARCH_CLEAR bit, contains PROT_BTI confiming that bit should be cleared. Introduce PAGE_TARGET_STICKY to allow target/arch/cpu.h to control which bits may be reset during page_set_flags. This is sort of the opposite of VM_ARCH_CLEAR, but works better with qemu's PAGE_* bits that are separate from PROT_* bits. Reported-by: Vitaly Buka Signed-off-by: Richard Henderson Message-id: 20220711031420.17820-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 +++++-- accel/tcg/translate-all.c | 13 +++++++++++-- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e36a839ee4..6afcc882f2c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3392,9 +3392,12 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. + * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect + * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. */ -#define PAGE_BTI PAGE_TARGET_1 -#define PAGE_MTE PAGE_TARGET_2 +#define PAGE_BTI PAGE_TARGET_1 +#define PAGE_MTE PAGE_TARGET_2 +#define PAGE_TARGET_STICKY PAGE_MTE #ifdef TARGET_TAGGED_ADDRESSES /** diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8fd23a9d05f..ef62a199c7d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2256,6 +2256,15 @@ int page_get_flags(target_ulong address) return p->flags; } +/* + * Allow the target to decide if PAGE_TARGET_[12] may be reset. + * By default, they are not kept. + */ +#ifndef PAGE_TARGET_STICKY +#define PAGE_TARGET_STICKY 0 +#endif +#define PAGE_STICKY (PAGE_ANON | PAGE_TARGET_STICKY) + /* Modify the flags of a page and invalidate the code if necessary. The flag PAGE_WRITE_ORG is positioned automatically depending on PAGE_WRITE. The mmap_lock should already be held. */ @@ -2299,8 +2308,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->target_data = NULL; p->flags = flags; } else { - /* Using mprotect on a page does not change MAP_ANON. */ - p->flags = (p->flags & PAGE_ANON) | flags; + /* Using mprotect on a page does not change sticky bits. */ + p->flags = (p->flags & PAGE_STICKY) | flags; } } } From patchwork Mon Jul 18 13:59:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591458 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3043925max; Mon, 18 Jul 2022 07:11:12 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vnYmEZOOtyoQyVm3WhqdMcBQc0sN4sBxQo1ozKeewa2a4xXHtkrqVUcg+W8Vdnaqc3Fc6j X-Received: by 2002:a05:622a:1703:b0:31e:b547:ce4e with SMTP id h3-20020a05622a170300b0031eb547ce4emr21155405qtk.40.1658153472768; Mon, 18 Jul 2022 07:11:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658153472; cv=none; d=google.com; s=arc-20160816; b=0TcmnpenrOufJkIEBkafsPiGvm/5hE8Fjcc1oeKkaLY/gs+btcgg4wAZY31euOD5/q JQm8sSwwf6DH14BnD33qxUQVfi3W/qORKz2GRRTYYU9G6AZUmaGYpZx6Xn6o6ho90evw vMiqLi0TZKSiPZnVozBRaaSijpnG53Z4G5AMiHzwVJV+MtrAy2v9wmUkVRkKrcep1Nwo ILL6AEk5IfFzKCClOYWl9cE9UjiXuFdPQbwtyQKUW3NvHOiBXFs5vq3UC6Lvd/X39bZA YQpfv/zhUZmXCb1Me57qPOYpBymVIR1fKCMfnQxg8vKgVMakNaJF88pS1bRVF1/24eF0 fiKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WkWJRj26wPeTo9qIJ3RW2bntJqHKbO7FETgRMM6GtVw=; b=rcg51LtA3TQTDIYV5sWG4tUMVY4D91TIMRYtArpBuwm0YtDivg5wzKSqq2TU83+1WZ 6RX7BKFwYC9AXSH2cpH+X0/+6muZjCKbh1Nt0x2nIdsH4QIjfswp4CBcFRNym22/CmU8 /TVzTv+Tn+1oLJaE/chOX60LfNu/UXu28cy0GhSdWq7VMOXwOjmA1JKdT60s80ItfKqN aW7avTe27eQqTJ6+e5BgOCpWDUJPo+0UeYxHCjrwc7iTurVfWCp38D6334sCbqo5w0gt 5Rrv191v/qiqVrLuFM2X5L2MiG6ZH5Ls7roKWn4Vow5ZlcJHmVYKrst8dmbSNYBCX6vI Nsyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rrgHgSfh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/15] target/arm: Define and use new regime_tcr_value() function Date: Mon, 18 Jul 2022 14:59:10 +0100 Message-Id: <20220718135920.13667-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The regime_tcr() function returns a pointer to a struct TCR corresponding to the TCR controlling a translation regime. The struct TCR has the raw value of the register, plus two fields mask and base_mask which are used as a small optimization in the case of 32-bit short-descriptor lookups. Almost all callers of regime_tcr() only want the raw register value. Define and use a new regime_tcr_value() function which returns only the raw 64-bit register value. This is a preliminary to removing the 32-bit short descriptor optimization -- it only saves a handful of bit operations, which is tiny compared to the overhead of doing a page table walk at all, and the TCR struct is awkward and makes fixing https://gitlab.com/qemu-project/qemu/-/issues/1103 unnecessarily difficult. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-2-peter.maydell@linaro.org --- target/arm/internals.h | 6 ++++++ target/arm/helper.c | 6 +++--- target/arm/ptw.c | 8 ++++---- target/arm/tlb_helper.c | 2 +- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 00e2e710f6c..fa046124fa8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -793,6 +793,12 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } +/* Return the raw value of the TCR controlling this translation regime */ +static inline uint64_t regime_tcr_value(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + return regime_tcr(env, mmu_idx)->raw_tcr; +} + /** * arm_num_brps: Return number of implemented breakpoints. * Note that the ID register BRPS field is "number of bps - 1", diff --git a/target/arm/helper.c b/target/arm/helper.c index 24c45a9bf31..c245922bb5d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4216,7 +4216,7 @@ static int vae1_tlbmask(CPUARMState *env) static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) { - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr = regime_tcr_value(env, mmu_idx); int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); int select = extract64(addr, 55, 1); @@ -10158,7 +10158,7 @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr = regime_tcr_value(env, mmu_idx); bool epd, hpd, using16k, using64k, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu = env_archcpu(env); @@ -10849,7 +10849,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, { CPUARMTBFlags flags = {}; ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr = regime_tcr_value(env, mmu_idx); uint64_t sctlr; int tbii, tbid; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e71fc1f4293..0d7e8ffa41b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -820,7 +820,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr = regime_tcr_value(env, mmu_idx); uint32_t el = regime_el(env, mmu_idx); int select, tsz; bool epd, hpd; @@ -994,7 +994,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, uint32_t attrs; int32_t stride; int addrsize, inputsize, outputsize; - TCR *tcr = regime_tcr(env, mmu_idx); + uint64_t tcr = regime_tcr_value(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); uint64_t descaddrmask; @@ -1112,8 +1112,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, * For stage 2 translations the starting level is specified by the * VTCR_EL2.SL0 field (whose interpretation depends on the page size) */ - uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); - uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); + uint32_t sl0 = extract32(tcr, 6, 2); + uint32_t sl2 = extract64(tcr, 33, 1); uint32_t startlevel; bool ok; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7d8a86b3c45..a2f87a5042d 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -20,7 +20,7 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) return true; } if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { + && (regime_tcr_value(env, mmu_idx) & TTBCR_EAE)) { return true; } return false; From patchwork Mon Jul 18 13:59:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591469 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3063270max; Mon, 18 Jul 2022 07:31:21 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uSrb0KPCMwgYiTN3swhkKNW+cypmKqMqn5DT48XzmGooLlefV5OHhz0TcLdhO5zXOgSo1E X-Received: by 2002:a05:620a:25c9:b0:6b2:7409:892e with SMTP id y9-20020a05620a25c900b006b27409892emr16942944qko.367.1658154681670; Mon, 18 Jul 2022 07:31:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154681; cv=none; d=google.com; s=arc-20160816; b=NIA76yTOwrTka/nnx4IiupJFYJVl4oyu49Hq68P222b6lC+8yTbJatCwBMJ3HwARpZ HZlO91IMqmJg4/5slIJEAVht1R+hW3wyyoABAknJcZHPg+gRfPBkRE8Vdphd/YyWsdX/ /VNyPOVM3VDY+frYFeLUlFn1e1GQFnrunYIUIH3tEynyePNluHuZYoqswXrNCL7bw8VW 8cIUfMdNVQFhaesMSvS9/Pr06Kz7E27pvbChxmw5s1WBwuAvpePlaAFojWfNnsMnkcOh 2xDDCDhDGG58+2BroMUXmGFxZqhNXJmFtT/621o8glF2WVhK5a/g+W0Pj8KR9BRwOKFv b5BA== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/15] target/arm: Calculate mask/base_mask in get_level1_table_address() Date: Mon, 18 Jul 2022 14:59:11 +0100 Message-Id: <20220718135920.13667-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In get_level1_table_address(), instead of using precalculated values of mask and base_mask from the TCR struct, calculate them directly (in the same way we currently do in vmsa_ttbcr_raw_write() to populate the TCR struct fields). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-3-peter.maydell@linaro.org --- target/arm/ptw.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0d7e8ffa41b..16226d14233 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -315,20 +315,24 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - TCR *tcr = regime_tcr(env, mmu_idx); + uint64_t tcr = regime_tcr_value(env, mmu_idx); + int maskshift = extract32(tcr, 0, 3); + uint32_t mask = ~(((uint32_t)0xffffffffu) >> maskshift); + uint32_t base_mask; - if (address & tcr->mask) { - if (tcr->raw_tcr & TTBCR_PD1) { + if (address & mask) { + if (tcr & TTBCR_PD1) { /* Translation table walk disabled for TTBR1 */ return false; } *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; } else { - if (tcr->raw_tcr & TTBCR_PD0) { + if (tcr & TTBCR_PD0) { /* Translation table walk disabled for TTBR0 */ return false; } - *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; + base_mask = ~((uint32_t)0x3fffu >> maskshift); + *table = regime_ttbr(env, mmu_idx, 0) & base_mask; } *table |= (address >> 18) & 0x3ffc; return true; From patchwork Mon Jul 18 13:59:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591466 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3061178max; Mon, 18 Jul 2022 07:28:58 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sutOlHV2fnKAI47zI7UevTEeZh3MeshECNQGNS051Px8PZx3bArCF9df8l3e7Lr0T86uRa X-Received: by 2002:a05:622a:1789:b0:31e:a8ce:cb7 with SMTP id s9-20020a05622a178900b0031ea8ce0cb7mr21553368qtk.645.1658154538603; Mon, 18 Jul 2022 07:28:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154538; cv=none; d=google.com; s=arc-20160816; b=ir+cXoJN5zDod2NPtKf9enEtfyGf3GvSfvEHnAOJ2pglXqw7j0N3OotAwmqFwX6oUm lfo76HIw9nQP53nCNGrzH0gRqxwKx5LSL6BfMCZ/sGrNe4caOsGl7HIviI0blWs3d5RD pjJ6/XpX46WU2LmRREa3LPy89voWuWFcCYqQT+VGbunFengZRXB+owdnphRtFsoX5hxV H1UzsJhbB4DJ/URXJwhJgj7X+jcqSSlTiWBZ9CztWULyguYpV3Hu4lAasL2kUpIWPxq7 nzek7Y4o1RyB2sUa4wzSqyC3OjXXP3z6HatRcwu4B2LSl1hPcZrQH0sRjKMVrlfIso5u 7SBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ocRTy264UImfHohmga9Mhs3jVom81Fw75OT8Y228IS4=; b=HSgcwLrZYnXfRXshK29fjg4WG+Y0YrdaGSoqh08Y+ojbkGITTq51Y5mUn3htPhJbxH ffHtrGjMGnr5993tzUUh4SN79glzb2/ocL4PbwWHMruUpLC5/evsWlQTctwpq+Y75WL1 sW2+bdyiL8NvWTN/0rDEZsO/SQMMkY34JZG1NzaWAMH+ZipGLUUz1QUUbXnoA+6+MhBA byOCWEhriioC52iXCUqoLHWIF50w65+q13uEYHFAO++aMsIKTqs6OIjbYo/dud01/Zht p9mSmbSWgh0D/jC5AxtT7WX5/WJyuiCprSbTKSLrvacWK8ZT00/O+R4nJpQt/RgcGYRH qpfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zYdB1K1D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/15] target/arm: Fold regime_tcr() and regime_tcr_value() together Date: Mon, 18 Jul 2022 14:59:12 +0100 Message-Id: <20220718135920.13667-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The only caller of regime_tcr() is now regime_tcr_value(); fold the two together, and use the shorter and more natural 'regime_tcr' name for the new function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-4-peter.maydell@linaro.org --- target/arm/internals.h | 16 +++++----------- target/arm/helper.c | 6 +++--- target/arm/ptw.c | 6 +++--- target/arm/tlb_helper.c | 2 +- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fa046124fa8..0a1eb20afce 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -777,26 +777,20 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; } -/* Return the TCR controlling this translation regime */ -static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) +/* Return the value of the TCR controlling this translation regime */ +static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { if (mmu_idx == ARMMMUIdx_Stage2) { - return &env->cp15.vtcr_el2; + return env->cp15.vtcr_el2.raw_tcr; } if (mmu_idx == ARMMMUIdx_Stage2_S) { /* * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but * those are not currently used by QEMU, so just return VSTCR_EL2. */ - return &env->cp15.vstcr_el2; + return env->cp15.vstcr_el2.raw_tcr; } - return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; -} - -/* Return the raw value of the TCR controlling this translation regime */ -static inline uint64_t regime_tcr_value(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return regime_tcr(env, mmu_idx)->raw_tcr; + return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; } /** diff --git a/target/arm/helper.c b/target/arm/helper.c index c245922bb5d..8847f5b90ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4216,7 +4216,7 @@ static int vae1_tlbmask(CPUARMState *env) static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) { - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); int select = extract64(addr, 55, 1); @@ -10158,7 +10158,7 @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); bool epd, hpd, using16k, using64k, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu = env_archcpu(env); @@ -10849,7 +10849,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, { CPUARMTBFlags flags = {}; ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); uint64_t sctlr; int tbii, tbid; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 16226d14233..e9959848d88 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -315,7 +315,7 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); int maskshift = extract32(tcr, 0, 3); uint32_t mask = ~(((uint32_t)0xffffffffu) >> maskshift); uint32_t base_mask; @@ -824,7 +824,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); uint32_t el = regime_el(env, mmu_idx); int select, tsz; bool epd, hpd; @@ -998,7 +998,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, uint32_t attrs; int32_t stride; int addrsize, inputsize, outputsize; - uint64_t tcr = regime_tcr_value(env, mmu_idx); + uint64_t tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); uint64_t descaddrmask; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index a2f87a5042d..5a709eab56f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -20,7 +20,7 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) return true; } if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr_value(env, mmu_idx) & TTBCR_EAE)) { + && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { return true; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/15] target/arm: Fix big-endian host handling of VTCR Date: Mon, 18 Jul 2022 14:59:13 +0100 Message-Id: <20220718135920.13667-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have a bug in our handling of accesses to the AArch32 VTCR register on big-endian hosts: we were not adjusting the part of the uint64_t field within TCR that the generated code would access. That can be done with offsetoflow32(), by using an ARM_CP_STATE_BOTH cpreg struct, or by defining a full set of read/write/reset functions -- the various other TCR cpreg structs used one or another of those strategies, but for VTCR we did not, so on a big-endian host VTCR accesses would touch the wrong half of the register. Use offsetoflow32() in the VTCR register struct. This works even though the field in the CPU struct is currently a struct TCR, because the first field in that struct is the uint64_t raw_tcr. None of the other TCR registers have this bug -- either they are AArch64 only, or else they define resetfn, writefn, etc, and expect to be passed the full struct pointer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-5-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8847f5b90ad..7461d4091ef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5409,7 +5409,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .type = ARM_CP_ALIAS, .access = PL2_RW, .accessfn = access_el3_aa32ns, - .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, + .fieldoffset = offsetoflow32(CPUARMState, cp15.vtcr_el2) }, { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .access = PL2_RW, From patchwork Mon Jul 18 13:59:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591462 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3058521max; Mon, 18 Jul 2022 07:25:47 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tvmAt9iwVvS51f8GyjB9mOXzEa+w5Njhr5DAeuKs9+1rHTG7XpvrsxyT5TTZIHvBEHF9KU X-Received: by 2002:a05:620a:44c9:b0:6b2:1f49:f0f5 with SMTP id y9-20020a05620a44c900b006b21f49f0f5mr17292317qkp.327.1658154347047; Mon, 18 Jul 2022 07:25:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154347; cv=none; d=google.com; s=arc-20160816; b=tOHt4xDS+LRY/v9xhetkqKTt+fyLH+Kb/jeTCc+eqqPnSUz2OgmdCb8JXpJZB5G+xl DbM2jR/ptLCUexS0olK+/73v9B9oIq2EShBUZ7Tvwiiq7cH/x/L7fjKpQWC2hWPVGDwf fSzHBu20Gv3oADAntBWJ30rCSRkqU9kDut9mv/UmLQCn0rfOsBxpdAIoB6veVeRbOAP1 uUp8icoAmkRH0tU8w2O3MfX7KV0q4y/cwJlRSCNaGQwnZWGmoZhdI88qy1ztwwlNBHIY kaotH//o1z3FfHPvxsgGuFp2jloQ5JndIsfsLsArMG6/NI8o8CL3C8eK5jiM4wYWRCio CFnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=S9521uPJSfVMIBW00AoA0V1zvlCEYyKqf8sTNG4dyxo=; b=Aw6D0UWlSWpvz0ujPohyWP1kavWLfdKjEwRAl0eerUaoJRZWQgnDOZsVVAwUetCHY3 vrsK6ll7dNh5VVJMA6+1QaYOw+0SQEmnP9jqSNG5qiN5/eIimPVyFB6CVC4Mc5H328yO EpcO3mRvXpRXmSgWN2zk+xYoA85tLBptL8OAs8/LPoCwhUCwdTIWPf6eVSkundYu32+P nhyM3h8JWlMmov8VwbGwpopQh59nhYFkrarEmh4PuR8Nrm//EagDVPFfXd7ei5YZ9DOB f66ZhqHFu3Z/U5+kWGtaqNucmClsSmP2CdIgjFuBIBHL9tGGNsroCxEhP4PUO4Tz3MFd t/qA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="gwkSvpR/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/15] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t Date: Mon, 18 Jul 2022 14:59:14 +0100 Message-Id: <20220718135920.13667-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change the representation of the VSTCR_EL2 and VTCR_EL2 registers in the CPU state struct from struct TCR to uint64_t. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-6-peter.maydell@linaro.org --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 4 ++-- target/arm/helper.c | 4 +--- target/arm/ptw.c | 14 +++++++------- 4 files changed, 12 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6afcc882f2c..b14c7c3eec3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -340,8 +340,8 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ TCR tcr_el[4]; - TCR vtcr_el2; /* Virtualization Translation Control. */ - TCR vstcr_el2; /* Secure Virtualization Translation Control. */ + uint64_t vtcr_el2; /* Virtualization Translation Control. */ + uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register diff --git a/target/arm/internals.h b/target/arm/internals.h index 0a1eb20afce..9f654b12cea 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -781,14 +781,14 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { if (mmu_idx == ARMMMUIdx_Stage2) { - return env->cp15.vtcr_el2.raw_tcr; + return env->cp15.vtcr_el2; } if (mmu_idx == ARMMMUIdx_Stage2_S) { /* * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but * those are not currently used by QEMU, so just return VSTCR_EL2. */ - return env->cp15.vstcr_el2.raw_tcr; + return env->cp15.vstcr_el2; } return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 7461d4091ef..ea541e4b0c9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5413,9 +5413,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .access = PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + /* no .writefn needed as this can't cause an ASID change */ .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, { .name = "VTTBR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 6, .crm = 2, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e9959848d88..8049c67f039 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -241,9 +241,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, if (arm_is_secure_below_el3(env)) { /* Check if page table walk is to secure or non-secure PA space. */ if (*is_secure) { - *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + *is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + *is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); } } else { assert(!*is_secure); @@ -2341,9 +2341,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ipa_secure = attrs->secure; if (arm_is_secure_below_el3(env)) { if (ipa_secure) { - attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + attrs->secure = !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + attrs->secure = !(env->cp15.vtcr_el2 & VTCR_NSW); } } else { assert(!ipa_secure); @@ -2385,11 +2385,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, if (arm_is_secure_below_el3(env)) { if (ipa_secure) { attrs->secure = - !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); } else { attrs->secure = - !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) - || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); + !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) + || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); } } return 0; From patchwork Mon Jul 18 13:59:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591464 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3058585max; Mon, 18 Jul 2022 07:25:51 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uMWUdicvpeFAleHNVyquKOGkMLhDagcjYDi0NKQL10ObycOmy90Cdu7l9F3QkA1DDrSZrK X-Received: by 2002:a05:620a:2453:b0:6af:6f18:b432 with SMTP id h19-20020a05620a245300b006af6f18b432mr17809027qkn.54.1658154351765; Mon, 18 Jul 2022 07:25:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154351; cv=none; d=google.com; s=arc-20160816; b=ewhCVJ8HAn/Gv61rn+V+r8ovwuww6BBZZ16MWt+Y653bemOSFfOXqTGoqpKialr8gV Ivdg6EMrd4rFlITlLf5pwKH4nW8bfAX/oFX6EndhRx68ioUd7Mh5myeEGPrAMXCQ9lhK aYDcbNqNvSpqUlXnW0A7HO9WBSdLk1G+AlmYFExQpzSZtRPXdcLliseeVIMOfCS5z2jU zZii+FxiRy+jAtNVCW0vh6w2gwZ7H94hv1fGnjUn9doRujBDeJnDd1M/HDOw0RB8PgJY AYOAs9sdTjRD3lsgF4MrjjBsr4I93gmDZPYBOKq/d8tn75NzIVdhfDxIu8UjfgAmhV0e w+dQ== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t Date: Mon, 18 Jul 2022 14:59:15 +0100 Message-Id: <20220718135920.13667-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change the representation of the TCR_EL* registers in the CPU state struct from struct TCR to uint64_t. This allows us to drop the custom vmsa_ttbcr_raw_write() function, moving the "enforce RES0" checks to their more usual location in the writefn vmsa_ttbcr_write(). We also don't need the resetfn any more. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-7-peter.maydell@linaro.org --- target/arm/cpu.h | 8 +---- target/arm/internals.h | 6 ++-- target/arm/cpu.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/helper.c | 75 +++++++++++---------------------------- target/arm/ptw.c | 2 +- 6 files changed, 27 insertions(+), 68 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b14c7c3eec3..b43083c5ef5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -166,12 +166,6 @@ typedef struct ARMGenericTimer { #define GTIMER_HYPVIRT 4 #define NUM_GTIMERS 5 -typedef struct { - uint64_t raw_tcr; - uint32_t mask; - uint32_t base_mask; -} TCR; - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW @@ -339,7 +333,7 @@ typedef struct CPUArchState { uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ - TCR tcr_el[4]; + uint64_t tcr_el[4]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 9f654b12cea..742135ef146 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -252,9 +252,9 @@ unsigned int arm_pamax(ARMCPU *cpu); */ static inline bool extended_addresses_enabled(CPUARMState *env) { - TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; + uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; return arm_el_is_aa64(env, 1) || - (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); + (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE)); } /* Update a QEMU watchpoint based on the information the guest has set in the @@ -790,7 +790,7 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) */ return env->cp15.vstcr_el2; } - return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; + return env->cp15.tcr_el[regime_el(env, mmu_idx)]; } /** diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5de7e097e9b..1b7b3d76bb3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -226,7 +226,7 @@ static void arm_cpu_reset(DeviceState *dev) * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); + env->cp15.tcr_el[1] = 5 | (1ULL << 37); /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index d09fccb0a4f..c21739242c5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -439,7 +439,7 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env) using_lpae = true; } else { if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { using_lpae = true; } } diff --git a/target/arm/helper.c b/target/arm/helper.c index ea541e4b0c9..1a8b06410e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3606,19 +3606,21 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, }; -static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - TCR *tcr = raw_ptr(env, ri); - int maskshift = extract32(value, 0, 3); + ARMCPU *cpu = env_archcpu(env); if (!arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { - /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when - * using Long-desciptor translation table format */ + /* + * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when + * using Long-descriptor translation table format + */ value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); } else if (arm_feature(env, ARM_FEATURE_EL3)) { - /* In an implementation that includes the Security Extensions + /* + * In an implementation that includes the Security Extensions * TTBCR has additional fields PD0 [4] and PD1 [5] for * Short-descriptor translation table format. */ @@ -3628,55 +3630,23 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, } } - /* Update the masks corresponding to the TCR bank being written - * Note that we always calculate mask and base_mask, but - * they are only used for short-descriptor tables (ie if EAE is 0); - * for long-descriptor tables the TCR fields are used differently - * and the mask and base_mask values are meaningless. - */ - tcr->raw_tcr = value; - tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); - tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); -} - -static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu = env_archcpu(env); - TCR *tcr = raw_ptr(env, ri); - if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ tlb_flush(CPU(cpu)); } - /* Preserve the high half of TCR_EL1, set via TTBCR2. */ - value = deposit64(tcr->raw_tcr, 0, 32, value); - vmsa_ttbcr_raw_write(env, ri, value); -} - -static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - TCR *tcr = raw_ptr(env, ri); - - /* Reset both the TCR as well as the masks corresponding to the bank of - * the TCR being reset. - */ - tcr->raw_tcr = 0; - tcr->mask = 0; - tcr->base_mask = 0xffffc000u; + raw_write(env, ri, value); } static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); - TCR *tcr = raw_ptr(env, ri); /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ tlb_flush(CPU(cpu)); - tcr->raw_tcr = value; + raw_write(env, ri, value); } static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3780,15 +3750,15 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tvm_trvm, .writefn = vmsa_tcr_el12_write, - .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, + .raw_writefn = raw_write, + .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, - .raw_writefn = vmsa_ttbcr_raw_write, - /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ - .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), - offsetof(CPUARMState, cp15.tcr_el[1])} }, + .raw_writefn = raw_write, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), + offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, }; /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing @@ -3799,8 +3769,8 @@ static const ARMCPRegInfo ttbcr2_reginfo = { .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, .bank_fieldoffsets = { - offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), - offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), + offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]), }, }; @@ -5403,7 +5373,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .writefn = vmsa_tcr_el12_write, - /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */ .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name = "VTCR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, @@ -5643,12 +5612,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, .access = PL3_RW, - /* no .writefn needed as this can't cause an ASID change; - * we must provide a .raw_writefn and .resetfn because we handle - * reset and migration for the AArch32 TTBCR(S), which might be - * using mask and base_mask. - */ - .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, + /* no .writefn needed as this can't cause an ASID change */ + .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8049c67f039..3261039d93a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2466,7 +2466,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, int r_el = regime_el(env, mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax = arm_pamax(env_archcpu(env)); - uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; + uint64_t tcr = env->cp15.tcr_el[r_el]; int addrtop, tbi; tbi = aa64_va_parameter_tbi(tcr, mmu_idx); From patchwork Mon Jul 18 13:59:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591467 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3061188max; 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[209.51.188.17]) by mx.google.com with ESMTPS id d7-20020a05620a240700b006b5e8231b9asi1565938qkn.410.2022.07.18.07.28.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jul 2022 07:28:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X9f206kE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRk2-00073E-Pf for patch@linaro.org; Mon, 18 Jul 2022 10:28:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHe-00029Q-43 for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:38 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:52208) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHZ-0003B8-OH for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:36 -0400 Received: by mail-wm1-x329.google.com with SMTP id id17so97980wmb.1 for ; Mon, 18 Jul 2022 06:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eukvC+6HlCYJEnDc50zk+LTUKV0cWVgf+mK6xiITMuE=; b=X9f206kEoBpc4fjMTey1P0v2URTVdccCh80ZKxCmHcagJBKz4E9NEHUdKkTi6V2Raa 7mMaX8flonuBktLHZMsGuK7c7TRO3xQ9Ns+kpgoO91E0iwDCojQaRlqZSpoWKt43CMBm 2xPj1ij9OWilzOPf0re1Ca9ZRiyOl0tQsrFYH8qXzy0Kes17MfH9lId5+VATaeJoa7ZP 6m7uA+2kQmULmDic8JnnWv6H8WA/KWWEraHfD7G1ou78rKJlUUeuFXD/sxfZHTx6HXg5 dJJM8/tAW14DO6sOke1/UQY8Bmnvf3bdJ3BJqT065Jri14u+V7bN29JPzNgcM+LxVhbI viMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eukvC+6HlCYJEnDc50zk+LTUKV0cWVgf+mK6xiITMuE=; b=aTRTfgqFwjkycRp0+wlj1Zxm1TJKDo3c1Ej9h1GcmmeV9aNRRGgR55tOk3MOvIdxfq 8gTP5jk93Xe0srXq5GMyVmrLG6o4LoWoOGs5lLFBg1bBX4rVeyUTd0zNL8BY0shRK/hb qDwK0AmRqaY0Gej4ijRuxF4Bbkm/l+pi66fow5DWVMBHGiGMvAOgZiA6iM+67n/mjaq0 IWf8e8etfnNSQCo+eo4mXq4b9I93iN3R04oT5Or5RPZTTPJ7DwbLodLnnjVkXoZ7OJZ5 NVF7sSwKdcCD/yoOZADuNlDfC0g+/z9vTnq6dgmvWtQbYD2dnUsmLliAEg+29VMsbDGc X7WQ== X-Gm-Message-State: AJIora8uoNAwZICLYO+Y0LNtNYq3ekmLgq0nI+f69gYEB3A+rGFoc7KR pw7m1DKn1tCFfjbAxbzPdNz3UIdtouTe3A== X-Received: by 2002:a05:600c:3ca2:b0:3a0:1825:2e6b with SMTP id bg34-20020a05600c3ca200b003a018252e6bmr31858625wmb.132.1658152772151; Mon, 18 Jul 2022 06:59:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/15] target/arm: Honour VTCR_EL2 bits in Secure EL2 Date: Mon, 18 Jul 2022 14:59:16 +0100 Message-Id: <20220718135920.13667-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In regime_tcr() we return the appropriate TCR register for the translation regime. For Secure EL2, we return the VSTCR_EL2 value, but in this translation regime some fields that control behaviour are in VTCR_EL2. When this code was originally written (as the comment notes), QEMU didn't care about any of those fields, but we have since added support for features such as LPA2 which do need the values from those fields. Synthesize a TCR value by merging in the relevant VTCR_EL2 fields to the VSTCR_EL2 value. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1103 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-8-peter.maydell@linaro.org --- target/arm/cpu.h | 19 +++++++++++++++++++ target/arm/internals.h | 22 +++++++++++++++++++--- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b43083c5ef5..e890ee074d3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1412,6 +1412,25 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define TTBCR_SH1 (1U << 28) #define TTBCR_EAE (1U << 31) +FIELD(VTCR, T0SZ, 0, 6) +FIELD(VTCR, SL0, 6, 2) +FIELD(VTCR, IRGN0, 8, 2) +FIELD(VTCR, ORGN0, 10, 2) +FIELD(VTCR, SH0, 12, 2) +FIELD(VTCR, TG0, 14, 2) +FIELD(VTCR, PS, 16, 3) +FIELD(VTCR, VS, 19, 1) +FIELD(VTCR, HA, 21, 1) +FIELD(VTCR, HD, 22, 1) +FIELD(VTCR, HWU59, 25, 1) +FIELD(VTCR, HWU60, 26, 1) +FIELD(VTCR, HWU61, 27, 1) +FIELD(VTCR, HWU62, 28, 1) +FIELD(VTCR, NSW, 29, 1) +FIELD(VTCR, NSA, 30, 1) +FIELD(VTCR, DS, 32, 1) +FIELD(VTCR, SL2, 33, 1) + /* Bit definitions for ARMv8 SPSR (PSTATE) format. * Only these are valid when in AArch64 mode; in * AArch32 mode SPSRs are basically CPSR-format. diff --git a/target/arm/internals.h b/target/arm/internals.h index 742135ef146..b8fefdff675 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -777,6 +777,16 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; } +/* + * These are the fields in VTCR_EL2 which affect both the Secure stage 2 + * and the Non-Secure stage 2 translation regimes (and hence which are + * not present in VSTCR_EL2). + */ +#define VTCR_SHARED_FIELD_MASK \ + (R_VTCR_IRGN0_MASK | R_VTCR_ORGN0_MASK | R_VTCR_SH0_MASK | \ + R_VTCR_PS_MASK | R_VTCR_VS_MASK | R_VTCR_HA_MASK | R_VTCR_HD_MASK | \ + R_VTCR_DS_MASK) + /* Return the value of the TCR controlling this translation regime */ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -785,10 +795,16 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) } if (mmu_idx == ARMMMUIdx_Stage2_S) { /* - * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but - * those are not currently used by QEMU, so just return VSTCR_EL2. + * Secure stage 2 shares fields from VTCR_EL2. We merge those + * in with the VSTCR_EL2 value to synthesize a single VTCR_EL2 format + * value so the callers don't need to special case this. + * + * If a future architecture change defines bits in VSTCR_EL2 that + * overlap with these VTCR_EL2 fields we may need to revisit this. */ - return env->cp15.vstcr_el2; + uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK; + v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; + return v; } return env->cp15.tcr_el[regime_el(env, mmu_idx)]; } From patchwork Mon Jul 18 13:59:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591468 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3061363max; Mon, 18 Jul 2022 07:29:13 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tZZzxsKCzW4xtwBvBk2aXRlbQXWJQ7N2Z4z3vkLbHQqYrDWVSvMaNjRResf974c3kCkakD X-Received: by 2002:a05:622a:1046:b0:31e:f51f:97ce with SMTP id f6-20020a05622a104600b0031ef51f97cemr2011589qte.315.1658154553093; Mon, 18 Jul 2022 07:29:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154553; cv=none; d=google.com; s=arc-20160816; b=gKJcyYZUrkw2r5oqSfdZ9sFYymyJUIa3x2OpwtEIOl7a2Aoe2xndcE0k0PsCgyRq10 KilKLzLZtmq1D2BSU3PWbCUy/ddOXV/8OKX/88U6WIiJwN05tTREVuXlWepL/xJNDiHR WL7fPdeZtoXcMPaK3R0SJxDUonMXPO5B9jsq5qh4STpUrWblO/idbX+CuJfIfyklu/vF G8JkQIu1mrnLnB1nMab5ds0/A4o2/2vcXrGpQFcO/4R5YE5oPlHsMgHi+rxVFiUtKliV W2XB2ZwOpFHKfE4/83NiH1Sm0+0/5/vjRnjRrLjjyAdGoO51+QF2TujxCRhI8/9BovXW 42dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bsiTbIieXoyZzsovMov20+PKkWbaKl/whztxxrpGPA0=; b=yBXv/ylMuI1yJ5YmbSAP014+d2ZxnG81BGZSzCh7mfs7t74OzDn3urccbb+/ULEGM4 A2o9gWVUVNzdTVcKpzAPDoZfiyu9Bc2g+X87nlUK2lsoZTyuulZx0rZu8sGDtAK5Zlay TMItH5mM/UTzFcelAg8RVNXM2Su5oyKIhCv0aMAU53Lt9W1yZp8fC1yJ9DbPWy+Nvjk+ zjdV+RknzV6Sq1P/Qo5qFNWdYLyQYx2haagc+MHYim6BicrqOdGQG9VRUekG12dQqXqw EnXtdYeumrOVJz67gENlItzaYEvGlelUmdmdwJIMCeJ0o6hxaQuVIqc09rHBm6tp857+ fr5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GCEzTYqe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register Date: Mon, 18 Jul 2022 14:59:17 +0100 Message-Id: <20220718135920.13667-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Hao Wu The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch fixes that in the module, and also lower the IRQ when the guest is done handling an interrupt event from the ADC module. Signed-off-by: Hao Wu Reviewed-by: Patrick Venture Reviewed-by: Peter Maydell Message-id: 20220714182836.89602-4-wuhaotsh@google.com Signed-off-by: Peter Maydell --- hw/adc/npcm7xx_adc.c | 2 +- tests/qtest/npcm7xx_adc-test.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index 0f0a9f63e20..47fb9e5f74c 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -36,7 +36,7 @@ REG32(NPCM7XX_ADC_DATA, 0x4) #define NPCM7XX_ADC_CON_INT BIT(18) #define NPCM7XX_ADC_CON_EN BIT(17) #define NPCM7XX_ADC_CON_RST BIT(16) -#define NPCM7XX_ADC_CON_CONV BIT(14) +#define NPCM7XX_ADC_CON_CONV BIT(13) #define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) #define NPCM7XX_ADC_MAX_RESULT 1023 diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c index 3fa6d9ece0b..8048044d281 100644 --- a/tests/qtest/npcm7xx_adc-test.c +++ b/tests/qtest/npcm7xx_adc-test.c @@ -50,7 +50,7 @@ #define CON_INT BIT(18) #define CON_EN BIT(17) #define CON_RST BIT(16) -#define CON_CONV BIT(14) +#define CON_CONV BIT(13) #define CON_DIV(rv) extract32(rv, 1, 8) #define FST_RDST BIT(1) From patchwork Mon Jul 18 13:59:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591471 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3066145max; Mon, 18 Jul 2022 07:34:29 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tkaSoxuxPRg2WFejtdnMWYXkkJZ6xZAfHvT7P+LRgGY53oazHi7EeHjhkKDqcIzVpGQO7Q X-Received: by 2002:a05:620a:2181:b0:6b5:e0a3:21a9 with SMTP id g1-20020a05620a218100b006b5e0a321a9mr5541631qka.388.1658154869666; Mon, 18 Jul 2022 07:34:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154869; cv=none; d=google.com; s=arc-20160816; b=ZQNVQ8hcKzqQqAm2K7PCyUMI+kclypIEset9pNKhCsSrhKyKIMhF9ql2SEP6FWxl7O yZzb9h12Oj7L+MyziMK11C4eXSMUPk0fRynHVLGdvtW8RtFjE0AAJsTON4IbTWxzpyMr teK0NHjpnhEA9cV8JW6Um5SvOpEHalng8/SqARC+/G/rFyoony7zyCqIzB/aUJIyMixh rPXZVr78Xxnwcr4M7MkR/9+uEvk7GLn0nJQQYUnH0w4IYY4rDMQOC2SyQfbQxrHslB/o a+4ORwRmh7uO2OiNxyxw39XUWHjzOS9Z2U3e8LL9ZBixJmcI3nG9D9Hwqn/YmLrz9kJZ qpjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WLcuE5tjCtEqKCJRkl1tlMmWsSxVcZNfqF25uGydMws=; b=IxU5G5kqAHfmy5bgBhpd8EB2GfReuay4AZjQN3vnQEPdRjJXuipc8RNgU/lIlEwX+B Yx6gILwkJYtnkwIUN5lUFtrEljKn9ii1VClAm8u+TJ+pMJmaR210Qazum7ubCD+kTFwq T5nMs65c5KnODbM/nGxcQMm/pP5LpMnSZM1+AeTYzxrEKK10hyiDOjUcE4NkEvgNSh1G s8lgt8XSNSBKPCzd3TfN2R/SH4q1uAZTn985zhaDaQepvvHyqv+Ca0L69LRkJX34sOjn h9o9NDlbXdmx8Ee4VyjUma2O0vDRgAjUnsXjr+F+JTMJnMBwGiTAiS1ZfZJIM62jT0q/ OFCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fYKyNHXS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/15] hw/adc: Make adci[*] R/W in NPCM7XX ADC Date: Mon, 18 Jul 2022 14:59:18 +0100 Message-Id: <20220718135920.13667-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Hao Wu Our sensor test requires both reading and writing from a sensor's QOM property. So we need to make the input of ADC module R/W instead of write only for that to work. Signed-off-by: Hao Wu Reviewed-by: Titus Rwantare Reviewed-by: Peter Maydell Message-id: 20220714182836.89602-5-wuhaotsh@google.com Signed-off-by: Peter Maydell --- hw/adc/npcm7xx_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index 47fb9e5f74c..bc6f3f55e64 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -242,7 +242,7 @@ static void npcm7xx_adc_init(Object *obj) for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { object_property_add_uint32_ptr(obj, "adci[*]", - &s->adci[i], OBJ_PROP_FLAG_WRITE); + &s->adci[i], OBJ_PROP_FLAG_READWRITE); } object_property_add_uint32_ptr(obj, "vref", &s->vref, OBJ_PROP_FLAG_WRITE); From patchwork Mon Jul 18 13:59:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591470 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3063333max; Mon, 18 Jul 2022 07:31:26 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vi3qIwyEFIJKcXENNWXR+4ScEr/0+YgBomd+wAa99htvfiL9cqQb72I3U0Qxe/NVeoiE/S X-Received: by 2002:a05:620a:254e:b0:6b4:8dd1:e4b6 with SMTP id s14-20020a05620a254e00b006b48dd1e4b6mr18498097qko.39.1658154686359; Mon, 18 Jul 2022 07:31:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154686; cv=none; d=google.com; s=arc-20160816; b=Uz0Ah11gRdcLMnNOpaarxSOEVE/xBTvs1KDUp38Ti33swLMGBUATLpG6pkSclBA7/M 3da6Nx5UKtUggs8Ik3YBnR8htXl+u56aqs881ktiHssv9JWCN3O/2ITxu8n8IwHjm34O iGbuYNIRk0ZSHal78nBY+UUCG4vkqu/sn6ytx5jt6NeB/RSzShqJMH5CzqbrP9bXD3zX l3HY0yIo/gj/CmVzpvuME7BYgpZ0XoFvwis5LFYmN+XzXhyL7SHClcemD2FJ9luL8pci 0OxkkDRtyl7mEjKgVdLmyCFRCCiEYwwSAv/42vv13vmDd/LcjJwqZENC3mrhkeOVJ866 /1Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QuX4bqrgJsmwtriilRgKBMrcdhU6Sl9wuLdDCeKIqPA=; b=r1iNmT4+Uicu8oeKkh84xFBFimO4CNOQpwTyaJ5JgCvGU9HFq26bt9/959f8gasCM0 5aV19ww61i0HpqHh6B0r9ebcjXhXdV0c5C+cXcqoXwy435InrO0u7WRDuvxA2lQFyhHa b3KXJfLXYtOp0SFvdgwlqPXxi6PkpqRFiBj7x0wQDQO+WUSjIt+flf6oiItTMgKx7aMC mF6OGXUls6eSbpdrmURsWuzyz+rI1CjURt61BhaIJNdSSj2gXOZz6rgzrw3NyHiH6Xlo ikVqFVWm9NOM83vHBjYBVvxg7YmNCkXgz5WPCgOPGd30gYKLJmTXssB1FvKlemkR/s+h zZHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yeo4kAbg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores with writeback Date: Mon, 18 Jul 2022 14:59:19 +0100 Message-Id: <20220718135920.13667-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The architecture requires that for faults on loads and stores which do writeback, the syndrome information does not have the ISS instruction syndrome information (i.e. ISV is 0). We got this wrong for the load and store instructions covered by disas_ldst_reg_imm9(). Calculate iss_valid correctly so that if the insn is a writeback one it is false. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220715123323.1550983-1-peter.maydell@linaro.org --- target/arm/translate-a64.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7b64f73584..163df8c6157 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3138,7 +3138,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, bool is_store = false; bool is_extended = false; bool is_unpriv = (idx == 2); - bool iss_valid = !is_vector; + bool iss_valid; bool post_index; bool writeback; int memidx; @@ -3191,6 +3191,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, g_assert_not_reached(); } + iss_valid = !is_vector && !writeback; + if (rn == 31) { gen_check_sp_alignment(s); } From patchwork Mon Jul 18 13:59:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 591472 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp3066207max; Mon, 18 Jul 2022 07:34:33 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sYgeMs0yHA2rEv8fSb7rt8WjMSLjldNVEFpUEdWOOnAvw2l0ulnESBd22E60bvBzXzH+o1 X-Received: by 2002:a37:644b:0:b0:6b5:d62f:7ed with SMTP id y72-20020a37644b000000b006b5d62f07edmr8171337qkb.143.1658154873341; Mon, 18 Jul 2022 07:34:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658154873; cv=none; d=google.com; s=arc-20160816; b=pBH3lthXXm3ja0UQoq1ByJKnF6OBU0ccivExp0GVE3osD5k2vNX3dHZoKcYFU9uvxT JQk5zhj3hpAjkfA2bMwgmr1NsI2ynA65rGr1kJa1FHOb/zXGJQFRDUiiK7gtZZ8dAWAt wdwAc7LiGk61Xm+iE8+sqjo+UmEeSx+DlHzgfAcXvwmbULUSg6XagRdW6gJO/a45VZdF kv6eUv/Zcb9LZDEyKX9I58DjO7HgXIbIZZeVpC22bsvv3wqdCFEZTWLFG/NTmRiuyCcn Y2QWDd0ltct0OS4e4PzSb/BqD48+0CnGVgyIO/4DC/5pZr2cY9HyPGhqIPyRTiGRBEyo gTVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=O9MWcMSwBbu4CMzo7bCb2HSbS/5shVLaXo9ftmPe+ww=; b=t+feWJfdPvjcAfnza/p+2Gmm8oRkRQippuxVUpAgLdHCi1yUAL93V968J4eot5i/T6 NEgiGUoveMJ5eyK5Laz1CgMQAGWj8er7v3NhVX6jQPFR0yukoW+OeXn2UQpvFada3OH8 0y6hQsZCvS5Ld76vrMc53zJIOrVvX+MJUso4kW1V12/835VeTjZ3T35r1aOw45IRlmx4 blV+kxjYtNreYD89ta9IpKTS8Z80I0xkPYT/e0oW+skwHZOANkvy8DYhpMeKhxpKIo9u wz77a+F+yIx/VGAJ8Duk09wgtpoyk1imKYnDStrT9fs799HmmBmeyUEagWClidxeFPW1 lBJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HeyTXnKy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/15] Align Raspberry Pi DMA interrupts with Linux DTS Date: Mon, 18 Jul 2022 14:59:20 +0100 Message-Id: <20220718135920.13667-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrey Makarov There is nothing in the specs on DMA engine interrupt lines: it should have been in the "BCM2835 ARM Peripherals" datasheet but the appropriate "ARM peripherals interrupt table" (p.113) is nearly empty. All Raspberry Pi models 1-3 (based on bcm2835) have Linux device tree (arch/arm/boot/dts/bcm2835-common.dtsi +25): /* dma channel 11-14 share one irq */ This information is repeated in the driver code (drivers/dma/bcm2835-dma.c +1344): /* * in case of channel >= 11 * use the 11th interrupt and that is shared */ In this patch channels 0--10 and 11--14 are handled separately. Signed-off-by: Andrey Makarov Message-id: 20220716113210.349153-1-andrey.makarov@auriga.com [PMM: fixed checkpatch nits] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/bcm2835_peripherals.h | 2 + hw/arm/bcm2835_peripherals.c | 26 +++++- tests/qtest/bcm2835-dma-test.c | 118 +++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 4 files changed, 147 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/bcm2835-dma-test.c diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h index d864879421a..c9d25d493e0 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -17,6 +17,7 @@ #include "hw/char/bcm2835_aux.h" #include "hw/display/bcm2835_fb.h" #include "hw/dma/bcm2835_dma.h" +#include "hw/or-irq.h" #include "hw/intc/bcm2835_ic.h" #include "hw/misc/bcm2835_property.h" #include "hw/misc/bcm2835_rng.h" @@ -55,6 +56,7 @@ struct BCM2835PeripheralState { BCM2835AuxState aux; BCM2835FBState fb; BCM2835DMAState dma; + qemu_or_irq orgated_dma_irq; BCM2835ICState ic; BCM2835PropertyState property; BCM2835RngState rng; diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 48538c9360c..3c2a4160cd1 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -23,6 +23,13 @@ /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ #define BCM2835_SDHC_CAPAREG 0x52134b4 +/* + * According to Linux driver & DTS, dma channels 0--10 have separate IRQ, + * while channels 11--14 share one IRQ: + */ +#define SEPARATE_DMA_IRQ_MAX 10 +#define ORGATED_DMA_IRQ_COUNT 4 + static void create_unimp(BCM2835PeripheralState *ps, UnimplementedDeviceState *uds, const char *name, hwaddr ofs, hwaddr size) @@ -101,6 +108,11 @@ static void bcm2835_peripherals_init(Object *obj) /* DMA Channels */ object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA); + object_initialize_child(obj, "orgated-dma-irq", + &s->orgated_dma_irq, TYPE_OR_IRQ); + object_property_set_int(OBJECT(&s->orgated_dma_irq), "num-lines", + ORGATED_DMA_IRQ_COUNT, &error_abort); + object_property_add_const_link(OBJECT(&s->dma), "dma-mr", OBJECT(&s->gpu_bus_mr)); @@ -322,12 +334,24 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); - for (n = 0; n <= 12; n++) { + for (n = 0; n <= SEPARATE_DMA_IRQ_MAX; n++) { sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA0 + n)); } + if (!qdev_realize(DEVICE(&s->orgated_dma_irq), NULL, errp)) { + return; + } + for (n = 0; n < ORGATED_DMA_IRQ_COUNT; n++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), + SEPARATE_DMA_IRQ_MAX + 1 + n, + qdev_get_gpio_in(DEVICE(&s->orgated_dma_irq), n)); + } + qdev_connect_gpio_out(DEVICE(&s->orgated_dma_irq), 0, + qdev_get_gpio_in_named(DEVICE(&s->ic), + BCM2835_IC_GPU_IRQ, + INTERRUPT_DMA0 + SEPARATE_DMA_IRQ_MAX + 1)); /* THERMAL */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->thermal), errp)) { diff --git a/tests/qtest/bcm2835-dma-test.c b/tests/qtest/bcm2835-dma-test.c new file mode 100644 index 00000000000..8293d822b94 --- /dev/null +++ b/tests/qtest/bcm2835-dma-test.c @@ -0,0 +1,118 @@ +/* + * QTest testcase for BCM283x DMA engine (on Raspberry Pi 3) + * and its interrupts coming to Interrupt Controller. + * + * Copyright (c) 2022 Auriga LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* Offsets in raspi3b platform: */ +#define RASPI3_DMA_BASE 0x3f007000 +#define RASPI3_IC_BASE 0x3f00b200 + +/* Used register/fields definitions */ + +/* DMA engine registers: */ +#define BCM2708_DMA_CS 0 +#define BCM2708_DMA_ACTIVE (1 << 0) +#define BCM2708_DMA_INT (1 << 2) + +#define BCM2708_DMA_ADDR 0x04 + +#define BCM2708_DMA_INT_STATUS 0xfe0 + +/* DMA Trasfer Info fields: */ +#define BCM2708_DMA_INT_EN (1 << 0) +#define BCM2708_DMA_D_INC (1 << 4) +#define BCM2708_DMA_S_INC (1 << 8) + +/* Interrupt controller registers: */ +#define IRQ_PENDING_BASIC 0x00 +#define IRQ_GPU_PENDING1_AGGR (1 << 8) +#define IRQ_PENDING_1 0x04 +#define IRQ_ENABLE_1 0x10 + +/* Data for the test: */ +#define SCB_ADDR 256 +#define S_ADDR 32 +#define D_ADDR 64 +#define TXFR_LEN 32 +const uint32_t check_data = 0x12345678; + +static void bcm2835_dma_test_interrupt(int dma_c, int irq_line) +{ + uint64_t dma_base = RASPI3_DMA_BASE + dma_c * 0x100; + int gpu_irq_line = 16 + irq_line; + + /* Check that interrupts are silent by default: */ + writel(RASPI3_IC_BASE + IRQ_ENABLE_1, 1 << gpu_irq_line); + int isr = readl(dma_base + BCM2708_DMA_INT_STATUS); + g_assert_cmpint(isr, ==, 0); + uint32_t reg0 = readl(dma_base + BCM2708_DMA_CS); + g_assert_cmpint(reg0, ==, 0); + uint32_t ic_pending = readl(RASPI3_IC_BASE + IRQ_PENDING_BASIC); + g_assert_cmpint(ic_pending, ==, 0); + uint32_t gpu_pending1 = readl(RASPI3_IC_BASE + IRQ_PENDING_1); + g_assert_cmpint(gpu_pending1, ==, 0); + + /* Prepare Control Block: */ + writel(SCB_ADDR + 0, BCM2708_DMA_S_INC | BCM2708_DMA_D_INC | + BCM2708_DMA_INT_EN); /* transfer info */ + writel(SCB_ADDR + 4, S_ADDR); /* source address */ + writel(SCB_ADDR + 8, D_ADDR); /* destination address */ + writel(SCB_ADDR + 12, TXFR_LEN); /* transfer length */ + writel(dma_base + BCM2708_DMA_ADDR, SCB_ADDR); + + writel(S_ADDR, check_data); + for (int word = S_ADDR + 4; word < S_ADDR + TXFR_LEN; word += 4) { + writel(word, ~check_data); + } + /* Perform the transfer: */ + writel(dma_base + BCM2708_DMA_CS, BCM2708_DMA_ACTIVE); + + /* Check that destination == source: */ + uint32_t data = readl(D_ADDR); + g_assert_cmpint(data, ==, check_data); + for (int word = D_ADDR + 4; word < D_ADDR + TXFR_LEN; word += 4) { + data = readl(word); + g_assert_cmpint(data, ==, ~check_data); + } + + /* Check that interrupt status is set both in DMA and IC controllers: */ + isr = readl(RASPI3_DMA_BASE + BCM2708_DMA_INT_STATUS); + g_assert_cmpint(isr, ==, 1 << dma_c); + + ic_pending = readl(RASPI3_IC_BASE + IRQ_PENDING_BASIC); + g_assert_cmpint(ic_pending, ==, IRQ_GPU_PENDING1_AGGR); + + gpu_pending1 = readl(RASPI3_IC_BASE + IRQ_PENDING_1); + g_assert_cmpint(gpu_pending1, ==, 1 << gpu_irq_line); + + /* Clean up, clear interrupt: */ + writel(dma_base + BCM2708_DMA_CS, BCM2708_DMA_INT); +} + +static void bcm2835_dma_test_interrupts(void) +{ + /* DMA engines 0--10 have separate IRQ lines, 11--14 - only one: */ + bcm2835_dma_test_interrupt(0, 0); + bcm2835_dma_test_interrupt(10, 10); + bcm2835_dma_test_interrupt(11, 11); + bcm2835_dma_test_interrupt(14, 11); +} + +int main(int argc, char **argv) +{ + int ret; + g_test_init(&argc, &argv, NULL); + qtest_add_func("/bcm2835/dma/test_interrupts", + bcm2835_dma_test_interrupts); + qtest_start("-machine raspi3b"); + ret = g_test_run(); + qtest_end(); + return ret; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 31287a91739..3a474010e49 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -218,7 +218,8 @@ qtests_aarch64 = \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'migration-test'] + 'migration-test', + 'bcm2835-dma-test'] qtests_s390x = \ (slirp.found() ? ['pxe-test', 'test-netfilter'] : []) + \