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Also add a mechanism to fall back to PIO mode, if DMA is not available or if initialization returns error. Signed-off-by: Akhil R --- drivers/i2c/busses/i2c-tegra.c | 39 ++++++++++++++++------------------ 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2941e42aa6a0..26a3d5805a9e 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -188,7 +188,6 @@ enum msg_end_type { * allowing 0 length transfers. * @supports_bus_clear: Bus Clear support to recover from bus hang during * SDA stuck low from device for some unknown reasons. - * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. * @tlow_std_mode: Low period of the clock in standard mode. * @thigh_std_mode: High period of the clock in standard mode. * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. @@ -215,7 +214,6 @@ struct tegra_i2c_hw_feature { bool has_mst_fifo; const struct i2c_adapter_quirks *quirks; bool supports_bus_clear; - bool has_apb_dma; u32 tlow_std_mode; u32 thigh_std_mode; u32 tlow_fast_fastplus_mode; @@ -253,6 +251,7 @@ struct tegra_i2c_hw_feature { * @dma_phys: handle to DMA resources * @dma_buf: pointer to allocated DMA buffer * @dma_buf_size: DMA buffer size + * @dma_support: indicates if DMA can be enabled * @dma_mode: indicates active DMA transfer * @dma_complete: DMA completion notifier * @atomic_mode: indicates active atomic transfer @@ -289,6 +288,7 @@ struct tegra_i2c_dev { bool multimaster_mode; bool atomic_mode; + bool dma_support; bool dma_mode; bool msg_read; bool is_dvc; @@ -443,13 +443,8 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) u32 *dma_buf; int err; - if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) - return 0; - - if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { - dev_dbg(i2c_dev->dev, "DMA support not enabled\n"); - return 0; - } + if (!i2c_dev->dma_support) + return -EOPNOTSUPP; chan = dma_request_chan(i2c_dev->dev, "rx"); if (IS_ERR(chan)) { @@ -486,6 +481,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) err_out: tegra_i2c_release_dma(i2c_dev); if (err != -EPROBE_DEFER) { + i2c_dev->dma_support = false; dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); dev_err(i2c_dev->dev, "falling back to PIO\n"); return 0; @@ -1251,7 +1247,16 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && - i2c_dev->dma_buf && !i2c_dev->atomic_mode; + i2c_dev->dma_support && !i2c_dev->atomic_mode; + + /* If DMA is not initialized, initialize it now. + * Fall back to PIO mode, if it fails. + */ + if (i2c_dev->dma_mode && !i2c_dev->dma_buf) { + err = tegra_i2c_init_dma(i2c_dev); + if (err) + i2c_dev->dma_mode = false; + } tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); @@ -1473,7 +1478,6 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, - .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, .tlow_fast_fastplus_mode = 0x4, @@ -1497,7 +1501,6 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, - .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, .tlow_fast_fastplus_mode = 0x4, @@ -1521,7 +1524,6 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, - .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, .tlow_fast_fastplus_mode = 0x4, @@ -1545,7 +1547,6 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, - .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, .tlow_fast_fastplus_mode = 0x4, @@ -1569,7 +1570,6 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, - .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, .tlow_fast_fastplus_mode = 0x4, @@ -1593,7 +1593,6 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, - .has_apb_dma = false, .tlow_std_mode = 0x4, .thigh_std_mode = 0x3, .tlow_fast_fastplus_mode = 0x4, @@ -1617,7 +1616,6 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_mst_fifo = true, .quirks = &tegra194_i2c_quirks, .supports_bus_clear = true, - .has_apb_dma = false, .tlow_std_mode = 0x8, .thigh_std_mode = 0x7, .tlow_fast_fastplus_mode = 0x2, @@ -1657,6 +1655,8 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) i2c_dev->is_vi = true; + else + i2c_dev->dma_support = !!(of_find_property(np, "dmas", NULL)); } static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) @@ -1789,9 +1789,7 @@ static int tegra_i2c_probe(struct platform_device *pdev) if (err) return err; - err = tegra_i2c_init_dma(i2c_dev); - if (err) - goto release_clocks; + tegra_i2c_init_dma(i2c_dev); /* * VI I2C is in VE power domain which is not always ON and not @@ -1838,7 +1836,6 @@ static int tegra_i2c_probe(struct platform_device *pdev) pm_runtime_disable(i2c_dev->dev); tegra_i2c_release_dma(i2c_dev); -release_clocks: tegra_i2c_release_clocks(i2c_dev); return err; From patchwork Wed Jul 20 12:41:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 592018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64967C433EF for ; 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Wed, 20 Jul 2022 05:42:43 -0700 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH 2/2] arm64: tegra: Add GPCDMA support for Tegra234 I2C Date: Wed, 20 Jul 2022 18:11:48 +0530 Message-ID: <20220720124148.7969-3-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220720124148.7969-1-akhilrajeev@nvidia.com> References: <20220720124148.7969-1-akhilrajeev@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 775dd079-5458-4979-0081-08da6a4d5a45 X-MS-TrafficTypeDiagnostic: DM4PR12MB5794:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TZ+y9sYLfzQ8psEpiTBdj9xxy8qydW6Lv5xDYJGc6/12CWEtJbvyCL18uSgjZ+GehUXw7XGRMrWmR62ZjDU8EHIV7S9ZaY4O5+dGPpFIFNjA0CXgovh1dGDCsh4gqOnsavjlvegYn8iZF9VI7+JCThx9fl6VBYuZ/NsIBbSWO7R845M2lwmF2M2Er9OJA0NFsQ5y/9N0/XC77pFVct36BvL5AqiMKQw1pfOtyLnkQfXsUzRqnbypBMA26D13Y5TXQs/MCYwfx6u9aOJBXITS/CVO/pEQ3aMbp5ssGfTtVn25K7WCrZv51wUxnaKbbiuuGAvgXL8gqm0h+FTGlHza3Wxw+aF2DLyCbF0hdVErXwnqf35InzCn7FdWHsORMeHtI930msxiWMa/ectupkIxQkApnrpNHp3TtPUbSWlMnj0Dwm8VT1vWPM+7uhIp28PxkjNRyrhiOhYyFk2dsj6qf4yf1pxSf88tbkJKL4A8ExdbgXS9A6yVqVImEbnACkKJQMx13m39+LiLDItOU2S4pfktPVma3ax4D/y47Tnw/cbS/8RIGDgTTK5s2D2UN/+EaAOkC6C9vDt6GQzAXcutn4ji++kQnQoXDSO+jcTxEwG5KCMGk1KsQUfQetPJtkFYvIbCOM1dpi9+V5p7YC5BTd+eaEfu3u37FtRag7axgRRk7fsHcOJ8rTmYbpkJrls4UW7ceM+Gzu+2KQb2szS87L5DDVHxiVGfjyL7qQB+uPaBxaIaFMRCulRdTuUo2ZbFlHYFyseBR9i9thziRWby6miXtJ7j8daG5zs/u3FnjJJyy6uzgk/lzLr0wiaXXh+n2iF3NANIpeTuNyCJXU29q9Pwk7+t/coOQpGAB8vrwZOBwo8NPElc07FdMXtxCLso/3K0k2DkYaCTNa/v2JUIIA== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(136003)(346002)(39860400002)(376002)(396003)(46966006)(40470700004)(36840700001)(81166007)(110136005)(478600001)(2906002)(7696005)(41300700001)(26005)(40480700001)(8936002)(4326008)(316002)(5660300002)(8676002)(82310400005)(7416002)(82740400003)(921005)(36860700001)(1076003)(356005)(2616005)(83380400001)(70206006)(47076005)(40460700003)(86362001)(336012)(70586007)(426003)(36756003)(107886003)(186003)(36900700001)(2101003)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 12:42:48.4750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 775dd079-5458-4979-0081-08da6a4d5a45 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5794 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dma properties to support GPCDMA in Tegra234 I2C Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index c3d2e48994d1..c9eed199d980 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -668,6 +668,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C1>; reset-names = "i2c"; + dmas = <&gpcdma 21>, <&gpcdma 21>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; cam_i2c: i2c@3180000 { @@ -683,6 +687,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C3>; reset-names = "i2c"; + dmas = <&gpcdma 23>, <&gpcdma 23>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; dp_aux_ch1_i2c: i2c@3190000 { @@ -698,6 +706,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C4>; reset-names = "i2c"; + dmas = <&gpcdma 26>, <&gpcdma 26>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; dp_aux_ch0_i2c: i2c@31b0000 { @@ -713,6 +725,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C6>; reset-names = "i2c"; + dmas = <&gpcdma 30>, <&gpcdma 30>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; dp_aux_ch2_i2c: i2c@31c0000 { @@ -728,6 +744,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C7>; reset-names = "i2c"; + dmas = <&gpcdma 27>, <&gpcdma 27>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; dp_aux_ch3_i2c: i2c@31e0000 { @@ -743,6 +763,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C9>; reset-names = "i2c"; + dmas = <&gpcdma 31>, <&gpcdma 31>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; spi@3270000 { @@ -1026,6 +1050,10 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C2>; reset-names = "i2c"; + dmas = <&gpcdma 22>, <&gpcdma 22>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; gen8_i2c: i2c@c250000 { @@ -1042,6 +1070,10 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C8>; reset-names = "i2c"; + dmas = <&gpcdma 0>, <&gpcdma 0>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; rtc@c2a0000 {