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X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 01/12] target/arm: Introduce isar_feature_aa64_bti X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also create field definitions for id_aa64pfr1 from ARMv8.5. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Include MTE and RAS_FRAC fields of AA64PFR1. --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff81db420d..d7190f0712 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1672,6 +1672,11 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR1, BT, 0, 4) +FIELD(ID_AA64PFR1, SBSS, 4, 4) +FIELD(ID_AA64PFR1, MTE, 8, 4) +FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) + FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) FIELD(ID_AA64MMFR0, BIGEND, 8, 4) @@ -3319,6 +3324,11 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; } +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ From patchwork Mon Jan 28 22:31:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156911 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3971340jaa; Mon, 28 Jan 2019 14:59:59 -0800 (PST) X-Google-Smtp-Source: ALg8bN7nBYOkQYUhXpIJKjQ+CSFZ9Q+ttFcFS2jFDngLsipefm58kBg+/6vpe+vknLybAG2ppHAx X-Received: by 2002:adf:f903:: with SMTP id b3mr24483776wrr.82.1548716399271; Mon, 28 Jan 2019 14:59:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548716399; cv=none; d=google.com; s=arc-20160816; b=YVdkPhhi/X5VCLXsXhDoohpZsFoc8/xyqTavjJhcVxSHJcGsopz8wru21i8MELn/wQ 7LUHaf40VcR4lb9wEwnmBOqGEQz23M546iNkK+7CvqkNYhdCUSt+ccqHO9s0udrxbScZ PAt0nuYN8l31S7pDyNbdAORC+jJDtTMFusFSbliThe2VuTmavBd/yERGa4LqUFGy8nGr RSqi+Gf1wdTPQHspSlnTXlj4F4j9RwUfkNOJYoZsLILoBG8+2iwmrTyELHIApoFeDsI9 M0jdFuhqYb5Td7xFHtgMVvvDqmGIR+P75gyX+dzE5qbyByOrGoARR5Niq2uefbgt1vOn 9NOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=L1V0Cb951FG+u8k/qfbiwXAE3MaliW8mMdVB2nz63mc=; b=aXOb6U4vY02pn7dAWCTI4QiYm3G8g2Oo/rD90Vu+gup5tCWLABPI8W+Ne8VZFoU5sP ZFfjn3cq+1TFHlHYGQstBrHC6zbHFaeyxJiBLCPqTf7Gcl8YVaFzeJBn7u1RhU+53z+g ik2LEEF/YvHqYob9a2i86+qgZBr+OFT9yhG9/VI4vshIMnHl9Xj1/D3J+JuthfTkchOe lOVjbLiqxfuNaVAllf0vcdVASc0WqfhGAK2bzFcwXtLtlDAODrUivTufBpoBR471a2gz pCTsk98n4Lr+LkbIzcq2jQ0vcDVzoLT3MT+JccICqg2d1dBHEq9YHxA6QcHjzdxncgwb KK9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GEqDlfPe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 02/12] target/arm: Add PSTATE.BTYPE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Place this in its own field within ENV, as that will make it easier to reset from within TCG generated code. With the change to pstate_read/write, exception entry and return are automatically handled. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++++-- target/arm/translate-a64.c | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d7190f0712..76e2f8fd42 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -234,6 +234,7 @@ typedef struct CPUARMState { * semantics as for AArch32, as described in the comments on each field) * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif + * BTYPE is kept in env->btype * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; @@ -263,6 +264,7 @@ typedef struct CPUARMState { uint32_t GE; /* cpsr[19:16] */ uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ + uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ uint64_t elr_el[4]; /* AArch64 exception link regs */ @@ -1197,6 +1199,7 @@ uint64_t get_pmceid(CPUARMState *env, unsigned which); #define PSTATE_I (1U << 7) #define PSTATE_A (1U << 8) #define PSTATE_D (1U << 9) +#define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_V (1U << 28) @@ -1205,7 +1208,7 @@ uint64_t get_pmceid(CPUARMState *env, unsigned which); #define PSTATE_N (1U << 31) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) -#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) +#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) /* Mode values for AArch64 */ #define PSTATE_MODE_EL3h 13 #define PSTATE_MODE_EL3t 12 @@ -1237,7 +1240,7 @@ static inline uint32_t pstate_read(CPUARMState *env) ZF = (env->ZF == 0); return (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) - | env->pstate | env->daif; + | env->pstate | env->daif | (env->btype << 10); } static inline void pstate_write(CPUARMState *env, uint32_t val) @@ -1247,6 +1250,7 @@ static inline void pstate_write(CPUARMState *env, uint32_t val) env->CF = (val >> 29) & 1; env->VF = (val << 3) & 0x80000000; env->daif = val & PSTATE_DAIF; + env->btype = (val >> 10) & 3; env->pstate = val & ~CACHED_PSTATE_BITS; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4d28a27c3b..611279e98e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -163,6 +163,9 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, el, psr & PSTATE_SP ? 'h' : 't'); + if (cpu_isar_feature(aa64_bti, cpu)) { + cpu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); + } if (!(flags & CPU_DUMP_FPU)) { cpu_fprintf(f, "\n"); return; From patchwork Mon Jan 28 22:31:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156907 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3964646jaa; Mon, 28 Jan 2019 14:50:14 -0800 (PST) X-Google-Smtp-Source: ALg8bN7PRi3S9/7YiSQfCoZs1lBLduI7fm4bwxfeGDn9NDqPQTVOVxET5y6L0yfDNJphafVG2QQ5 X-Received: by 2002:a5d:6889:: with SMTP id h9mr23300778wru.222.1548715814040; Mon, 28 Jan 2019 14:50:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715814; cv=none; d=google.com; s=arc-20160816; b=pw/meBAuzulrYkSFHFLYIvBycqzqr9OtL+k0wFfqfJ4/gB4Vs8OJO6pGQ18euUnIm7 wI3xjmIJP6dKYWIoAhFCnNBzwBHoPQyYC8k82MfnO9wXLououIrNoEfCY/qB2el/7hlT /N/DC4owhO81OU8L5Vxf2RtY/C1Xwna0wMiyoaUjjFhHa0H/8jlC09ikosSk7pDT27Fp FZbeuY3rNLiJRHIfaE4GacMgreMZ4hg4WQ0+3qJUwqe19ajT0iSGLdHjD5w4Wsis6aQu LUcMm3ftbafDqy2MDMxbcZcU4TQsSdLs8gDsXQlqF+fCG304NIwuuKFk8+B6Fr3ZJ7bB PkVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=yfx9FpdqdozZiBPg7dcsv6e5CFB+7qa5v/xOlmbgNhY=; b=MaqooS0oehRtTYSYZ6TuBN03fZF1N1JLDAexhNDfubWVcZDcxaFKhAuLpqvq+fCmA9 8scw4b51Lbj5sSO1HNbNMxBEfWMWDVyX2jKGTRqpjcKs2EzhNnrELtDRAmBFXKbypM2X azjVsu2wj5FfH8FfZ38h2bx1rdZFFGT3xIp5Ke3XiR0SA3+ahMcKzj4ya4a4rrExAK8d q3WU2aANvQXHhLHnhhTjxg5g8jteQHXLeRDBj4X6TkJB7x5DlTwtmMLBAuVQQtG3jXiT RMHRoVQafEcrPtGsRqhrkbtPBjtqWZ8UiHIKeKv6Fyv/GF+fbvOoJ1HdVGFi9qOUHVS/ /F5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kM4pn0wB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s82si529364wmf.82.2019.01.28.14.50.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:50:14 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kM4pn0wB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39684 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFjJ-0003hE-0E for patch@linaro.org; Mon, 28 Jan 2019 17:50:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcC-0006rk-Ue for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRE-0006Cn-Ua for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:34 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:35290) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRE-0006Ai-Js for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:32 -0500 Received: by mail-oi1-x244.google.com with SMTP id v6so14530861oif.2 for ; Mon, 28 Jan 2019 14:31:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yfx9FpdqdozZiBPg7dcsv6e5CFB+7qa5v/xOlmbgNhY=; b=kM4pn0wB9UQR3RwymhGca/pcSefCUtQUgGGnOOBospAPrRGzF2FuPPeq3FuWtRpjuE qgduZmP4+N0hoThqHclyS+E7FuZZWum3hY7bkXqpOq3dXUEK7vXW7PK/2qjl5oOB5Leb x90pq8fSLHWvnsKEjjqKvUTCNm178LayPE+n8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yfx9FpdqdozZiBPg7dcsv6e5CFB+7qa5v/xOlmbgNhY=; b=AcP1piEgnaWCFpWjM2Pl/+0FT+P6iBceBUueutx6OU1zTRp89dF/5CYYvtc7nONvBC YQ42ZxE0oQ3HXLOd0NkH08Jpmg1GX5bIZIqjGk93jPafEmOxQD8Hm1XR1bajGGz+2UlE sl0SqyQjXE3ElJLsoEHd0PUjUUdTwio+UuU47RdaLbv77gfXfLyTHGui2l8zGhFqPSCT sasV0blvhVnl/56uviaNZFlL+elgt2YwwiGbeTGFGeD7NkFK1mODtdaXNCsLAL0uRatc jydH4EwFf+ZIXKoXjf4Zf5ZLlFDXezDJL+wN7Kifq6thaySAF1MqQjM1tr1gx2ZgJAlV iOyQ== X-Gm-Message-State: AJcUukctIn2VlyGE/5/KjTxqI6quo9XM9sBBQOOmi8o7YjoieDgjMu+y 0DcWuQsLv+VRl0Sh1qKU2jtGWTB06nw= X-Received: by 2002:aca:aad8:: with SMTP id t207mr7021779oie.90.1548714688679; Mon, 28 Jan 2019 14:31:28 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:09 -0800 Message-Id: <20190128223118.5255-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH v2 03/12] target/arm: Add BT and BTYPE to tb->flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 4 ++++ target/arm/helper.c | 22 +++++++++++++++------- target/arm/translate-a64.c | 2 ++ 4 files changed, 23 insertions(+), 7 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 76e2f8fd42..e18f823419 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3043,6 +3043,8 @@ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) +FIELD(TBFLAG_A64, BT, 9, 1) +FIELD(TBFLAG_A64, BTYPE, 10, 2) static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index bb37d35741..3d5e8bacac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -69,6 +69,10 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ + bool bt; + /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ + uint8_t btype; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 92666e5208..6efe88a157 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13607,6 +13607,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (is_a64(env)) { ARMCPU *cpu = arm_env_get_cpu(env); + uint64_t sctlr; *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13651,6 +13652,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } + if (current_el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[current_el]; + } if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether @@ -13658,17 +13665,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * a nop, or "active" when some action must be performed. * The decision of which action to take is left to a helper. */ - uint64_t sctlr; - if (current_el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr = env->cp15.sctlr_el[1]; - } else { - sctlr = env->cp15.sctlr_el[current_el]; - } if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); } } + + if (cpu_isar_feature(aa64_bti, cpu)) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + } } else { *pc = env->regs[15]; flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 611279e98e..9ce523e2ff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13801,6 +13801,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); + dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); + dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Mon Jan 28 22:31:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156901 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3960809jaa; Mon, 28 Jan 2019 14:44:46 -0800 (PST) X-Google-Smtp-Source: ALg8bN6fvV5u/sGq1kSDDgl86dT1lLKtfciFkUkiuaaAdlaTSWPAqYflaYDHMpxOhy1P3CMYzvKP X-Received: by 2002:a1c:f319:: with SMTP id q25mr18752070wmq.151.1548715486143; Mon, 28 Jan 2019 14:44:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715486; cv=none; d=google.com; s=arc-20160816; b=wTtPSLELf+1/EFx14qp8f6bvRwYHavnB4p+Fa39+qwrVvQyLoxnRUmcKrJyNgGZNJ/ g5whMVPdvdbA+2u1gIPEW9K7g8XCQmBWI0ZppyJOfaAaioug7dONmXh5cK1SVWFAUBG8 /V2mrNs/b7Bztr4dfM6nM8F/vpndu+rnKoh9R2jrX8fKRF2hEhBXuZjleHB4kiYRJWfw ifdBPCFhuh1n37ue2Lx8yZWHXVr+4vhQ8AlIAXAZQvcdl9UITGzk7Q7zjOXhOUnKrv9V Jp/g5Ynyj/jXjGc8bWioqN212LZ1hshmBgSaWwpEDLb4Ht36NPlrZ/MkfSQ8pqWYOgae 6kxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=PuHA9slAwS6cMEvVcURGk2HxWJ9T4N5ch4vNRS6j+AM=; b=aJFvJlIEjvYqW8ZHj61OyQ7Mb60IEQB3+wkIUrpDaejBsVnkMG/ycnMKy+W7eeRpQP dNIMR2x61PENbHE8LESqgv8tTHTlFKmh5EXdQmg9zMw1NI5gCynqu4qUADt7KwwhV4lj 8APp8RC+Y/RiAiTBwOhZUSl4v9YogtsBvvEBRwd8sWIzEmG7QtF1ME9ItdQjgkfju66Y lzA/tqpMNtLrUtwctTifoKb8ncw5Tbu6RNKa64/OtAnPq1iS/Y/TMZG69pOpwm/eWnz3 U3Hm0g3EHgIT+o68181fxekVtx85xabPJBDoqAWPoYLLpKsHjdOrKCxFd4h/FsKnjB1M Q2kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IiWuYMX1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d17si486908wmb.100.2019.01.28.14.44.45 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:44:46 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IiWuYMX1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFe1-0008Er-4U for patch@linaro.org; Mon, 28 Jan 2019 17:44:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcA-0006wV-IB for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRS-0006Jz-NK for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:48 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:37911) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRR-0006B8-0J for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:46 -0500 Received: by mail-oi1-x241.google.com with SMTP id a77so14513303oii.5 for ; Mon, 28 Jan 2019 14:31:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PuHA9slAwS6cMEvVcURGk2HxWJ9T4N5ch4vNRS6j+AM=; b=IiWuYMX1jpvgkxpK0LDH6uYffIgdEnbsgvw9Lfkk0W7xO9fnyr8g9p22PbEigM8Sqw yOo2D1YmFxwKbRgsf4j2VsvQmCtVB6LT50Ov0eGoW1T/4eeRMnN09iMEe2mDIoBPBwaX y8tHO7u7lh3OgGE6q/RjrKaDy7+EpcisfC0NU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PuHA9slAwS6cMEvVcURGk2HxWJ9T4N5ch4vNRS6j+AM=; b=STy/mrElMEOGioQ7zOA4WbycSMquvOeQx6qQR7sWPAFFF9SvEQwmE9gH/A6LpMna5g 9T1dQtaC38iqbO7QTFWvWdyUiOKFgzpJY9U+IlVttcLws7PnnZezqKCZiK3au8L5N912 s1cMb5S8m0Jl/YO7qWIFTCLi6HljstVfz/DwE7qHPMJ7/+87wmrI4B5vu7k0nT9uTVSW 3uGOG3NPIjdnbAvN0KNYWDZONzURlE6bEAalU1EeXp+peftNK8FcLXKHWIqGewuL9vyl 0asxUerYreZWPo4AdU8wkBkQWYzjJH7ZtXr7sYZW8BpdvW3GQK43ZhPSmc9+ddunxSxl sBdQ== X-Gm-Message-State: AJcUukfhDPIeP4H7YnQPN6ibyfYibqqUCQyPtHJJBWexxaUxRWzh1Q3I MpC7eWIcTC+8AJsYkhopLKO0jpx8kkk= X-Received: by 2002:a54:450f:: with SMTP id l15mr7612944oil.351.1548714689843; Mon, 28 Jan 2019 14:31:29 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:10 -0800 Message-Id: <20190128223118.5255-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 04/12] exec: Add target-specific tlb bits to MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These bits can be used to cache target-specific data in cputlb read from the page tables. Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a1642098..d4a3477d71 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,16 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* + * The following are target-specific page-table bits. These are not + * related to actual memory transactions at all. However, this structure + * is part of the tlb_fill interface, cached in the cputlb structure, + * and has unused bits. These fields will be read by target-specific + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. + */ + unsigned int target_tlb_bit0 : 1; + unsigned int target_tlb_bit1 : 1; + unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, From patchwork Mon Jan 28 22:31:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156900 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3959928jaa; Mon, 28 Jan 2019 14:43:30 -0800 (PST) X-Google-Smtp-Source: ALg8bN7qYzEN8ecjDU9F8ZDBgF9B3Gx9ffj2BfVNfTSVcqHB0MAushtf0xHFRp4sGEkHJMtb/LWr X-Received: by 2002:adf:d0c9:: with SMTP id z9mr22459339wrh.317.1548715410132; Mon, 28 Jan 2019 14:43:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715410; cv=none; d=google.com; s=arc-20160816; b=Sg5cL7FZ9fX02yKyUXZaibwWTB9WJAJoISkrmMzicxEA3JhDEDUafRiT5T9P5Uu6lV odT2pffWnyKD8FlQitGSz8eLJr22IAU2tskkzr3RoI6wCe5FPrJFA0UiNHs+vK3LkAur ryMpbvaC6O9vrqqT3LUSJcAQOW/YJ95dY7ZV8hQ7nhbs4GSmfouMnc5yV+R/S3qUqyHG YoHbzg7sm1xqVqH1O32Q2A19CBPBODY5PTf+oQUUxHWMEWwlnQTlfQ9xR/0gnaO/YnZd 3O6LQ+LgSKsvEzkCGM26wMnJKyl55h9GgdS+zz1tAog/l8xFwVR+Eb61+Kfql0y2a9Yr G1/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=D+PDofj1o/9B5dTtIL1BwBv8O4UrkEKB0kHElaN43pE=; b=c8oNiaVOsmGGBbaHsg7zuX9TPniqV+Z2gI/mvA11LgTVx9pMwfUQNGgAunbdmfl5jy Sp6ObS16Wug4nUfXH8jg28c3Am62OAzFvjQW13s+eKGzntc96A0hZtIK/8KnTbUeT/lP Be/zXW9O1mhCuysRR1nhCgWxxsm+YfDXE1Obz3J/oT28qp0gQG5cJA/xmRgc7qdRTYKL mSVgtMQfL1dobKwQoGHC+DuzXWy/xgVfvaqvFCFkAQgkVciVf0XPqCy0EuumOhudH1BY kQw+2mnczD23Mako7rJgdsReBDn/50VgZUjSoACsE2a/b9IiB5RZ/jJKWuYuQJY1Ef8p 8pTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NdmIDKY2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o204si499613wme.148.2019.01.28.14.43.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:43:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NdmIDKY2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39591 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcn-00072L-3n for patch@linaro.org; Mon, 28 Jan 2019 17:43:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcB-0006iZ-5Y for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRQ-0006Ic-Ns for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:46 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:46884) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRO-0006Bz-N1 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:42 -0500 Received: by mail-ot1-x343.google.com with SMTP id w25so16140538otm.13 for ; Mon, 28 Jan 2019 14:31:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D+PDofj1o/9B5dTtIL1BwBv8O4UrkEKB0kHElaN43pE=; b=NdmIDKY2WqNM3i55GEzJfoTuSM+FZCANmO2dZQMf2ZTjKzid9qHttBI016VTpl42C+ gw8ceq5CVBehzAvgeGA9z2ogiYZJ0qJlkncHhBLRHUN8gdcGQMaWQx+dQoxwqPjjKAGf 6K64Cc577uDCMTPZjo3jTWkqARqM0IXyUM2Xg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D+PDofj1o/9B5dTtIL1BwBv8O4UrkEKB0kHElaN43pE=; b=rkOQ53dGxqyHj7JONXTsH9nzqEqEFWmICxsVSUaIrePqL5cS9juBi5PYVh6IlB5uN2 fIw0En7+RJBDm4OPJLz0yuY79Np5YAX/SAAuR/k6sHmR8wx0MkWXHaTmbiIXGxW8rkYp zaoTdp8GhWB+sRkG/NbcunM63TNMYNQQKNkCz92OqqR6WskSyRrps0WOdTJXNfLh7T/Y e+QNvBiHeKgVk+FrN0U5BaUm18AzwHFXyq8AQY4zO9MMl7xfM3TwBtQR1p2sCZ7LtwDa zhznc0bX+sx0lOaFA6bBY5c5jFjro49fB0ihQcqqRsnLNZzwoVPX7UrpnyrPH7uUe2VN XrIQ== X-Gm-Message-State: AJcUukfv9NJnn546ET8YHf11lfdQbKbNoS+0jVddljFXke6/Tloe6gQP y2fGvwX+4qa0Q1vAduVKwM+yi1vUCzY= X-Received: by 2002:a9d:6c44:: with SMTP id g4mr16550494otq.368.1548714690939; Mon, 28 Jan 2019 14:31:30 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:11 -0800 Message-Id: <20190128223118.5255-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v2 05/12] target/arm: Cache the GP bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Caching the bit means that we will not have to re-walk the page tables to look up the bit during translation. Signed-off-by: Richard Henderson --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index 6efe88a157..70277222da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10457,6 +10457,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); + bool guarded = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10629,6 +10630,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ + guarded |= extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; @@ -10674,6 +10676,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, */ txattrs->secure = false; } + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { + txattrs->target_tlb_bit0 = true; + } if (cacheattrs != NULL) { if (mmu_idx == ARMMMUIdx_S2NS) { From patchwork Mon Jan 28 22:31:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156906 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3964216jaa; Mon, 28 Jan 2019 14:49:38 -0800 (PST) X-Google-Smtp-Source: ALg8bN4rct0AGtNgQSsquK2mttoCgthPXupaampQL2eRL8BixvinvNrhu1BUYurqmuQQa4wlIWP6 X-Received: by 2002:adf:e34b:: with SMTP id n11mr22299361wrj.91.1548715778266; Mon, 28 Jan 2019 14:49:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715778; cv=none; d=google.com; s=arc-20160816; b=zVh74iIzlFSPICkbGRS90dr/LgdHCEwK42BDCMtYgOElWBeNQaKdOWBC4ZiLA4a40L KHBKfpIc8QijZAFTCeX8KljQUc1VYsjVN1N8ryzyb6DtehW1Q2wStFXMbyM2NwIgjiJ2 NcPpKtzsPsFrhxKFMt4E9WaNXkqPjHtHs30SQZR+yNBtdA/VBpYhexMxw3pC6W4wL5jX TN3a1zoQ+26+tg6UpLb9HjhvJiN6W8OXDBp6auyrdc7xkc/uPt39ox4OP372ZJPFTfhZ 7SrDrArrm6lD98RMn0YcYBYs5rshOu1lWcOksy48GpYm3NO3vfVcHYIC/PemHV8ub18B 0PSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=xY3AiwlvI8bD51I3D9hVlZ1QPX6oH0ZaOkYhIUDuI8E=; b=WcDy0iX+0YTMSXgq1wepkIOQ22x4mueNKvWnnxv50XjTQDSVvFMWY2lYyYx3mtkEV0 8BAi1guybm3hip4O+4DJHpWo0y5QjlDY7ItnLiG/rq8wJCqRL7Z3xv0ABevOT3rBOrrp X3DFeP7GnACgDtdGYesn3yh2zliDMqsDT1xoVK+QwrQSyp+bsNk1dWxQlgHCO6GJd8YZ WRwSYsxlVHKkaO25mqKqTwhZ5I5A6pPQZbo53eRHE7l65Vht62i/yGqAAEvL9l5+ums5 8OSR9ws5gFGA0NAKbRtBU6jLWTPfDPnOkMpEgNdmtd1+VGjy5W2mIM16dqmMopS9B3eA jB/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HuFTKCD4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x184si569070wmx.54.2019.01.28.14.49.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:49:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HuFTKCD4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39667 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFij-0002Nc-42 for patch@linaro.org; Mon, 28 Jan 2019 17:49:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcB-0006wV-Dl for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRP-0006Hh-0I for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:44 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:44849) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRM-0006Cj-Sj for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:42 -0500 Received: by mail-ot1-x344.google.com with SMTP id g16so12158270otg.11 for ; Mon, 28 Jan 2019 14:31:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xY3AiwlvI8bD51I3D9hVlZ1QPX6oH0ZaOkYhIUDuI8E=; b=HuFTKCD43GNTykYYB/RbQ+tJnUTHP7j3BXGknLKia2e0pfPtwJDbQFxNHa7TU9pxZJ UVquzPqQsSgSBCjbpBGMtCI8vzy2yZ7L+EJB2ThgAT6A5nshMKsP9Tj38rCyfUuYjccS s2QyN2Ty8DYp8RBjV6MH7aYzz8JRj2lLDSgGw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xY3AiwlvI8bD51I3D9hVlZ1QPX6oH0ZaOkYhIUDuI8E=; b=j2AeHdLMXJd7pgRw5YSzkCJOhIir8w0roWeyX0Mcr9iREpzCe12KfoTvFglnGZc6dL V3f9f2YouRI9hrlIGpMldzPErfu3GyVmliIpPgc/GL68beK7jwYcR3VUnvRRhSBu/Xgb mfTeHhsZ/lsP+Tz6fhcwInXMmbnnoIfuULGdmwBPEFnNBs7yNjuA9lbBx3QG8bwqwhO3 T+ecWPAXrLdSqqwj1DK7QRdW0VIvTUMPG8Bo99sQxJboOx+SZewv7Fba0ep+rhPvyg5P YYOc1YxWkMKb7x8Qupb4+RwiPq2EYWvKHdFxkXk4BzYoUhP0vAL1mbG1qNWS+8YrEw/H xxQg== X-Gm-Message-State: AJcUukeYMEPCs+eNQcr0ayLch5gnfgOAbCDTp/CzgF9xU2sKwka5xw8O UgAlVlrprpvwSpBP8d7K2xPZcc2c08g= X-Received: by 2002:a05:6830:1453:: with SMTP id w19mr18001388otp.213.1548714692041; Mon, 28 Jan 2019 14:31:32 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:12 -0800 Message-Id: <20190128223118.5255-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 06/12] target/arm: Default handling of BTYPE during translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The branch target exception for guarded pages has high priority, and only 8 instructions are valid for that case. Perform this check before doing any other decode. Clear BTYPE after all insns that neither set BTYPE nor exit via exception (DISAS_NORETURN). Not yet handled are insns that exit via DISAS_NORETURN for some other reason, like direct branches. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Change octal constants to binary. --- target/arm/internals.h | 6 ++ target/arm/translate.h | 9 ++- target/arm/translate-a64.c | 139 +++++++++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/internals.h b/target/arm/internals.h index a6fd4582b2..d01a3f9f44 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -268,6 +268,7 @@ enum arm_exception_class { EC_FPIDTRAP = 0x08, EC_PACTRAP = 0x09, EC_CP14RRTTRAP = 0x0c, + EC_BTITRAP = 0x0d, EC_ILLEGALSTATE = 0x0e, EC_AA32_SVC = 0x11, EC_AA32_HVC = 0x12, @@ -439,6 +440,11 @@ static inline uint32_t syn_pactrap(void) return EC_PACTRAP << ARM_EL_EC_SHIFT; } +static inline uint32_t syn_btitrap(int btype) +{ + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/translate.h b/target/arm/translate.h index 3d5e8bacac..f73939d7b4 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -71,8 +71,13 @@ typedef struct DisasContext { bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; - /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ - uint8_t btype; + /* + * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. + * < 0, set by the current instruction. + */ + int8_t btype; + /* True if this page is guarded. */ + bool guarded_page; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9ce523e2ff..bb64a47c0f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -128,6 +128,16 @@ static inline int get_a64_user_mem_index(DisasContext *s) return arm_to_core_mmu_idx(useridx); } +static void reset_btype(DisasContext *s) +{ + if (s->btype != 0) { + TCGv_i32 zero = tcg_const_i32(0); + tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); + tcg_temp_free_i32(zero); + s->btype = 0; + } +} + void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -13717,6 +13727,90 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) } } +/** + * is_guarded_page: + * @env: The cpu environment + * @s: The DisasContext + * + * Return true if the page is guarded. + */ +static bool is_guarded_page(CPUARMState *env, DisasContext *s) +{ +#ifdef CONFIG_USER_ONLY + return false; /* FIXME */ +#else + uint64_t addr = s->base.pc_first; + int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); + unsigned int index = tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + + /* + * We test this immediately after reading an insn, which means + * that any normal page must be in the TLB. The only exception + * would be for executing from flash or device memory, which + * does not retain the TLB entry. + * + * FIXME: Assume false for those, for now. We could use + * arm_cpu_get_phys_page_attrs_debug to re-read the page + * table entry even for that case. + */ + return (tlb_hit(entry->addr_code, addr) && + env->iotlb[mmu_idx][index].attrs.target_tlb_bit0); +#endif +} + +/** + * btype_destination_ok: + * @insn: The instruction at the branch destination + * @bt: SCTLR_ELx.BT + * @btype: PSTATE.BTYPE, and is non-zero + * + * On a guarded page, there are a limited number of insns + * that may be present at the branch target: + * - branch target identifiers, + * - paciasp, pacibsp, + * - BRK insn + * - HLT insn + * Anything else causes a Branch Target Exception. + * + * Return true if the branch is compatible, false to raise BTITRAP. + */ +static bool btype_destination_ok(uint32_t insn, bool bt, int btype) +{ + if ((insn & 0xfffff01fu) == 0xd503201fu) { + /* HINT space */ + switch (extract32(insn, 5, 7)) { + case 0b011001: /* PACIASP */ + case 0b011011: /* PACIBSP */ + /* + * If SCTLR_ELx.BT, then PACI*SP are not compatible + * with btype == 3. Otherwise all btype are ok. + */ + return !bt || btype != 3; + case 0b100000: /* BTI */ + /* Not compatible with any btype. */ + return false; + case 0b100010: /* BTI c */ + /* Not compatible with btype == 3 */ + return btype != 3; + case 0b100100: /* BTI j */ + /* Not compatible with btype == 2 */ + return btype != 2; + case 0b100110: /* BTI jc */ + /* Compatible with any btype. */ + return true; + } + } else { + switch (insn & 0xffe0001fu) { + case 0xd4200000u: /* BRK */ + case 0xd4400000u: /* HLT */ + /* Give priority to the breakpoint exception. */ + return true; + } + } + return false; +} + /* C3.1 A64 instruction index by encoding */ static void disas_a64_insn(CPUARMState *env, DisasContext *s) { @@ -13728,6 +13822,43 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) s->fp_access_checked = false; + if (dc_isar_feature(aa64_bti, s)) { + if (s->base.num_insns == 1) { + /* + * At the first insn of the TB, compute s->guarded_page. + * We delayed computing this until successfully reading + * the first insn of the TB, above. This (mostly) ensures + * that the softmmu tlb entry has been populated, and the + * page table GP bit is available. + * + * Note that we need to compute this even if btype == 0, + * because this value is used for BR instructions later + * where ENV is not available. + */ + s->guarded_page = is_guarded_page(env, s); + + /* First insn can have btype set to non-zero. */ + tcg_debug_assert(s->btype >= 0); + + /* + * Note that the Branch Target Exception has fairly high + * priority -- below debugging exceptions but above most + * everything else. This allows us to handle this now + * instead of waiting until the insn is otherwise decoded. + */ + if (s->btype != 0 + && s->guarded_page + && !btype_destination_ok(insn, s->bt, s->btype)) { + gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype), + default_exception_el(s)); + return; + } + } else { + /* Not the first insn: btype must be 0. */ + tcg_debug_assert(s->btype == 0); + } + } + switch (extract32(insn, 25, 4)) { case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); @@ -13764,6 +13895,14 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) /* if we allocated any temporaries, free them here */ free_tmp_a64(s); + + /* + * After execution of most insns, btype is reset to 0. + * Note that we set btype == -1 when the insn sets btype. + */ + if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { + reset_btype(s); + } } static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, From patchwork Mon Jan 28 22:31:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156904 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3962436jaa; Mon, 28 Jan 2019 14:46:53 -0800 (PST) X-Google-Smtp-Source: AHgI3IYYMHxAkGaoNbLfo5z7YLI4JsfI499waUy69069Oj+QVQXGKXW7tU3Jyd4UfmbAJprK9bd1 X-Received: by 2002:adf:fd81:: with SMTP id d1mr15902003wrr.105.1548715613669; Mon, 28 Jan 2019 14:46:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715613; cv=none; d=google.com; s=arc-20160816; b=ckdbgVRbka87Vkk6CU0jcfgVM6lBKZFdSe/gdTrjSftKMRbG5wEiVqcv1juVIhZfKd No0Un8HXwNhr4KeKjRffI/QDyAUFtxveMTBFRRgyJLEImzst+GjBOwbCYJ5mW2zpMSZb f2mr2KH5xcoaslB5zP/ohd62PhgBGs4z6NSRhI7fzf6ivGTragoK4MH51HbX+RBlHzry CbK+XM4A889iuCeJSAc5Pmhu4d46rNjGSd78wLijHnnSgFGEnr99fScZvYOlSXQnW58z 7xBOCoVrixi6u0rMSLMtqDwVE5Qc3vBXQAzspodHmaRtVOHylZlEa7LqkYPXiEfp5OU6 ezbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=g/wlaoP5e340Ci6J1OFniSrZU/3oGYMfCDfo8IwBy0Y=; b=HB/iUSs5Ps2H7U2kxsq54XW3KYi1KB3JntAuYOVgwXPjb3ZkL9oQsTiyF5weZY5Zus L3Eo3FCRocgbWKi6bvzNlN7RomrqBv3CajwOHIwxDZSxAzimoje1XSVidSZ1v8uDhgEp S32DdrC9E0va2cwbOTtTHOmEk9Tr0lLIzUJoDwYLi/fviuW7HDSsgbSxn5LA+35sizWc 9Gm3uTURgurs1K8mGMyuIuQMvToLcLX5vbEErbWpFTKT0Rne07ZhjDkyuDsKwFiThafh oMAeGgXQWrITCyAzACL5P+nwfyF13+5ksRhM6mztvIhvH4ACwl8UslIW56lmqEU6SzDG 5YXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BI4HhTc4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s11si531118wms.57.2019.01.28.14.46.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:46:53 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BI4HhTc4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39659 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFg4-0001Hj-I7 for patch@linaro.org; Mon, 28 Jan 2019 17:46:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcC-0006iZ-4F for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRI-0006EL-HK for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:40 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:33122) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRG-0006DJ-QN for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:36 -0500 Received: by mail-ot1-x341.google.com with SMTP id i20so16202603otl.0 for ; Mon, 28 Jan 2019 14:31:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g/wlaoP5e340Ci6J1OFniSrZU/3oGYMfCDfo8IwBy0Y=; b=BI4HhTc4xKOxmY35izj+YJxBCtSf+DdfUtMBhEupQKEfHFJUi2uBZ6jY99ZJSbvwRY 344EveFisW39/lCGiXN1WLAR/BfeXGbhGBj4VAeK9/6PlptBajtqTmqh90iIVVgEklP/ oIfxWC2J1FSX1iH3Qn7Y2ZK27RavZRo+0ELv4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g/wlaoP5e340Ci6J1OFniSrZU/3oGYMfCDfo8IwBy0Y=; b=YECwWh5wehO2JrQjeJapll+S8h9Q6OCvT8W3gQSWBcmCrOaDqhC15Pn+zDDCpZgeVd 6oW+FhSOZ/Gc4gGJC2iN5ZLUq55JrPe3jLkknLMRO/uUrRlnp0iUgTGo9ucC6f/KVSuh G6ZbB1U7aaIlroN5xnvJVwj916tkyiGHz+Xa1tvrIa3SsLPrSwhjbvetatrmmyf7Ry4x s9hZfZwhlS8Tmyfag7VYTPuHHRUrkd6e0cm/CwRxZgCSO7gqQNcss8xLG/q/DXKXEpKW aozsfo41Q+m7a3uENK33hwbAX5JoQUyc5sxdEsWq/8ZENba5ESbSp/XC9MKKF37r/Q2P Q8Hw== X-Gm-Message-State: AJcUukdk1Tkfy01oYrjbwaMsAP9J1olhqH9PoLlrWPY1szSIR6qkn/YS keWAfyoAzqTuHFCbhG95AFuMBQ8no6w= X-Received: by 2002:a9d:6a1a:: with SMTP id g26mr18305385otn.172.1548714693253; Mon, 28 Jan 2019 14:31:33 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:13 -0800 Message-Id: <20190128223118.5255-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 07/12] target/arm: Reset btype for direct branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is all of the non-exception cases of DISAS_NORETURN. Signed-off-by: Richard Henderson --- v2: Do not reset byte for syscalls --- target/arm/translate-a64.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bb64a47c0f..dbac09743c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1362,6 +1362,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) } /* B Branch / BL Branch with link */ + reset_btype(s); gen_goto_tb(s, 0, addr); } @@ -1386,6 +1387,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) tcg_cmp = read_cpu_reg(s, rt, sf); label_match = gen_new_label(); + reset_btype(s); tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); @@ -1415,6 +1417,8 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) tcg_cmp = tcg_temp_new_i64(); tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); label_match = gen_new_label(); + + reset_btype(s); tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); tcg_temp_free_i64(tcg_cmp); @@ -1441,6 +1445,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; cond = extract32(insn, 0, 4); + reset_btype(s); if (cond < 0x0e) { /* genuinely conditional branches */ TCGLabel *label_match = gen_new_label(); @@ -1605,6 +1610,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, * a self-modified code correctly and also to take * any pending interrupts immediately. */ + reset_btype(s); gen_goto_tb(s, 0, s->pc); return; default: From patchwork Mon Jan 28 22:31:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156902 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3961727jaa; Mon, 28 Jan 2019 14:46:03 -0800 (PST) X-Google-Smtp-Source: ALg8bN4BZvfyu6EBrIwkQkhvMd0mLTrlh+TZa5/3l56CZS2HLi3b6kg7TSoymRtFCaE8Wm2xBSOu X-Received: by 2002:a1c:5fd7:: with SMTP id t206mr19718615wmb.145.1548715563464; Mon, 28 Jan 2019 14:46:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715563; cv=none; d=google.com; s=arc-20160816; b=WrZmDO0S7O3vh6v+lfIXNl1LoTBQ+7BTHQgAFcVINbsOSJMPHvlR8HdSbO3AfQE/j+ OkfXm5tOcftPcbg/a3HKROaLcPXL5mo38Oz74Dab5EfUkh+GrRr89PmUp+C/+srWGcGu 6rdZndT9LlTBnsUFEQctK4AP7jby3P7LHWiwcuK1QqSmIgAnCqjOqgp/8xKfsLnx0Wra NyP3lE8tjMiC5DlbFtcGHInnlFSkkJuRUKBXV2xCr/CvElr5j3WZPN9B604TRs3XuTFv PIhVkzIyPxi3StHoDn8rKuGsS7uJloMtITMACSSF2WBLNb3fLeUJxYij7zg1J4eGwNtr A1wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aRqO13PLpb8W1n66DnnonWFep8pSE0GiVCC/pgwaWCQ=; b=0dY1ROJpX63RC3+AzzMGeJT1SCsmcSBdzAozcd+dn1V4/lS2TmmPshyATyiqCbNZ1X fGGf6KLIfOrYTYyt29YSWOXkxqAxi+G2iRR0KM1PVTX8uuk9e64uJO8aiEawv+LXPNry V2rGUmDgGeLcnSV/s/NyxHje38/1KZEtBebhXHDDUTroHKpr12WW7RiRz7hbrcse3lO4 8B0TpfdAw5jcowBMubj35RJpUtoMKsNN/FDFSqWJlgp0zeRQ65iHhT4sfrLTDsz9jrri Vvs3i4PT7xzhEgz6KHVs941Ja4ijaVF7fxPpoaPRnD+Pq1hCPmwNSyDOue7yPSp4bjFb iTRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PKihwxIr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v2 08/12] target/arm: Set btype for indirect branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dbac09743c..89cc54dbed 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -138,6 +138,19 @@ static void reset_btype(DisasContext *s) } } +static void set_btype(DisasContext *s, int val) +{ + TCGv_i32 tcg_val; + + /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ + tcg_debug_assert(val >= 1 && val <= 3); + + tcg_val = tcg_const_i32(val); + tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); + tcg_temp_free_i32(tcg_val); + s->btype = -1; +} + void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -1982,6 +1995,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; + unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ TCGv_i64 dst; TCGv_i64 modifier; @@ -1999,6 +2013,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) case 0: /* BR */ case 1: /* BLR */ case 2: /* RET */ + btype_mod = opc; switch (op3) { case 0: /* BR, BLR, RET */ @@ -2042,7 +2057,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc == 1) { @@ -2058,6 +2072,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) if (op3 != 2 || op3 != 3) { goto do_unallocated; } + btype_mod = opc & 1; if (s->pauth_active) { dst = new_tmp_a64(s); modifier = cpu_reg_sp(s, op4); @@ -2141,6 +2156,26 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) return; } + switch (btype_mod) { + case 0: /* BR */ + if (dc_isar_feature(aa64_bti, s)) { + /* BR to {x16,x17} or !guard -> 1, else 3. */ + set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); + } + break; + + case 1: /* BLR */ + if (dc_isar_feature(aa64_bti, s)) { + /* BLR sets BTYPE to 2, regardless of source guarded page. */ + set_btype(s, 2); + } + break; + + default: /* RET or none of the above. */ + /* BTYPE will be set to 0 by normal end-of-insn processing. */ + break; + } + s->base.is_jmp = DISAS_JUMP; } From patchwork Mon Jan 28 22:31:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156899 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3959442jaa; Mon, 28 Jan 2019 14:42:50 -0800 (PST) X-Google-Smtp-Source: ALg8bN69RBA0jl6B2UTmcYmq51geMjJJY/vHc2rFcRWBXBu51kw91oSpU7GyayXhNFF9ogAEp0lS X-Received: by 2002:a1c:cc2:: with SMTP id 185mr19387304wmm.1.1548715370814; Mon, 28 Jan 2019 14:42:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715370; cv=none; d=google.com; s=arc-20160816; b=u7sZPGm/A61zbcxSkFELUc9pJKRjiMo4MTcwrLzcYLDaNgITxsCJbV9UVPRE7FBiKo tU8cGqxbEEuyG0bAKHZGiMvPFsk8/pYYdweyjEopDWnoIps2vRd/PsDtCtObQp8rlqb9 EkNR1FY/FxUAn0xaHlTIv0HRuomoCZ6eTGk7WGLAZoT8lzRI/tQV3kyW95GahqYSgCJn PZJOy2GuAiqSedRdhr09U9Sjm58yshKM+Hr+IUKMaEhVOk656upK0LfG4Kmwh6thKdNL F0yGZzH7tbdCxm0CSUGa6vKhFq4agyVO1AYrXB+aP9ApzZ6sgcnaOMk/hrJtpqNRe9hq n1wQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Srgal5L+T4f9BJA308PnBpjmkpNAduRiPZ7ATLTRwkQ=; b=aMb0Hjpa60GOHyHdUFIPwk7K0jUqh2CRfhBICnFDpOdkO54axIAl/5J4Ommlw3iUwT gRD54jbtbMSSPTa2jGhcpI1urW1dtISTzb43M1F+IsYNnHsPNdHz+J13lT7irqSBnahZ /rYlAVeVxzE4S54as7tWOoWGpvm4TBPmX5hqJJWdDEkl1JBpD4Jjuk8V0cqBtm5nXnui lmBzZpzrjmB25IEh4tFBTre46VLOYP+mwkBca5kOPglzifQ6d8uu8WTIFVaY2EUvKXiM dArODFF1YKh5i8Lvf4b16sWRVIL69FT0Kr21f6ZXad0GIcrbRNo/bwu9rTjdmGPA8Gik QMRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="RCl/BXog"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t132si533194wmd.119.2019.01.28.14.42.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:42:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="RCl/BXog"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39574 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFc9-0006jp-Ai for patch@linaro.org; Mon, 28 Jan 2019 17:42:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFbq-0006iZ-Dx for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRP-0006HX-09 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:44 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:35289) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRN-0006EV-HY for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:42 -0500 Received: by mail-oi1-x241.google.com with SMTP id v6so14531168oif.2 for ; Mon, 28 Jan 2019 14:31:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Srgal5L+T4f9BJA308PnBpjmkpNAduRiPZ7ATLTRwkQ=; b=RCl/BXogUyRAExfZa+W/Gw9RrHscv7PKc3rJQ7rXYxB4Yzzvoenr7ayW4Dj1Wg0f6n J3IJ8xDBWQMj7Nm8ilIe6ZbI98aYFcqLHQ28FSEWs4OsTWZ0FEHoT9kaAbna9pR7WR5K MS4conjzW3IJ2kvIutc9M74mIdZ0RQo7R3y0E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Srgal5L+T4f9BJA308PnBpjmkpNAduRiPZ7ATLTRwkQ=; b=HAiRQSMKifUX+PSP4ZNi8QJ8MwxYwIVgcayKttc1QryHObG0jbaIuvTRX8RSY14ZgC sbkoa9eCBReXAi1Y4PxTvbkJVqP73cxX2UrZdwwTkPsToRYLFsJqXhPDCw4X77DE4GdL rPAwS1YyjOwkCiSTad+TWS5mYpd1Nijl0k7zHRCDuuhqH2euQFRRVn1BVLvtj8IrdWJa SCsbIKtvgx5WX0jW6HXhtoPvbVKZ9Q58VdFue7T7Ddyt7MbW6lciec7nrU6Gr4+/0n0K Yqw+QmVSrQ4tkTvJ6sAvtLjaevq46nyNk7QQ1WXQIwTmZGNfz/MuxACDcZzz1KR0o64K yzjg== X-Gm-Message-State: AJcUukdPmr3x3+71OcPGM15P6/gHNt4wkW3TV1KHGc0s8RYNZ1hTd+hT f3coeQDsUzn0b/kgBPbk3/VHBFb8NQE= X-Received: by 2002:a54:4f8f:: with SMTP id g15mr7662915oiy.166.1548714695462; Mon, 28 Jan 2019 14:31:35 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:15 -0800 Message-Id: <20190128223118.5255-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 09/12] target/arm: Add x-guarded-pages cpu property for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While waiting for a proper userland ABI, allow static test cases to be written assuming that GP is set for all pages. Signed-off-by: Richard Henderson --- v2: Renamed the property with x- prefix --- target/arm/cpu.h | 4 ++++ target/arm/cpu64.c | 18 ++++++++++++++++++ target/arm/translate-a64.c | 8 +++++++- 3 files changed, 29 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e18f823419..8c9eb519ef 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -895,6 +895,10 @@ struct ARMCPU { */ bool cfgend; +#ifdef CONFIG_USER_ONLY + bool guarded_pages; +#endif + QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e9bc461c36..a563f7e74d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -311,6 +311,18 @@ static void cpu_max_set_packey(Object *obj, Visitor *v, const char *name, } error_propagate(errp, err); } + +static bool aarch64_cpu_get_guarded_pages(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu->guarded_pages; +} + +static void aarch64_cpu_set_guarded_pages(Object *obj, bool val, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + cpu->guarded_pages = val; +} #endif /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); @@ -416,6 +428,12 @@ static void aarch64_max_initfn(Object *obj) cpu->env.cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB; cpu->env.cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB; } + + object_property_add_bool(obj, "x-guarded-pages", + aarch64_cpu_get_guarded_pages, + aarch64_cpu_set_guarded_pages, NULL); + object_property_set_description(obj, "x-guarded-pages", + "Set on/off GuardPage bit for all pages", NULL); #endif cpu->sve_max_vq = ARM_MAX_VQ; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 89cc54dbed..a1adb8cde0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13778,7 +13778,13 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) static bool is_guarded_page(CPUARMState *env, DisasContext *s) { #ifdef CONFIG_USER_ONLY - return false; /* FIXME */ + /* + * FIXME: What is the userland ABI for this? + * For the moment this is controlled by an attribute: + * -cpu max,guarded_pages=on. + */ + ARMCPU *cpu = arm_env_get_cpu(env); + return cpu->guarded_pages; #else uint64_t addr = s->base.pc_first; int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); From patchwork Mon Jan 28 22:31:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156905 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3964116jaa; Mon, 28 Jan 2019 14:49:29 -0800 (PST) X-Google-Smtp-Source: ALg8bN5Lke5vfrEjQSdEeXvjzFd19u7mnFMlr8bkKhesRca0We6o2QERpLGG/fRKTPPaoYg7lwZg X-Received: by 2002:a1c:864f:: with SMTP id i76mr18263401wmd.83.1548715769823; Mon, 28 Jan 2019 14:49:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715769; cv=none; d=google.com; s=arc-20160816; b=EjnkLuD622rdO+gjTjCIt/GGUk8xsuzhdzlsA7wJlgaO2qylvCX/wnc6gkOOUkgRP8 jWQAL7G7sNT8ReaVC1Yg2Tv+lVFplPEsutDcQjL+SIuNnxexCrDil2mg/MpcCnuCSFZA eyiYnTgFDW6jkQP8pqH9f3QVl3GIHQkleVuFAAfde2qRjoPhuYKpUZlnmhpCdCBfxREZ oYje3OiG7hdEx3phkM3DC8XSBbU0HHrTz1QbwiYdCS7YSTfhl8WapAUMYYP05NU10c0m rLshu4SfLgFJvMvNJaALHgWI2auOxZpyWYfB8jm+Bd86e83godHBdbagnIe50H76lC0Z EjWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=UKRLKQXKGzj/mpvH/wYH3nx2J6OhgQcb+mzh4u+p648=; b=SzwMcWEo+EXjTB6bPjG9dWNwAvCz4sAa61aXoNPs7TP42sel/wQFo5IHq3JZMwF37r YWOpXUdR/Bh1fhbYcMNwBPuQBXsWPzr0lBWY/p604yp3aJr1MYGwjGOZdeBKOJRWKsn+ aReaKvnXDpv6Mts6O1jef5i1dXdwxfKyjsoTCZWHtsLGTmM9LnvX9pH6IEW8B7V2fVgO pW1e5b62KEUOJ44pY38tyDKpkaDpd3ei8fouqgKovff2qhwAoObkdESjEYhboA+lljd7 2H0z9UT5dH5Vzpgl4HzEHN+Vfi7emPy/kN+P5BttGrF2eeFgfwhYmrx+zf+zJUinw/HI aHlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="MJqd9/nq"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n123si530965wmb.157.2019.01.28.14.49.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:49:29 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="MJqd9/nq"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39673 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFia-0003DC-LN for patch@linaro.org; Mon, 28 Jan 2019 17:49:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcB-0006rk-8s for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRP-0006Hc-0G for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:44 -0500 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]:33433) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRM-0006El-R4 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:42 -0500 Received: by mail-oi1-x232.google.com with SMTP id c206so14560594oib.0 for ; Mon, 28 Jan 2019 14:31:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UKRLKQXKGzj/mpvH/wYH3nx2J6OhgQcb+mzh4u+p648=; b=MJqd9/nqGh1FTKSLgOvy5IWkD+S4mxf/3Mwwz0uhj5uQehZuAJ4hxNl7Un0GFG6DtY HpcGQ+xmhbBzxLn5yY6LLmhyeLPULiwuGBYHxWByAYwfjL1aFTPWnOkMqhUox7Vjs9FD YkSpRST2q9GsZbeOBSAOrtuIEVJAmH5Ji7aTk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UKRLKQXKGzj/mpvH/wYH3nx2J6OhgQcb+mzh4u+p648=; b=HiaR2eTJgDC9Aos+EjxslUcBlnTCJc5TA8pKGdpN9USObLZMGoGMYHc1/eBOe/5sqD tv7mhmKjckL82RZakgRfiOmWMECfCrnXiZX2iH61ua8nOY8foArKsHoelG0YSxWPpGcU 7LWenoIG9fOAvN0t4w55pT8OKC1Kuf2eKGhG1bNi5y0fmjvFJ50vP7eKrVwJczr7dbpX 4HKYil15c0F/HZO36EsmiCIqz03OFnhcyWfrtOAMlg91CDzQWpytmwX4FP4lXAYWp36m Qow93cZKRhOpXDCyzuPNIwRaQTVbEIvVhi0pHsvINwpWg2h4U7vQbZOYCVlGaEez192H KK9w== X-Gm-Message-State: AJcUukdfysur4JSpmOfW1aQ8E5weo/MUKDOahjAajGDrriT2a32ftljd 8yltYmas2b4/fcxmrxeonsCjU4t8egE= X-Received: by 2002:aca:c142:: with SMTP id r63mr7565867oif.98.1548714696544; Mon, 28 Jan 2019 14:31:36 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:16 -0800 Message-Id: <20190128223118.5255-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::232 Subject: [Qemu-devel] [PATCH v2 10/12] target/arm: Enable BTI for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a563f7e74d..9d2276fe53 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -368,6 +368,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); cpu->isar.id_aa64pfr0 = t; + t = cpu->isar.id_aa64pfr1; + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + cpu->isar.id_aa64pfr1 = t; + t = cpu->isar.id_aa64mmfr1; t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); From patchwork Mon Jan 28 22:31:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156910 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3971009jaa; Mon, 28 Jan 2019 14:59:30 -0800 (PST) X-Google-Smtp-Source: ALg8bN4RVK7ys4ESYFv09LYA589JDa1l/ziDQwdbNtTaYSJgndmPQzaKbrzG9SDtEZwK+0CsQEvc X-Received: by 2002:a1c:3d44:: with SMTP id k65mr18544295wma.76.1548716370484; Mon, 28 Jan 2019 14:59:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548716370; cv=none; d=google.com; s=arc-20160816; b=hC7m9Z37Gco8ZI/FADBihIolx4wn9G3jO7keE/49tx0TlEirKOkzHetUZcmDXupDET t7idPVwnLEcgPMlAE9nvEBkQaouO9WgcQLjC9Y0f9xt1n2i165PYIO+r+C8NvoiFao21 FrqQu5/YSZMoxXl52e/bItHtteNLs7KW7e/TFsGdHyVA5ha5fDoEg++Dun1yBnZIHxu2 HSFtioSB+Q//U2YSWcTD671aJaVMTjEFQuuYuZDzGZ9YyYWsLDypj6V4rovV+4BL5qaD TabM7YyvEXBeVIcx6UEcXv70mPR2Ll+Hkya2mk6txqN3ZMlIj9HK191dOSLyRJGLZt6s iJ5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=FU6VM0/bn2KGW7WbYepledET8E6WIGztTULH/WAiw80=; b=jZCu5Kz0u25ZTj2gmYUnfvrqRWdMOZg1BSzW/h1MyssdJ9tpP24twQtUbAVV2KGpq6 AzMM1oCfEyVebkOdpNuqHqAofM5earcTgauTMC5QJt5jvHLMau1FQyaNo2lI62q2Jq9v IO/6tDeZ5V3wN/MboQTnaUthMHPpKJwAYyqkLZAN7/ZEBxHuDTpTS2J1AOVrNc92Eh// 1ThUU4gWf522sy70KTUNkTVIt799WdOIOGcEEPH2N12ZUaxnCnCPVXD1VItL7fYsqgMZ B7vWxznZRviqT2rrA0KcQT+zCXrRzjdIwOsMOEZCw0CGUzHWk6By2NvGoVe8q8VlSGaB lfXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kpVei5F9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v10si12140652wre.30.2019.01.28.14.59.30 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:59:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kpVei5F9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39816 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFsH-0001kL-G5 for patch@linaro.org; Mon, 28 Jan 2019 17:59:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcB-0006rk-W3 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRM-0006GX-SR for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:42 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:36376) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRM-0006FK-4s for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:40 -0500 Received: by mail-oi1-x243.google.com with SMTP id x23so14513399oix.3 for ; Mon, 28 Jan 2019 14:31:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FU6VM0/bn2KGW7WbYepledET8E6WIGztTULH/WAiw80=; b=kpVei5F9kQzPwTdj5e9fE6LMjw1LhU/qyOtcgW7/gpbtlQGB71ElE1LabPft9VaW78 NMKz7u8xzNL44A7DMIc3v/+5XaxSQHQEiMsfn/aFZuqrCYJ5VrnwDirF0bKeWap3EYZQ tYB5sfxzylbRpf0KNO7t1dnlw8ApUHhDoY6U8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FU6VM0/bn2KGW7WbYepledET8E6WIGztTULH/WAiw80=; b=Mo0qw28cx4kRBnR3xY0bBHZ1cMpS0NscQnfOKqNkSS3geGbFRBM305ai4YchHRZD68 3rxvYt7358L2DO7NlyEv/4/ErnpH/fUcifvLdqu96yUXYdYF6EwP0T7Hh8UQD7nj4p+d Hcj2AtLRziU1WpStimFiT/WjUDMeTptaJy1dsv8e74IpBMq2iDbPYUIxbHCWPiX5Juw5 G+KCJf3xngn2ibYnYLBY1PyI6Rb6aHQeojuJEwOsAfhyrc/mHDv6lxVE97btsfHkLVP2 XRKOQwY1NRue1neU6eNK9OOQ6UbKFWKT814b4rWtn5aFU33RC5oQG9pUeioKWjZMID+p MsSg== X-Gm-Message-State: AJcUukdrzfaz+SFXXQNygUEDouu25jNqYUrrN+sBRDW2nzUQigfNRtyy MXd1OzIpsZypo+rw2JzkNm6yIHaJ2Mg= X-Received: by 2002:aca:1702:: with SMTP id j2mr7536584oii.267.1548714697762; Mon, 28 Jan 2019 14:31:37 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:17 -0800 Message-Id: <20190128223118.5255-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v2 11/12] linux-user/aarch64: Reset btype for syscalls and signals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The value of btype for syscalls is CONSTRAINED UNPREDICTABLE, so we need to make sure that the value is 0 before clone, fork, or syscall return. The value of btype for signals is defined, but it does not make sense for a SIGILL handler to enter with the btype set as for the indirect branch that caused the SIGILL. Clearing the value early means that btype is zero within the pstate saved into the signal frame, and so is also zero on (normal) signal return, but also allows the signal handler to adjust the value as seen after the sigcontext restore. This last is a guess at a future kernel's user-space ABI. Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.2 diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 65d815f030..51ea9961ba 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -83,8 +83,19 @@ void cpu_loop(CPUARMState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); + /* + * The state of BTYPE on syscall and interrupt entry is CONSTRAINED + * UNPREDICTABLE. The real kernel will need to tidy this up as well. + * Do this before syscalls and signals, so that the value is correct + * both within signal handlers, and on return from syscall (especially + * clone & fork) and from signal handlers. + * + * The SIGILL signal handler, for BTITrap, can see the failing BTYPE + * within the ESR value in the signal frame. + */ switch (trapnr) { case EXCP_SWI: + env->btype = 0; ret = do_syscall(env, env->xregs[8], env->xregs[0], @@ -104,6 +115,7 @@ void cpu_loop(CPUARMState *env) /* just indicate that signals should be handled asap */ break; case EXCP_UDEF: + env->btype = 0; info.si_signo = TARGET_SIGILL; info.si_errno = 0; info.si_code = TARGET_ILL_ILLOPN; @@ -112,6 +124,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: + env->btype = 0; info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; /* XXX: check env->error_code */ @@ -121,12 +134,14 @@ void cpu_loop(CPUARMState *env) break; case EXCP_DEBUG: case EXCP_BKPT: + env->btype = 0; info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: + env->btype = 0; env->xregs[0] = do_arm_semihosting(env); break; case EXCP_YIELD: From patchwork Mon Jan 28 22:31:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156903 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3961769jaa; Mon, 28 Jan 2019 14:46:06 -0800 (PST) X-Google-Smtp-Source: ALg8bN7rsR3KVDsL6+YndPxj64MM4J2o/TJLYQuvZdpNd2KQqHS8mnis/gMDfwXPzrBNYVz7r1YL X-Received: by 2002:a5d:494a:: with SMTP id r10mr24138170wrs.272.1548715566406; Mon, 28 Jan 2019 14:46:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548715566; cv=none; d=google.com; s=arc-20160816; b=irBL7BjBx+OavvrnQLZ8Ry14iWuyfjeiWp+fR1vXqmWf4CwIi2xFkrxGoc+J79Fwvu Bj0smhwtyGnvnOurXICLLt7XpcLw6ndV6lONd3OokDjvtEE+D7Ho60V/C2smCnlmicyq oBr++FYWoVJHhfuKVEJLfiLFued6oOfv8iWleVc9KsnrnMxLx2iwh7Wwj5WWYwLCQfpR sVKpnSx95SvkR7kPh91EddIsS224JsnwGDDF7Zh/YZ/GVBcDx9FIVgf/aV6YeSBOQq7F fLHp9LGPCPyjKY2LhTHS39ibrWagi3OaYcbanHMoqXEzObdFOU+dD0a1E+n2JJGVrU2a HYdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=y0k/H38xJNqLR/HphofIOtky77ujQ33o+YBmpOTNSTs=; b=IUKK0u4uxfWW2uIGk8SABZyodT3cULVeNqu3fM8hp0OISCga2I05uHxMYjjnXdCoCt Sm2fnuiSUCM6k7EISwl5hDJLkPUpS1PBQ2dpKb5wMCnLYTjvcN2gypFTnWpS1OV4BGd7 5pqOIcmvSLJcuCwaJ5x2AsYjPzU4PlSptA/sh5pzoIAwGE0oIzeqWJPEFFcTedIkeVk1 h8DgWT4SwzRN3XM2nlIf0TGTqHCblus13t1wPTptpwf3oDCBPMn7ehG3BVes7E2NyGan SWPW6nM9k13FN1ku107z4/7+kY5KIE2hgSkk/4JXtqHRIIccdLuJ5ksCfKq2ME8KB6BO FCBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=D9WGvklm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v2 12/12] tests/tcg/aarch64: Add bti smoke test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/bti-1.c | 61 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/bti-crt.inc.c | 51 ++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 7 +++- 3 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/bti-1.c create mode 100644 tests/tcg/aarch64/bti-crt.inc.c -- 2.17.2 diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c new file mode 100644 index 0000000000..fa8a521a47 --- /dev/null +++ b/tests/tcg/aarch64/bti-1.c @@ -0,0 +1,61 @@ +/* + * Branch target identification, basic notskip cases. + */ + +#include "bti-crt.inc.c" + +static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) +{ + uc->uc_mcontext.pc += 8; +} + +#define NOP "nop" +#define BTI_N "hint #32" +#define BTI_C "hint #34" +#define BTI_J "hint #36" +#define BTI_JC "hint #38" + +#define BTYPE_1(DEST) \ + asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16") + +#define BTYPE_2(DEST) \ + asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16", "x30") + +#define BTYPE_3(DEST) \ + asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x15") + +#define TEST(WHICH, DEST, EXPECT) \ + do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0) + + +int main() +{ + int fail = 0; + int skipped; + + /* Signal-like with SA_SIGINFO. */ + signal_info(SIGILL, skip2_sigill); + + TEST(BTYPE_1, NOP, 1); + TEST(BTYPE_1, BTI_N, 1); + TEST(BTYPE_1, BTI_C, 0); + TEST(BTYPE_1, BTI_J, 0); + TEST(BTYPE_1, BTI_JC, 0); + + TEST(BTYPE_2, NOP, 1); + TEST(BTYPE_2, BTI_N, 1); + TEST(BTYPE_2, BTI_C, 0); + TEST(BTYPE_2, BTI_J, 1); + TEST(BTYPE_2, BTI_JC, 0); + + TEST(BTYPE_3, NOP, 1); + TEST(BTYPE_3, BTI_N, 1); + TEST(BTYPE_3, BTI_C, 1); + TEST(BTYPE_3, BTI_J, 0); + TEST(BTYPE_3, BTI_JC, 0); + + return fail; +} diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.inc.c new file mode 100644 index 0000000000..ef7831ad76 --- /dev/null +++ b/tests/tcg/aarch64/bti-crt.inc.c @@ -0,0 +1,51 @@ +/* + * Minimal user-environment for testing BTI. + * + * Normal libc is not built with BTI support enabled, and so could + * generate a BTI TRAP before ever reaching main. + */ + +#include +#include +#include +#include + +int main(void); + +void _start(void) +{ + exit(main()); +} + +void exit(int ret) +{ + register int x0 __asm__("x0") = ret; + register int x8 __asm__("x8") = __NR_exit; + + asm volatile("svc #0" : : "r"(x0), "r"(x8)); + __builtin_unreachable(); +} + +/* + * Irritatingly, the user API struct sigaction does not match the + * kernel API struct sigaction. So for simplicity, isolate the + * kernel ABI here, and make this act like signal. + */ +void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *)) +{ + struct kernel_sigaction { + void (*handler)(int, siginfo_t *, ucontext_t *); + unsigned long flags; + unsigned long restorer; + unsigned long mask; + } sa = { fn, SA_SIGINFO, 0, 0 }; + + register int x0 __asm__("x0") = sig; + register void *x1 __asm__("x1") = &sa; + register void *x2 __asm__("x2") = 0; + register int x3 __asm__("x3") = sizeof(unsigned long); + register int x8 __asm__("x8") = __NR_rt_sigaction; + + asm volatile("svc #0" + : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory"); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 08c45b8470..b529a8c9c9 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,10 +8,15 @@ VPATH += $(AARCH64_SRC) # we don't build any of the ARM tests AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) AARCH64_TESTS+=fcvt -TESTS:=$(AARCH64_TESTS) fcvt: LDFLAGS+=-lm run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) + +AARCH64_TESTS += bti-1 +bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib +run-bti-1: QEMU += -cpu max,x-guarded-pages=on + +TESTS:=$(AARCH64_TESTS)