From patchwork Sun Jul 24 17:10:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 594176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6116AC43334 for ; Sun, 24 Jul 2022 17:11:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229469AbiGXRLO (ORCPT ); Sun, 24 Jul 2022 13:11:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229542AbiGXRLN (ORCPT ); Sun, 24 Jul 2022 13:11:13 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 958EF6568 for ; Sun, 24 Jul 2022 10:11:11 -0700 (PDT) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id BAE9A82119; Sun, 24 Jul 2022 19:11:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1658682669; bh=P0Zh7M6+7SwBXtsauIfRW+58aUCtGChVQAC86ph7HS4=; h=From:To:Cc:Subject:Date:From; b=ZHL/DZlmwDJYt4EmVigMi1gvlKXPSZgYR9laEbIbCeqAVtgTdOXf/3uqNsbRyFj8Y qpS8wfn0QTvOa5iENdf4LUtc/u95q1v0HE/nPXtI8GEDuHZF1Vp0ex/wZrQg07i8ER V7KbcbSLTa1i4l28LM5ZhQWSy+2bU4DFsYXgv6VJGtxSmKJynidHuY/Xq9KBudhoO9 A4nEZhBGdBn6K70UWELOYv8nZBL2ibQYOUl00e7L+dkliuDqVGpqlwscTMMgbVVmOH kMslcBJxGZco+wG7HSfMJFpS+IG9GCGYmJDkb7kWfhhgLtjdldqBN83Og/Zasld50U KvspFAec/fjAw== From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: Marek Vasut , Bartosz Golaszewski , Linus Walleij , Loic Poulain , Marc Zyngier , NXP Linux Team , Peng Fan , Shawn Guo Subject: [PATCH v3 1/2] gpio: mxc: Protect GPIO irqchip RMW with bgpio spinlock Date: Sun, 24 Jul 2022 19:10:56 +0200 Message-Id: <20220724171057.18549-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The driver currently performs register read-modify-write without locking in its irqchip part, this could lead to a race condition when configuring interrupt mode setting. Add the missing bgpio spinlock lock/unlock around the register read-modify-write. Fixes: 07bd1a6cc7cbb ("MXC arch: Add gpio support for the whole platform") Signed-off-by: Marek Vasut Cc: Bartosz Golaszewski Cc: Linus Walleij Cc: Loic Poulain Cc: Marc Zyngier Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo --- V3: New patch --- drivers/gpio/gpio-mxc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c871602fc5ba9..74a50139c9202 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -147,6 +147,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; + unsigned long flags; u32 bit, val; u32 gpio_idx = d->hwirq; int edge; @@ -185,6 +186,8 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) return -EINVAL; } + spin_lock_irqsave(&port->gc.bgpio_lock, flags); + if (GPIO_EDGE_SEL >= 0) { val = readl(port->base + GPIO_EDGE_SEL); if (edge == GPIO_INT_BOTH_EDGES) @@ -204,15 +207,20 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) writel(1 << gpio_idx, port->base + GPIO_ISR); + spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); + return 0; } static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) { void __iomem *reg = port->base; + unsigned long flags; u32 bit, val; int edge; + spin_lock_irqsave(&port->gc.bgpio_lock, flags); + reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ bit = gpio & 0xf; val = readl(reg); @@ -230,6 +238,8 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) return; } writel(val | (edge << (bit << 1)), reg); + + spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); } /* handle 32 interrupts in one status register */ From patchwork Sun Jul 24 17:10:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 593218 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD5A6C433EF for ; Sun, 24 Jul 2022 17:11:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229546AbiGXRLO (ORCPT ); Sun, 24 Jul 2022 13:11:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229469AbiGXRLN (ORCPT ); Sun, 24 Jul 2022 13:11:13 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95C0E6575 for ; Sun, 24 Jul 2022 10:11:11 -0700 (PDT) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 2B96F83FDA; Sun, 24 Jul 2022 19:11:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1658682669; bh=h/8grsXnnr3I67hGx18SXoCceX/Rg7Cy2VUpbzrmjgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aXXQmiXA9bQmoZokWfVXl8JwpmLzqukxl7OHQEqEkZpRaPqkTOQHcrluiGOifUWg2 +p/tdZKf6GFrDrWH8WZbfb+EwVTc8nstmtmLiJu1Rkw2eUxZ6iCY3N3kPUQgqRzZvs nYecwIq2eSxegUP2ypR/oKYB49+j+eGUw9GbZZ0e+CWT+C+wOf5MfG+QHQiO5v3EAb uq3xQWesvXy7CrmJq+u5bVpgT050iUmGLXC/IkyodMdn2OsASRQ2f1lo62N4iTKDr8 /FVf92S5Dk5OHShlNMEDl6J4AusFr5RbGECOy3jC0BIp0k1LaDhXlTynzGmmG6bhG0 TqpLNLdIe+9ig== From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: Marek Vasut , Bartosz Golaszewski , Linus Walleij , Loic Poulain , Marc Zyngier , NXP Linux Team , Peng Fan , Shawn Guo Subject: [PATCH v3 2/2] gpio: mxc: Always set GPIOs used as interrupt source to INPUT mode Date: Sun, 24 Jul 2022 19:10:57 +0200 Message-Id: <20220724171057.18549-2-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220724171057.18549-1-marex@denx.de> References: <20220724171057.18549-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Always configure GPIO pins which are used as interrupt source as INPUTs. In case the default pin configuration is OUTPUT, or the prior stage does configure the pins as OUTPUT, then Linux will not reconfigure the pin as INPUT and no interrupts are received. Always configure interrupt source GPIO pin as input to fix the above case. Fixes: 07bd1a6cc7cbb ("MXC arch: Add gpio support for the whole platform") Signed-off-by: Marek Vasut Cc: Bartosz Golaszewski Cc: Linus Walleij Cc: Loic Poulain Cc: Marc Zyngier Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo --- V2: Actually update and clear bits in GDIR register V3: Rebase on top of new patch 1/2, expand CC list, add Fixes tag --- drivers/gpio/gpio-mxc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 74a50139c9202..945e8a2efb896 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -148,7 +148,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; unsigned long flags; - u32 bit, val; + u32 bit, val, dir; u32 gpio_idx = d->hwirq; int edge; void __iomem *reg = port->base; @@ -207,6 +207,10 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) writel(1 << gpio_idx, port->base + GPIO_ISR); + dir = readl(port->base + GPIO_GDIR); + dir &= ~BIT(gpio_idx); + writel(dir, port->base + GPIO_GDIR); + spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); return 0;