From patchwork Mon Jul 25 10:34:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 594173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1279C43334 for ; Mon, 25 Jul 2022 10:35:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232971AbiGYKfH (ORCPT ); Mon, 25 Jul 2022 06:35:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232320AbiGYKfF (ORCPT ); Mon, 25 Jul 2022 06:35:05 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BC1D18360 for ; Mon, 25 Jul 2022 03:35:04 -0700 (PDT) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id A394684065; Mon, 25 Jul 2022 12:35:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1658745302; bh=1IpjuDnYDqITLcAoz6lQlvw+NfYvcQMou44Zke8oRYI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rkMa6xtT92KR8gq+DSjd//3EN1rzmxjt1AB5OYSXErv0+gkfQ4d3t1jaiU3sXC7a6 qM6GUggDGob8UNCkLIAGqyo8tzRmNcZ4OUvGbN026K4BO8o25YwAjOld2j3k28PkAV ZISgZ4qvzgtbMBbsDyKYUosdYI7Z/6iNHl0sznFdQPhFlwF5qMR/xyJ8VIaHj55yEh +ysHKWeXPijUeGv5CMl5CQjLYPppD9oeY3RTcP4BOk0Kj28HKVLXbXwa351sG5uOd+ pIL12gTlhL0nWmaHRGzN+ge+8N8z9Biifm8+1LrruwGAB7TCKBVvTH8ijSzmtoMYrt AP4rOnUpJWhgQ== From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: Marek Vasut , Bartosz Golaszewski , Linus Walleij , Loic Poulain , Marc Zyngier , NXP Linux Team , Peng Fan , Shawn Guo Subject: [PATCH v5 1/2] gpio: mxc: Protect GPIO irqchip RMW with bgpio spinlock Date: Mon, 25 Jul 2022 12:34:44 +0200 Message-Id: <20220725103445.88674-2-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220725103445.88674-1-marex@denx.de> References: <20220725103445.88674-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The driver currently performs register read-modify-write without locking in its irqchip part, this could lead to a race condition when configuring interrupt mode setting. Add the missing bgpio spinlock lock/unlock around the register read-modify-write. Fixes: 07bd1a6cc7cbb ("MXC arch: Add gpio support for the whole platform") Signed-off-by: Marek Vasut Cc: Bartosz Golaszewski Cc: Linus Walleij Cc: Loic Poulain Cc: Marc Zyngier Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo --- V3: New patch V4: Include linux/spinlock.h V5: Use raw_spinlock per 3c938cc5cebcb ("gpio: use raw spinlock for gpio chip shadowed data") --- drivers/gpio/gpio-mxc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c871602fc5ba9..6cc98a5684ae1 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -147,6 +148,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; + unsigned long flags; u32 bit, val; u32 gpio_idx = d->hwirq; int edge; @@ -185,6 +187,8 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) return -EINVAL; } + raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); + if (GPIO_EDGE_SEL >= 0) { val = readl(port->base + GPIO_EDGE_SEL); if (edge == GPIO_INT_BOTH_EDGES) @@ -204,15 +208,20 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) writel(1 << gpio_idx, port->base + GPIO_ISR); + raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); + return 0; } static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) { void __iomem *reg = port->base; + unsigned long flags; u32 bit, val; int edge; + raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); + reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ bit = gpio & 0xf; val = readl(reg); @@ -230,6 +239,8 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) return; } writel(val | (edge << (bit << 1)), reg); + + raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); } /* handle 32 interrupts in one status register */ From patchwork Mon Jul 25 10:34:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 593366 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C7C9CCA48B for ; Mon, 25 Jul 2022 10:35:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233861AbiGYKfI (ORCPT ); Mon, 25 Jul 2022 06:35:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233071AbiGYKfF (ORCPT ); Mon, 25 Jul 2022 06:35:05 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2FDF18364 for ; Mon, 25 Jul 2022 03:35:04 -0700 (PDT) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 3EAAE84072; Mon, 25 Jul 2022 12:35:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1658745302; bh=d8WkBKyRBCXmmezC0HF4qr+mk0gBNxOFL3vyoYeOsdo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VS9A3SwoVJDhQQGDMxMLCKATkWdqSJ+9kcV5VeVHi6EHG1mPDX0GyZ5YV+8ou+Ito Vqy9mhKWs08bR3ubYCu0Z019YO4rZIsUWfhFwUCTssHlAmqNBVZbKSeyuzGK61B711 YEPyxzMMg1tR9FZeNwx11d37uQ89r+cNZdC9PJPO2gLVVrbWlVlazCny7la8bGIANw EGUv9i3quUoZ/tMplWMvbE08+5f//UCR6r0NP0UHabzJ0sxZNRQBfPbTWVYHUKmCEp jZGgEBxUepiTrAUa08NfncwHTsX4JH2pg0LXabTig7vjMtWrsaHjYhk/AUsmq3GMzu /7Oqewr4gL+gQ== From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: Marek Vasut , Bartosz Golaszewski , Linus Walleij , Loic Poulain , Marc Zyngier , NXP Linux Team , Peng Fan , Shawn Guo Subject: [PATCH v5 2/2] gpio: mxc: Always set GPIOs used as interrupt source to INPUT mode Date: Mon, 25 Jul 2022 12:34:45 +0200 Message-Id: <20220725103445.88674-3-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220725103445.88674-1-marex@denx.de> References: <20220725103445.88674-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Always configure GPIO pins which are used as interrupt source as INPUTs. In case the default pin configuration is OUTPUT, or the prior stage does configure the pins as OUTPUT, then Linux will not reconfigure the pin as INPUT and no interrupts are received. Always configure interrupt source GPIO pin as input to fix the above case. Fixes: 07bd1a6cc7cbb ("MXC arch: Add gpio support for the whole platform") Signed-off-by: Marek Vasut Cc: Bartosz Golaszewski Cc: Linus Walleij Cc: Loic Poulain Cc: Marc Zyngier Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo --- V2: Actually update and clear bits in GDIR register V3: Rebase on top of new patch 1/2, expand CC list, add Fixes tag V4: No change V5: No change --- drivers/gpio/gpio-mxc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 6cc98a5684ae1..95327c8963b6c 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -149,7 +149,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; unsigned long flags; - u32 bit, val; + u32 bit, val, dir; u32 gpio_idx = d->hwirq; int edge; void __iomem *reg = port->base; @@ -208,6 +208,10 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) writel(1 << gpio_idx, port->base + GPIO_ISR); + dir = readl(port->base + GPIO_GDIR); + dir &= ~BIT(gpio_idx); + writel(dir, port->base + GPIO_GDIR); + raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); return 0;