From patchwork Wed Jan 30 23:40:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 157089 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6543587jaa; Wed, 30 Jan 2019 15:41:05 -0800 (PST) X-Google-Smtp-Source: ALg8bN4Vr9TnvuE4PA0Z9BID/uWv5QZ+5zGNmkjNWiuE1PoPLilidRB48uunFjIh0tGqUdMd4VuD X-Received: by 2002:a62:e044:: with SMTP id f65mr32269445pfh.208.1548891665239; Wed, 30 Jan 2019 15:41:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548891665; cv=none; d=google.com; s=arc-20160816; b=Vqa0e/U7Y/i+coGHq5qFVcJQLwwkrGqewnw6R0hjfQ/Q/e1cFOhIJ+u/rECmnkggwO d8tvvby+aXunLNm+2GWL/l2E52+/qDljB7F05lgitN1VTnuUr2IR53UBO2F62Vi9HnwT +hxvDhzW2J+9MSycU8I4nQIYUuYlfT+JCe//SBbwaE8NwAzmK72MB8e14T5VYo7RvLbd n3ocQPUB3AEjgREyhJAWKni+Ar0ra0k2FkalKVzK21CfsyZmFJVnP7kVEFVr6SA4tY0Q MrNBp6zmsbu6HalGzfcosEgrbmmQV7/Vu/oK4ANIEvF0nAMyna+bl3kEGWiMqNKvMunp 1Jow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=va7FohJb74SnkxiSXy6OUyKOGugG7nKO/rjO0ClvdL4=; b=rKn3rs+aDdWKzULeUAR80h1C+KRAVQu1AugkIcCsSZiZqrB2Cppu350DeyyZsQQiqK V+4VHi+i400cJ1ep5S2s00M7hUREyKNxcLQ9ytXxCsJpuMmI5z7aC1qi+X+bj9UHCz6V Rg3BfUB1CUgiAAlqq1R6gLPvn56y2VHRtQc0IYvU4858BUalemenQyvV3ufNKPZlzY16 vYA8d4TUFmNEkf5RF6K7FXRWDNDmSzsn176BqDWIrE14moU00HmqfAUGBaWzGGJn3YYt qv0y5xwleHAQSXLnqjBKpN257lqvyQQ0TJKD/tNKSyCKjcuiISUiUu+nbf7QQoxzlZXo hlYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="DWfwgR/S"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q5si2700822pgg.204.2019.01.30.15.41.04; Wed, 30 Jan 2019 15:41:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="DWfwgR/S"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727579AbfA3XlD (ORCPT + 31 others); Wed, 30 Jan 2019 18:41:03 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:42970 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726915AbfA3Xk7 (ORCPT ); Wed, 30 Jan 2019 18:40:59 -0500 Received: by mail-wr1-f66.google.com with SMTP id q18so1304139wrx.9 for ; Wed, 30 Jan 2019 15:40:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=va7FohJb74SnkxiSXy6OUyKOGugG7nKO/rjO0ClvdL4=; b=DWfwgR/S65dcnqcYoUckc6KHlMzIkfG4A8idX/JzQvfSySSk+bp3uUPO7LG+ENuhJ+ vB7T8r2WOTzdvHXrOdnnfBTHwXB3ubrcgB/yEtgWtBqiWOSgTYxSr0LKnxKptFBgW0VQ EA4rm2oiXDoj35lNwruiQOFi5x9WFDmF9RxYI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=va7FohJb74SnkxiSXy6OUyKOGugG7nKO/rjO0ClvdL4=; b=CxRgNCpktXitRaBGHVKH4c9OiwaL2f3K9oTvbNAJT8sIH1Ngy1jA/WNdg/WdyeLLug zbQ4uzLUkEIMOvL7ENsliGTL+9bpPT1dVd8cJW7dswdR8AB9OyxIZ7xu8eyUpW8BSdEZ 0CXljibIf3j0ikeCNWB3T4ZFJy32IB7y46ujoppy1EoCHN3iVc7ZHv4hXJeA79aFb4eh jwOQBP9W8rM+/lOjESl//MAlk7ljUvhNpfmHQbYNqFELjgcCT5TFnSI90MtQmzv0ySAV MLya8FHGFwhmmuuga4v8oGSDM1X8nSALhmDTbf4gnvyzVPD1DZo85qYKRRaUfs/m4Dik /zQg== X-Gm-Message-State: AJcUukdxOpycxQPp4zwOmDXnSMzAA7gG/U2U/NsWhIT2uV1Q2lYWvKFE CTAKDUogEsgVyAKRGEDM9W976A== X-Received: by 2002:adf:f4c2:: with SMTP id h2mr31258198wrp.21.1548891657975; Wed, 30 Jan 2019 15:40:57 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id s3sm2344770wmj.23.2019.01.30.15.40.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 15:40:57 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Cc: linux@armlinux.org.uk, saiprakash.ranjan@codeaurora.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, arm@kernel.org Subject: [PATCH v4 1/3] drivers: amba: Updates to component identification for driver matching. Date: Wed, 30 Jan 2019 23:40:49 +0000 Message-Id: <20190130234051.2294-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190130234051.2294-1-mike.leach@linaro.org> References: <20190130234051.2294-1-mike.leach@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components. The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID. Bits 15:12 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required. This patch introduces the amba_cs_uci_id structure which will be used in all coresight drivers for indentification via the private data pointer in the amba_id structure. Existing drivers that currently use the amba_id->data pointer for private data are updated to use the amba_cs_uci_id->data pointer. Macros and inline functions are added to simplify this code. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm3x.c | 44 ++++++------------- drivers/hwtracing/coresight/coresight-priv.h | 32 ++++++++++++++ drivers/hwtracing/coresight/coresight-stm.c | 14 ++---- drivers/hwtracing/coresight/coresight-tmc.c | 30 ++++--------- include/linux/amba/bus.h | 33 ++++++++++++++ 5 files changed, 90 insertions(+), 63 deletions(-) -- 2.19.1 Tested-by: Sai Prakash Ranjan diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index fd5c4cca7db5..88c1280fdf91 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -871,7 +871,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) } pm_runtime_put(&adev->dev); - dev_info(dev, "%s initialized\n", (char *)id->data); + dev_info(dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); if (boot_enable) { coresight_enable(drvdata->csdev); drvdata->boot_enable = true; @@ -915,36 +915,18 @@ static const struct dev_pm_ops etm_dev_pm_ops = { }; static const struct amba_id etm_ids[] = { - { /* ETM 3.3 */ - .id = 0x000bb921, - .mask = 0x000fffff, - .data = "ETM 3.3", - }, - { /* ETM 3.5 - Cortex-A5 */ - .id = 0x000bb955, - .mask = 0x000fffff, - .data = "ETM 3.5", - }, - { /* ETM 3.5 */ - .id = 0x000bb956, - .mask = 0x000fffff, - .data = "ETM 3.5", - }, - { /* PTM 1.0 */ - .id = 0x000bb950, - .mask = 0x000fffff, - .data = "PTM 1.0", - }, - { /* PTM 1.1 */ - .id = 0x000bb95f, - .mask = 0x000fffff, - .data = "PTM 1.1", - }, - { /* PTM 1.1 Qualcomm */ - .id = 0x000b006f, - .mask = 0x000fffff, - .data = "PTM 1.1", - }, + /* ETM 3.3 */ + CS_AMBA_ID_DATA(0x000bb921, "ETM 3.3"), + /* ETM 3.5 - Cortex-A5 */ + CS_AMBA_ID_DATA(0x000bb955, "ETM 3.5"), + /* ETM 3.5 */ + CS_AMBA_ID_DATA(0x000bb956, "ETM 3.5"), + /* PTM 1.0 */ + CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"), + /* PTM 1.1 */ + CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"), + /* PTM 1.1 Qualcomm */ + CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"), { 0, 0}, }; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 579f34943bf1..02a1f5204f9d 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -6,6 +6,7 @@ #ifndef _CORESIGHT_PRIV_H #define _CORESIGHT_PRIV_H +#include #include #include #include @@ -159,4 +160,35 @@ static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } #endif +/* + * Macros and inline functions to handle CoreSight UCI data and driver + * private data in AMBA ID table entries, and extract data values. + */ + +/* coresight AMBA ID, no UCI, no driver data: id table entry */ +#define CS_AMBA_ID(pid) \ + { \ + .id = pid, \ + .mask = 0x000fffff, \ + } + +/* coresight AMBA ID, UCI with driver data only: id table entry. */ +#define CS_AMBA_ID_DATA(pid, dval) \ + { \ + .id = pid, \ + .mask = 0x000fffff, \ + .data = (void *)&(struct amba_cs_uci_id) \ + { \ + .data = (void *)dval, \ + } \ + } + +/* extract the data value from a UCI structure given amba_id pointer. */ +static inline void *coresight_get_uci_data(const struct amba_id *id) +{ + if (id->data) + return ((struct amba_cs_uci_id *)(id->data))->data; + return 0; +} + #endif diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 35d6f9709274..31ff4e6279bc 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -874,7 +874,7 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) pm_runtime_put(&adev->dev); - dev_info(dev, "%s initialized\n", (char *)id->data); + dev_info(dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; stm_unregister: @@ -909,16 +909,8 @@ static const struct dev_pm_ops stm_dev_pm_ops = { }; static const struct amba_id stm_ids[] = { - { - .id = 0x000bb962, - .mask = 0x000fffff, - .data = "STM32", - }, - { - .id = 0x000bb963, - .mask = 0x000fffff, - .data = "STM500", - }, + CS_AMBA_ID_DATA(0x000bb962, "STM32"), + CS_AMBA_ID_DATA(0x000bb963, "STM500"), { 0, 0}, }; diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index ea249f0bcd73..2a02da3d630f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -443,7 +443,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops = &tmc_etr_cs_ops; - ret = tmc_etr_setup_caps(drvdata, devid, id->data); + ret = tmc_etr_setup_caps(drvdata, devid, + coresight_get_uci_data(id)); if (ret) goto out; break; @@ -475,26 +476,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) } static const struct amba_id tmc_ids[] = { - { - .id = 0x000bb961, - .mask = 0x000fffff, - }, - { - /* Coresight SoC 600 TMC-ETR/ETS */ - .id = 0x000bb9e8, - .mask = 0x000fffff, - .data = (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS, - }, - { - /* Coresight SoC 600 TMC-ETB */ - .id = 0x000bb9e9, - .mask = 0x000fffff, - }, - { - /* Coresight SoC 600 TMC-ETF */ - .id = 0x000bb9ea, - .mask = 0x000fffff, - }, + CS_AMBA_ID(0x000bb961), + /* Coresight SoC 600 TMC-ETR/ETS */ + CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS), + /* Coresight SoC 600 TMC-ETB */ + CS_AMBA_ID(0x000bb9e9), + /* Coresight SoC 600 TMC-ETF */ + CS_AMBA_ID(0x000bb9ea), { 0, 0}, }; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..e3c36223e40b 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,39 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d +/* + * CoreSight Architecture specification updates the ID specification + * for components on the AMBA bus. (ARM IHI 0029E) + * + * Bits 15:12 of the CID are the device class. + * + * Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above) + * Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) + * Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support + * at present. + * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. + * + * Remaining CID bits stay as 0xb105-00d + */ + +/** + * Class 0x9 components use additional values to form a Unique Component + * Identifier (UCI), where peripheral ID values are identical for different + * components. Passed to the amba bus code from the component driver via + * the amba_id->data pointer. + * @devarch : coresight devarch register value + * @devarch_mask: mask bits used for matching. 0 indicates UCI not used. + * @devtype : coresight device type value + * @data : additional driver data. As we have usurped the original + * pointer some devices may still need additional data + */ +struct amba_cs_uci_id { + unsigned int devarch; + unsigned int devarch_mask; + unsigned int devtype; + void *data; +}; + struct clk; struct amba_device { From patchwork Wed Jan 30 23:40:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 157090 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6543604jaa; Wed, 30 Jan 2019 15:41:07 -0800 (PST) X-Google-Smtp-Source: ALg8bN6hCKuCDwucxgNM437Qfdciz4TksT6FwmPHLtsGY2l3wbjnbj07f9wBgarV+zB6Oc6Og/oA X-Received: by 2002:a63:bf0b:: with SMTP id v11mr30031893pgf.302.1548891667459; Wed, 30 Jan 2019 15:41:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548891667; cv=none; d=google.com; s=arc-20160816; b=ofEjP0HhR+2dSxa4L006+L2uAtxXVCe74N9flaVx+G4fQXyDDFyS/FZ9SCXuzCu4Mo f5rs5ijvskqsoEd2LZD4i0ZHQCGRL50X7juWW4adq31l/zgMeEA1FEs39FdRlbKJueqK vSvVMQGGM/9qODNUdqSXj0ltJiPMapmaE0mkjBD7iHCSgwjWDde8zjoZi7WwMg78HXo8 /riOFVfyqU0unsCP56KAeMOuSwrkKirqqPnCZCWsqrGt4NvNiVX1nj1rlnpaNeuIrr6V UEP1/ZoaQHKwQ4mUujogoFmtVP+6+WV54OiH4g8vzLz8qdc/7dio0S51pl84f0HPqOsd Tn+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tYoiEn3rGlYfp2djZcDtRq0G4N8SiFNVjNwRGoB1+ak=; b=okxR8Ndg9XC5+yZC84Zpojt+STZtnPcdx7YKe4MCW97fz6bSAXMmRHXOXQy4bfzLHt rTu5wzGE4uyJVVV+HxlfD0JWJWLttbpsrEy46f/TjTWsHzCZxoPgg9mQCZ+4xeebWWcX 0kmtTr4P1tRZ7bwaIft6H82HYvn7RR6nmMjGavfmloq2locdnwGJSJ/n/eDocpWOePQV U2umq2tW05n+lYvm0txmfkDZxd+EwYncbSBzSl8WTTHuX5Ls2m09y4I1xVZ/GK1nDJW/ Qx1aK4tPjWcPYj3b1yQKvl8MACvmgn7BZR7kWqJLBfdnfi6xmznmFDHpPSXI3+bDk6WD VA3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="NG/qi3r9"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q5si2700822pgg.204.2019.01.30.15.41.07; Wed, 30 Jan 2019 15:41:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="NG/qi3r9"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727959AbfA3XlG (ORCPT + 31 others); Wed, 30 Jan 2019 18:41:06 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:43824 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725768AbfA3XlA (ORCPT ); Wed, 30 Jan 2019 18:41:00 -0500 Received: by mail-wr1-f65.google.com with SMTP id r10so1296788wrs.10 for ; Wed, 30 Jan 2019 15:40:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tYoiEn3rGlYfp2djZcDtRq0G4N8SiFNVjNwRGoB1+ak=; b=NG/qi3r9Jong2qjYQkyYg6Gypld8RDdK4DWdP9KrS3GzGFcpWRvs0ZsM3JcGY14i2K 0i4gZLY4L1L3bQrFomimVnGMrlYRk9X5Lq0tjJExWFTAhGrX4vyIIOW2F2b59B1cSoul cPVjwOZCc84dqDUpvHR5vAhrEkZY2ZpHLjnEA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tYoiEn3rGlYfp2djZcDtRq0G4N8SiFNVjNwRGoB1+ak=; b=roLlYB5IoD2tOUd0HQntg9PGchFGcRwPRv/oWBvp5K1pJXNRUkp/8M1fpBFUF33e8a uanqwdxFPfqXc9Wro+CnWLe5/5kJPWMUDucpVf7qe94djdFt7Zt8/wDzwPLtjPINy1bv Ni3ffY79Og6rb1l8zu2aa7bpjgi4xVc6t+EWp1NUXDxUsK7IykTZvUj5aJhG4EGNB+aE +Lmb1MBWYtHaUCItY8FLmIYgv+GCCABtcdg1fob02sHTa5+u9+RAEZDR2rD5D8UFXZY+ dyhkG7PGuqS8Jrb3A4WxkKY5PWwktghT9BOLC/XLA6Rsm1A059P1TVyq1/6r5z3H8QAr tqNw== X-Gm-Message-State: AJcUukdYnIhFC4Fkn19nuRzorIOPRwScb8NFPmPU6RC6ibI9OYL+R5Cf gok2FmdxFIoxIpAJxlupUOepEQ== X-Received: by 2002:adf:cd0e:: with SMTP id w14mr33224434wrm.218.1548891658976; Wed, 30 Jan 2019 15:40:58 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id s3sm2344770wmj.23.2019.01.30.15.40.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 15:40:58 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Cc: linux@armlinux.org.uk, saiprakash.ranjan@codeaurora.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, arm@kernel.org Subject: [PATCH v4 2/3] drivers: amba: Update component matching to use the CoreSight UCI values. Date: Wed, 30 Jan 2019 23:40:50 +0000 Message-Id: <20190130234051.2294-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190130234051.2294-1-mike.leach@linaro.org> References: <20190130234051.2294-1-mike.leach@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching. CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information. Signed-off-by: Mike Leach --- drivers/amba/bus.c | 45 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 6 ++++++ 2 files changed, 43 insertions(+), 8 deletions(-) -- 2.19.1 diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..b4dae624b9af 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,36 @@ #define to_amba_driver(d) container_of(d, struct amba_driver, drv) -static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; + struct amba_cs_uci_id *uci; + + uci = table->data; + /* no table data or zero mask - return match on periphid */ + if (!uci || (uci->devarch_mask == 0)) + return 1; + + /* test against read devtype and masked devarch value */ + ret = (dev->uci.devtype == uci->devtype) && + ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); + return ret; +} + +static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) { - ret = (dev->periphid & table->mask) == table->id; - if (ret) - break; + if (((dev->periphid & table->mask) == table->id) && + ((dev->cid != CORESIGHT_CID) || + (amba_cs_uci_id_match(table, dev)))) + return table; table++; } - - return ret ? table : NULL; + return NULL; } static int amba_match(struct device *dev, struct device_driver *drv) @@ -399,10 +416,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8); + if (cid == CORESIGHT_CID) { + /* set the base to the start of the last 4k block */ + void __iomem *csbase = tmp + size - 4096; + + dev->uci.devarch = + readl(csbase + UCI_REG_DEVARCH_OFFSET); + dev->uci.devtype = + readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff; + } + amba_put_disable_pclk(dev); - if (cid == AMBA_CID || cid == CORESIGHT_CID) + if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid; + dev->cid = cid; + } if (!dev->periphid) ret = -ENODEV; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index e3c36223e40b..f99b74a6e4ca 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -58,6 +58,10 @@ struct amba_cs_uci_id { void *data; }; +/* define offsets for registers used by UCI */ +#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC + struct clk; struct amba_device { @@ -65,6 +69,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid; + unsigned int cid; + struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override; }; From patchwork Wed Jan 30 23:40:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 157091 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6543696jaa; Wed, 30 Jan 2019 15:41:15 -0800 (PST) X-Google-Smtp-Source: ALg8bN7Qg9NTCEzPNSUIQhqA3thcn0hhrEfpqnFAVxgnXFsK82KidQ5RQhMJoWgA8rsS7phGr7j8 X-Received: by 2002:a65:4381:: with SMTP id m1mr28889152pgp.358.1548891675437; Wed, 30 Jan 2019 15:41:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548891675; cv=none; d=google.com; s=arc-20160816; b=rR9Via/ABiFYsHUrpt4fnraGoXpsARDr7CeVhvlPo8obob+aClrV/QHd1Vj8D373M6 tdfJ192NwSWYMLjw1kRyFCweLULD93xAXwwQBJYtkhKVtwsWtsHJcT8+aB5Qjgoc7BI8 gpodIqDSbTqPScYd6wl8r4JB44h7Rm6gzQeD0NyImNSthB9TjBbYy6T7d/Hsuyb7YsGd 6fd3+vjETHeRRX+br+SCoUDp+I4LsxCeDaRGayQKrmKlP48q9TH1rsLqZjFCjTSBEB8v 2b+oIqsljl6WajvIwknLPFt8AeLMPWuDkXglZuTqRl7Yan08ddQjAQP9aCuEQk2WxaVi VvPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=N0+MiYkl2FyUrNQhM06/7391PqinzSAuv8ZoqqjUEE4=; b=uTr2HuvNcjzLmnX4lULhiKhDLSTNwmJC1HompwoOoeEFy4a+tmf40tJmX+5HUDgOen Oc3f9vBJOuBKvg38+Xz3TQK3zOk/38NBHMj7u5R3uw96a3kAwawo76LTy1zX6RfPF3Xk u5+N5XXyVZLv6K3BpmV6fXZobGKu/iJ070mE2eKmiHffTJaxvRATJD/TOJZzeDTB/4gx tk4l7AXOMxGpjHTRRwsQdP3afmWDKoF8KSjkIw0XkuaVIgtSVmuVBxMc6bybgK0d6juK Sqx+sSBpykfclGaQ5ja6J7UtQc8MmdxtIsQIIXREQ/7vxW3YBr4VXzr9qMB0tWq4w9eC txfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A4ICsNpM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q2si2842333plh.261.2019.01.30.15.41.15; Wed, 30 Jan 2019 15:41:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A4ICsNpM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728641AbfA3XlN (ORCPT + 31 others); Wed, 30 Jan 2019 18:41:13 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:37101 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727166AbfA3XlC (ORCPT ); Wed, 30 Jan 2019 18:41:02 -0500 Received: by mail-wr1-f68.google.com with SMTP id s12so1336545wrt.4 for ; Wed, 30 Jan 2019 15:41:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N0+MiYkl2FyUrNQhM06/7391PqinzSAuv8ZoqqjUEE4=; b=A4ICsNpMFi+QJWC1G7cGMifLk7QGKMRGBKWrFYbboVsNH/8mdeQwKL1b0XE/rNcup7 2T/DIqLlU0K0Zzd98Q7j+cTCFsCSlGookt7jBeM9iSepujof5qpJlckNf7cprfPxfi2S 9ytIC2pIsbtAFcrytL90m0Qo+vFW3Jz7h0KVc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N0+MiYkl2FyUrNQhM06/7391PqinzSAuv8ZoqqjUEE4=; b=Wvs1uZZOpuGNpuxh2iI7RtFcjtHnP8gOGL5EpTRElkuonl4Gt4aTlgO5UTC28GtOuR BQA4Pl7tObmCbu3cvGukfkIBppWPrVKkmq69Wv8YTz+f4HXRa8JIuhhYK0CBo6tDJNV1 QFWwKfERm2GdEHpzdH0tBRtc1i4fjzJUrPfoh1cSnOQDUUCikuTd2jYFYNI8Q00ZKkO1 BX98vuBobP2YZpZ7NkWqFjYJxZoPrllDpQqYhSpNq0OdMFWkZoGAd53mvxQEEhrT2oul 9vSf35xC+OWt3rsz2f4iX8VdL2J97A0DjmyFAHnTl6MDZsszfCVV30zmQcblM30Y9X3g ujdg== X-Gm-Message-State: AJcUukeNqI0QSAg2xZFUR2TVhMwrd93Op3QJ0lDZXKJfWCarS0HV0m78 NZK3MBqR68ypXkSnk/g3aBHlUg== X-Received: by 2002:a5d:4b01:: with SMTP id v1mr30735806wrq.5.1548891660014; Wed, 30 Jan 2019 15:41:00 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id s3sm2344770wmj.23.2019.01.30.15.40.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 15:40:59 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Cc: linux@armlinux.org.uk, saiprakash.ranjan@codeaurora.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, arm@kernel.org Subject: [PATCH v4 3/3] coresight: etmv4: Update ID register table to add UCI support Date: Wed, 30 Jan 2019 23:40:51 +0000 Message-Id: <20190130234051.2294-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190130234051.2294-1-mike.leach@linaro.org> References: <20190130234051.2294-1-mike.leach@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds macro to enable UCI entries to be added to AMBA ID tables. Updates the ID register tables to contain a UCI entry for the A35 ETM device to allow correct matching of driver in the amba bus code. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm4x.c | 21 +++++++++++-------- drivers/hwtracing/coresight/coresight-priv.h | 8 +++++++ 2 files changed, 20 insertions(+), 9 deletions(-) -- 2.19.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 53e2fb6e86f6..dd9b9b5ebb84 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1067,18 +1067,21 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return ret; } -#define ETM4x_AMBA_ID(pid) \ - { \ - .id = pid, \ - .mask = 0x000fffff, \ +static struct amba_cs_uci_id uci_id_etm4[] = { + { + /* ETMv4 UCI data */ + .devarch = 0x47704a13, + .devarch_mask = 0xfff0ffff, + .devtype = 0x00000013, } +}; static const struct amba_id etm4_ids[] = { - ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ - ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ - ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ - ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ - ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ + CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ + CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ + CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ + CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4), /* Cortex-A35 */ {}, }; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 02a1f5204f9d..fd69ad24432a 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -183,6 +183,14 @@ static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } } \ } +/* coresight AMBA ID, full UCI structure: id table entry. */ +#define CS_AMBA_UCI_ID(pid, uci_ptr) \ + { \ + .id = pid, \ + .mask = 0x000fffff, \ + .data = uci_ptr \ + } + /* extract the data value from a UCI structure given amba_id pointer. */ static inline void *coresight_get_uci_data(const struct amba_id *id) {