From patchwork Tue Aug 2 17:57:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 594969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6FACC19F29 for ; Tue, 2 Aug 2022 17:58:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235087AbiHBR62 (ORCPT ); Tue, 2 Aug 2022 13:58:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235027AbiHBR60 (ORCPT ); Tue, 2 Aug 2022 13:58:26 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F3864F66A for ; Tue, 2 Aug 2022 10:58:25 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id a18-20020a05600c349200b003a30de68697so1022606wmq.0 for ; Tue, 02 Aug 2022 10:58:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vuo/vfkePpTgDDEhsrHOq8e5JZuKt6L4eA032kLF7mw=; b=PnFR54/krkQJBd9Cf9a4Xk/Fct0bWlowlgRa8ZaGY0hDslopTBk/b9JuMhEE9wm0nj f9CPxt4/15USCxyOb217JyqZOsQiP71VknMujxa5tmHdA9j3grppFgZSa9oqCWasMW3X txoksfC18gjyehYqyKNPtqZ4iYmIzSLBx9gFa9dYdLB5kX1fLLZpG/fADDodDAvQ1PtN SguY7LD2ouWC1j5H065nWm5J44FSj+T9zZmpase271yDX06aSD6u2v8YGIjDyfhAX4Ap 3QM+OZJ7Wxo1toFmslEvOmVhaDxVBB0YAAsfT0YMVsS6xXy//CvoCTVYgfPLxQuA1OmZ tygQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vuo/vfkePpTgDDEhsrHOq8e5JZuKt6L4eA032kLF7mw=; b=Tk7at+PwcYK/oH1tNh5gUwHvdNGTpU2JEJ4+FoRa36j2zDOw78StRszRIms27Kz3Cd R8AqxSJ/IHwbe5NxChTlywlssPhGtO30KKvl0kxg53pegp431ZAae0d3KX+nBuXyzwND oyz4tOHLS1INS23fktgT6trTlBJD3+y/EvBueO2tYxGBZQbtRkhKKDGXJWj2+9bfdwRX 5G4U2Ny1+P9k4D3x4v6qC0X867ObylfYfZLgOiH4AkGa3a3z6amJBuocofcKBKDRNzXp yK6V+ZojXySIja7Z/H0K/53VgLgudoIQAdgqfo0ypcvQCKZiFLIi98k9pfYZyQjRe3mQ kHXw== X-Gm-Message-State: ACgBeo15Q3g8RJBvWRr31tmMVy7GcWUvAkJLY/N9o9tEP7CzUheQUY0/ u73cclf9V0isLthokzOO06XFnA== X-Google-Smtp-Source: AA6agR7fgM/0HFHd9EIUlLwNLdq6e6BT/2vkCwL/gzJY507E1BFT1d+PE2SL6vS8x8gdqvrg6ZKFTQ== X-Received: by 2002:a05:600c:40cf:b0:3a3:1fd6:47b7 with SMTP id m15-20020a05600c40cf00b003a31fd647b7mr406810wmh.32.1659463103860; Tue, 02 Aug 2022 10:58:23 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:58:23 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 01/11] spi: dw: define capability for enhanced spi Date: Tue, 2 Aug 2022 18:57:45 +0100 Message-Id: <20220802175755.6530-2-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some Synopsys SSI controllers support enhanced SPI which includes Dual mode, Quad mode and Octal mode. Define the capability and mention it in the controller supported modes. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 4 ++++ drivers/spi/spi-dw.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index f87d97ccd2d6..97e72da7c120 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -917,6 +917,10 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) master->use_gpio_descriptors = true; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; + if (dws->caps & DW_SPI_CAP_EXT_SPI) + master->mode_bits |= SPI_TX_DUAL | SPI_RX_DUAL | + SPI_TX_QUAD | SPI_RX_QUAD | + SPI_TX_OCTAL | SPI_RX_OCTAL; if (dws->caps & DW_SPI_CAP_DFS32) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); else diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9e8eb2b52d5c..71d18e9291a3 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -32,6 +32,7 @@ /* DW SPI controller capabilities */ #define DW_SPI_CAP_CS_OVERRIDE BIT(0) #define DW_SPI_CAP_DFS32 BIT(1) +#define DW_SPI_CAP_EXT_SPI BIT(2) /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ #define DW_SPI_CTRLR0 0x00 From patchwork Tue Aug 2 17:57:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 594968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9C61C00140 for ; Tue, 2 Aug 2022 17:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235652AbiHBR6p (ORCPT ); Tue, 2 Aug 2022 13:58:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235277AbiHBR6l (ORCPT ); Tue, 2 Aug 2022 13:58:41 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F1594F6B8 for ; Tue, 2 Aug 2022 10:58:39 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id b21-20020a05600c4e1500b003a32bc8612fso7300053wmq.3 for ; Tue, 02 Aug 2022 10:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UjGXyUyDLmjMDOf8jNJMvPEYFg/F977ZxHxgmhAvnmc=; b=Qh2sccOhKOymfr5Qop+pGzCH8T+687LGQLFRfVvoM3mFqaGCRJEm0wRxg98se49s0U N+wb1c9mjaL4yVirYDILB0P0YX4NPYi9DAHEV9Eg2iI0V0j1C/dHTMTtSmubquYBNiE7 DDnG2uqIJDUgkqbyvgCoOMvk0rA64gM0k18LqPAeHBOB7RprdaxP2Dly/I1A27INmgug J9/3qEKHS2ciOpZsH7KiXSf/iiUZ3lvfArqouhz/x1xSOUF95ftI6SHX2sRSodB3Rnx4 vh5gK7ye8THHoD7z30L9YwPyRms6IcJ/FeyrpKmOO3bf4EVLHbxK1WRpsFHzzyT/4nMi ezJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UjGXyUyDLmjMDOf8jNJMvPEYFg/F977ZxHxgmhAvnmc=; b=fABOAwhN2O1uV6QV9I/wUrtfejK2sitKecFNeeTSzxZkPk5SVd5VJCUdwbVUrgLxVx q7gzf2W63fIo6ptsdFlqW93rWc9i9eNXkw0tkhZKPE2pkgIK9gESVMvaPOH7zCtvCKTU yrt3s88hCGTMgneEH7Ln7R7u3dyhnrMEGfM328l5kMf3+oqRFWivVpNrh2hEqT//cqXn H7Q/37MHlbhinGNYce13pfhcN7BAGhh5RK27zFZZnZwtw0x8DbYpmlvb0iLukrW8VsDQ pURUTqHS1LsEs5a4V5zvQfKo1pmsGzFZu9vaHLIEdpmv5E4edCSLwcIzVjetlycohnJV AxfA== X-Gm-Message-State: ACgBeo0CNSMxkTw63gjrr+V0qXLIza+T+BTaA6sAavxPNWmiBgeMTp8M KKrPYBnZyvFOE9W+5M2tLDhk2A== X-Google-Smtp-Source: AA6agR4jqgI7Xs6iYK8jzlkHDKEuwOrDweCr7U8C/ikyOQNCqpvpyUePii/sxWpyirqjvlfe+oPfuA== X-Received: by 2002:a05:600c:19d2:b0:3a3:2cdb:cc02 with SMTP id u18-20020a05600c19d200b003a32cdbcc02mr382332wmq.182.1659463117937; Tue, 02 Aug 2022 10:58:37 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:58:37 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 03/11] spi: dw: define spi_frf for dual/quad/octal modes Date: Tue, 2 Aug 2022 18:57:47 +0100 Message-Id: <20220802175755.6530-4-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SPI mode needs to be mentioned in CTRLR0[23:22] register. Define a configuration variable to keep the mode based on the buswidth, which will then be used to update CR0. If the transfer is using dual/quad/octal mode then mark enhanced_spi as true. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 29 +++++++++++++++++++++++++++++ drivers/spi/spi-dw.h | 7 +++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 77529e359b6d..8c84a2e991b5 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -333,6 +333,14 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, /* CTRLR0[11:10] Transfer Mode */ cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode); + if (dws->caps & DW_SPI_CAP_EXT_SPI) { + if (cfg->spi_frf) + cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK, + cfg->spi_frf); + else + cr0 &= ~DW_HSSI_CTRLR0_SPI_FRF_MASK; + } + dw_writel(dws, DW_SPI_CTRLR0, cr0); if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || @@ -679,10 +687,31 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller); + bool enhanced_spi = false; struct dw_spi_cfg cfg; unsigned long flags; int ret; + if (dws->caps & DW_SPI_CAP_EXT_SPI) { + switch (op->data.buswidth) { + case 2: + cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_DUAL_SPI; + enhanced_spi = true; + break; + case 4: + cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_QUAD_SPI; + enhanced_spi = true; + break; + case 8: + cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_OCT_SPI; + enhanced_spi = true; + break; + default: + cfg.spi_frf = 0; + break; + } + } + /* * Collect the outbound data into a single buffer to speed the * transmission up at least on the initial stage. diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 71d18e9291a3..b8cc20e0deaa 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -96,6 +96,12 @@ #define DW_HSSI_CTRLR0_SRL BIT(13) #define DW_HSSI_CTRLR0_MST BIT(31) +/* Bit fields in CTRLR0 for enhanced SPI */ +#define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22) +#define DW_SSI_CTRLR0_SPI_FRF_DUAL_SPI 0x1 +#define DW_SSI_CTRLR0_SPI_FRF_QUAD_SPI 0x2 +#define DW_SSI_CTRLR0_SPI_FRF_OCT_SPI 0x3 + /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0) @@ -136,6 +142,7 @@ struct dw_spi_cfg { u8 dfs; u32 ndf; u32 freq; + u8 spi_frf; }; struct dw_spi; From patchwork Tue Aug 2 17:57:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 594967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98CA4C19F29 for ; Tue, 2 Aug 2022 17:59:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236553AbiHBR7U (ORCPT ); Tue, 2 Aug 2022 13:59:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236119AbiHBR66 (ORCPT ); Tue, 2 Aug 2022 13:58:58 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADEB151413 for ; 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Tue, 02 Aug 2022 10:58:51 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:58:51 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 05/11] spi: dw: define SPI_CTRLR0 register and its fields Date: Tue, 2 Aug 2022 18:57:49 +0100 Message-Id: <20220802175755.6530-6-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Synopsys SSI controllers supporting enhanced SPI mode of operation has SPI Control Register at offset 0xf4 which controls the following: CLK_STRETCH_EN: Enables clock stretching capability in SPI transfers. In case of write, if the FIFO becomes empty DWC_ssi will stretch the clock until FIFO has enough data to continue the transfer. In case of read, if the receive FIFO becomes full DWC_ssi will stop the clock until data has been read from the FIFO. WAIT_CYCLES: Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. INST_L: Dual/Quad/Octal mode instruction length in bits. ADDR_L: defines Length of Address to be transmitted. For now, we are only using 32bit Address length and 8 bit Instruction length. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index b8cc20e0deaa..a7a4637d6d32 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -63,6 +63,17 @@ #define DW_SPI_RX_SAMPLE_DLY 0xf0 #define DW_SPI_CS_OVERRIDE 0xf4 +/* Register offsets (Defined in DWC SSI 1.03a) */ +#define DW_HSSI_SPI_CTRLR0 0xf4 + +/* Bit fields in SPI_CTRLR0 (Defined in DWC SSI 1.03a) */ +#define DW_HSSI_SPI_CTRLR0_CLK_STRETCH_EN BIT(30) +#define DW_HSSI_SPI_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11) +#define DW_HSSI_SPI_CTRLR0_INST_L_MASK GENMASK(9, 8) +#define DW_HSSI_SPI_CTRLR0_INST_L8 0x2 +#define DW_HSSI_SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2) +#define DW_HSSI_SPI_CTRLR0_ADDR_L32 0x8 + /* Bit fields in CTRLR0 (DWC APB SSI) */ #define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0) #define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16) From patchwork Tue Aug 2 17:57:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 594966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C92FC19F28 for ; Tue, 2 Aug 2022 17:59:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236735AbiHBR7k (ORCPT ); Tue, 2 Aug 2022 13:59:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235394AbiHBR7Q (ORCPT ); Tue, 2 Aug 2022 13:59:16 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72A5951A15 for ; Tue, 2 Aug 2022 10:59:06 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id z17so14128002wrq.4 for ; Tue, 02 Aug 2022 10:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sl9Z98LrR1HGqesJuJI9JTYA1Pp0siEP1pFEoTfJVN4=; b=BraroAuIQqADk1cnPCUB+aLh71k99p66yNBjBE+daWZAXJlSqonJQiZ0FlH0EOzoWp qty7Gm9qCLCWysfVI6MKR3XEewBIan5xCzCgYM1vIWkV0Xhihh1EqDMYCmA3yG0OvsSP Vesref23GBooU7Y2ju9GiSMdXRzuYjwBDnOzRYUAs4cCxLUpB6XRzTiWq4DCt+s+pvUt ZNNPNHDsVuSMY4oojQy4b1QjHXc8NAZbRnObtruXL7xw1g+ckQ0/k+N7YRV2qcLZBsnj 5RRCUZvQgrpfIR75YsbOKLcogkxtn5cKFehPjzxmzCaaXnianjUUOqYVHWgBfcQXrZ2B jZtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sl9Z98LrR1HGqesJuJI9JTYA1Pp0siEP1pFEoTfJVN4=; b=HQUwqKdy7vg0culfUP5Qyw7TwIq3CpNe6gaMjg+Q+JLk5zvmt/mmzzB//WVCx5PVTY uRqWYJ1MpWzf5zJCf/p6Zk0ZzPMIIN8bclJG3NujqoS/t14PfYcbCmcqEN5V/gIGMp9W 1GTZChDOC9Cff/24ABrrB1mYnmPH3ZsbAPeuunGp2PnJGIzsRgSSEJ+/TvCODnkR5qpt r07/epgqnRCbOZ6nn3um3CKZV9EDrhBJ1H3fMomvVkm8VpoRAzeP+UkzUqVJ4+itQ7oY Il/Ad/O7kJ++l+b0jqVVvCSDLNACG+PJXlNzBdE3cIHKiI+czdPL/pZAMiOISYshk2o6 DHPw== X-Gm-Message-State: ACgBeo0eJHzq8+K9OHeItM4HJzY7sA2rx6QHwWu6GRCb3QCO2BijkiYm VfAC7EEzQ82z6O/un9OF7ZuD8A== X-Google-Smtp-Source: AA6agR66+Jqszo7T/0P1VL5IUVzXM9piN1M4GBE4tIZBTx475dA6PJNPHMkQlN3ie5uOahqE3xClRQ== X-Received: by 2002:a05:6000:230:b0:21e:cf23:499f with SMTP id l16-20020a056000023000b0021ecf23499fmr14072388wrz.29.1659463146015; Tue, 02 Aug 2022 10:59:06 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:59:05 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 07/11] spi: dw: update NDF while writing in enhanced spi mode Date: Tue, 2 Aug 2022 18:57:51 +0100 Message-Id: <20220802175755.6530-8-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If the transfer of Transmit only mode is using dual/quad/octal SPI then NDF needs to be updated with the number of data frames. If the Transmit FIFO goes empty in-between, DWC_ssi masks the serial clock and wait for rest of the data until the programmed amount of frames are transferred successfully. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 9d499bdf2ce6..8cb30540ad5b 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -344,7 +344,9 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, dw_writel(dws, DW_SPI_CTRLR0, cr0); if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || - cfg->tmode == DW_SPI_CTRLR0_TMOD_RO) + cfg->tmode == DW_SPI_CTRLR0_TMOD_RO || + (cfg->tmode == DW_SPI_CTRLR0_TMOD_TO && + (dws->caps & DW_SPI_CAP_EXT_SPI) && cfg->spi_frf)) dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); /* Note DW APB SSI clock divider doesn't support odd numbers */ @@ -760,6 +762,8 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) cfg.ndf = op->data.nbytes; } else { cfg.tmode = DW_SPI_CTRLR0_TMOD_TO; + if (enhanced_spi) + cfg.ndf = op->data.nbytes; } dw_spi_enable_chip(dws, 0); From patchwork Tue Aug 2 17:57:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 594965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A8B6C19F29 for ; Tue, 2 Aug 2022 18:00:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236845AbiHBSAD (ORCPT ); Tue, 2 Aug 2022 14:00:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234722AbiHBR7d (ORCPT ); Tue, 2 Aug 2022 13:59:33 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BD6751410 for ; Tue, 2 Aug 2022 10:59:21 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id v3so17898117wrp.0 for ; Tue, 02 Aug 2022 10:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EgBNPFA6iH7qw2lvPfZZWo2zsFGuQgHM3NShlMf43pY=; b=PF6fBnKlQ88A9aTw15wV58rFsRu/CLh/WhHzPYx/W3mpot5tutkCFEV2KkEEweaKqi ZMdSlXszL6AV+LTJWr+A5j5c3xEhliVkvKrOkPwqMoH+dR4I0cY4XnT/2MrKuvE3QAdE JTMqFuCcuO2RR+lraL6es3E1oqaa6FQyibyfHy1mZlOflz7eaKjem3HZkR1SUqBe2x5B otpaJtQqp/5F0xv2A6zFs9659cBYzAnpxF83u+f0nbHfo1Gf2z9z4TqTkYCJR2Yfnir+ y315Prw9EJAwO1lRVfbmJds8Hxxts6cIoOR/w2dcCLDE1PwLI8Z2FpC6DsXqvWIy7+iC 34LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EgBNPFA6iH7qw2lvPfZZWo2zsFGuQgHM3NShlMf43pY=; b=soQ1a7ibdgP3FnPK3uRTGT67JVN9lso0q1JKEYrbGfd8CuqtFGCCgZUvW0nmFBbIRU 38wsirhLLCxY1UFecajJUwRbGkgoWpf1/FwrAgnWjp0QI2I8honrwXde5jnVaAFMkmWr ngw3SkQlGuKYb1p8T0kCc/hq3XcZJpdUSiFazopjfRwQEHuQnfZdhahSKm3qykPu2s9r GpvzKeuX+Zx06S8ieD8kR3Nphh3eK+acc/akyvoesbqGidqfq1FwOND6UkwikYptfi4J yGs3TQC+M3ByRGFyv1B7VqR2QrTmgslk5rNlmPU27apPjTacUc2omhytUjWgyEx70egp WPrA== X-Gm-Message-State: ACgBeo255Y79MtmOWIKEeruLL1ZNPynUEIbCxm7jcsLhVaU/UzWVIEnq 2QrG1D4vDserRJeb4+GhRCjHtA== X-Google-Smtp-Source: AA6agR4+Xe7fQqjK1UteZlARwyFQQy84pkaf8BFmW88PyIz3BjbwgCCLs+QpO1C+QFvSgB9IjCv0Lg== X-Received: by 2002:adf:ebc5:0:b0:21d:640e:dc2f with SMTP id v5-20020adfebc5000000b0021d640edc2fmr13819804wrn.227.1659463160197; Tue, 02 Aug 2022 10:59:20 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.59.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:59:19 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 09/11] spi: dw: prepare the transfer routine for enhanced mode Date: Tue, 2 Aug 2022 18:57:53 +0100 Message-Id: <20220802175755.6530-10-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The transfer routine of dual/quad/octal is similar to standard SPI mode except that we do not need to worry about CS being de-asserted and we will be writing the address to a single FIFO location. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 141 +++++++++++++++++++++++++++++++++----- 1 file changed, 125 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 2564a2276572..d6afa75e7023 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -712,6 +712,28 @@ static int dw_spi_wait_mem_op_done(struct dw_spi *dws) return 0; } +static void ext_transfer_delay(struct dw_spi *dws) +{ + struct spi_delay delay; + unsigned long ns, us; + u32 nents; + + nents = dw_readl(dws, DW_SPI_TXFLR); + ns = NSEC_PER_SEC / dws->current_freq * nents; + ns *= dws->n_bytes * BITS_PER_BYTE; + if (ns <= NSEC_PER_USEC) { + delay.unit = SPI_DELAY_UNIT_NSECS; + delay.value = ns; + } else { + us = DIV_ROUND_UP(ns, NSEC_PER_USEC); + delay.unit = SPI_DELAY_UNIT_USECS; + delay.value = clamp_val(us, 0, USHRT_MAX); + } + /* wait until there is some space in TX FIFO */ + while (!(dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_TF_NOT_FULL)) + spi_delay_exec(&delay, NULL); +} + static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) { dw_spi_enable_chip(dws, 0); @@ -719,6 +741,82 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) dw_spi_enable_chip(dws, 1); } +static int enhanced_transfer(struct dw_spi *dws, struct spi_device *spi, + const struct spi_mem_op *op) +{ + u32 max, txw = 0, rxw; + bool cs_done = false; + void *buf = dws->tx; + int ret; + + /* Send cmd as 32 bit value */ + if (buf) { + txw = *(u32 *)(buf); + dw_write_io_reg(dws, DW_SPI_DR, txw); + buf += 4; + dws->tx_len--; + if (op->addr.nbytes) { + /* + * Send address as 32 bit value if address + * is present in the instruction. + */ + txw = *(u32 *)(buf); + dw_write_io_reg(dws, DW_SPI_DR, txw); + buf += 4; + dws->tx_len--; + } + } + + do { + max = min_t(u32, dws->tx_len, dws->fifo_len - + dw_readl(dws, DW_SPI_TXFLR)); + while (max--) { + if (buf) { + txw = *(u8 *)(buf); + buf += dws->n_bytes; + } + dw_write_io_reg(dws, DW_SPI_DR, txw); + --dws->tx_len; + } + /* Enable CS after filling up FIFO */ + if (!cs_done) { + dw_spi_set_cs(spi, false); + cs_done = true; + } + ext_transfer_delay(dws); + if (!dws->tx_len && !dws->rx_len) { + /* + * We only need to wait for done if there is + * nothing to receive and there is nothing more + * to transmit. If we are receiving, then the + * wait cycles will make sure we wait. + */ + ret = dw_spi_wait_mem_op_done(dws); + if (ret) + return ret; + } + } while (dws->tx_len); + + buf = dws->rx; + while (dws->rx_len) { + max = dw_spi_rx_max(dws); + + while (max--) { + rxw = dw_read_io_reg(dws, DW_SPI_DR); + if (buf) { + *(u8 *)(buf) = rxw; + buf += dws->n_bytes; + } + --dws->rx_len; + } + + ret = dw_spi_check_status(dws, true); + if (ret) + return ret; + } + return 0; +} + static void update_spi_ctrl0(struct dw_spi *dws, const struct spi_mem_op *op, bool enable) { u32 spi_ctrlr0; @@ -846,25 +944,36 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) * manually restricting the SPI bus frequency using the * dws->max_mem_freq parameter. */ - local_irq_save(flags); - preempt_disable(); + if (!enhanced_spi) { + local_irq_save(flags); + preempt_disable(); - ret = dw_spi_write_then_read(dws, mem->spi); + ret = dw_spi_write_then_read(dws, mem->spi); - local_irq_restore(flags); - preempt_enable(); + local_irq_restore(flags); + preempt_enable(); - /* - * Wait for the operation being finished and check the controller - * status only if there hasn't been any run-time error detected. In the - * former case it's just pointless. In the later one to prevent an - * additional error message printing since any hw error flag being set - * would be due to an error detected on the data transfer. - */ - if (!ret) { - ret = dw_spi_wait_mem_op_done(dws); - if (!ret) - ret = dw_spi_check_status(dws, true); + /* + * Wait for the operation being finished and check the + * controller status only if there hasn't been any + * run-time error detected. In the former case it's + * just pointless. In the later one to prevent an + * additional error message printing since any hw error + * flag being set would be due to an error detected on + * the data transfer. + */ + if (!ret) { + ret = dw_spi_wait_mem_op_done(dws); + if (!ret) + ret = dw_spi_check_status(dws, true); + } + } else { + /* + * We donot need to disable IRQs as clock stretching will + * be enabled in enhanced mode which will prevent CS + * from being de-assert. + */ + ret = enhanced_transfer(dws, mem->spi, op); } dw_spi_stop_mem_op(dws, mem->spi); From patchwork Tue Aug 2 17:57:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 594964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12B3EC00140 for ; Tue, 2 Aug 2022 18:00:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232152AbiHBSAS (ORCPT ); Tue, 2 Aug 2022 14:00:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235771AbiHBR7o (ORCPT ); Tue, 2 Aug 2022 13:59:44 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9F04501A2 for ; Tue, 2 Aug 2022 10:59:34 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id b6so7571034wmq.5 for ; Tue, 02 Aug 2022 10:59:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dksoanYJoZO8G01KR5WlaEaO1JRamu4a/M2lotcY4Us=; b=cJzyb6w6buAT4Si/LRbYnFJOIEuXMT96PIUp3Cza/fREQOsThox0SJ6o43dJ8Pk7Jn LfbiSVkviFwvZJBQYr+raawJje3EleuA5fdAPHnphp2Gh1S+bSPoAjazyFNpL/0wjZQW mOTBUX6qkVmcZV7JM1FeRCSGNHWmpzJO/bCYb3K7vNQzTFwsx7cf9jAMIsz3SpL6mAE5 Z8hr56URVZjl1JOV3bZ0qHtEl1yYfNR/kIMtfv42fk1H7agRsFbQ1duZeLMGWewzeqeB qiezCxTu4w6G496EFPEw+GTc0UbnK0C1sRsu5WZjzMToAq1sWQQGA/LPMsWMW06ELxj3 zuKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dksoanYJoZO8G01KR5WlaEaO1JRamu4a/M2lotcY4Us=; b=3198slbhuiuEoPp+WOP3/1q69ebnJIIbkbliRc43SkASEcsPRiZv70G22umdDKHsVr F38kaFIOVCRPWdO0A3rsNDyAzMRnfg7x+0us1JDxTRWFieVWZsRXpAmnKAyXqdQ25KuF aoG/Q+MLzOVroyT6M9f+mCbKU+Nayy7IKo0PN39jp1FNOLQ6mckHblbjGQpDJ8YEwkiZ oXkXMXVvaLGnpcIQJaDfgGWBSUkwz68NGf2tnKAV+pzp0JLVHElnDobb/vZltcR+mA+G UDB4sS+eHHGtu/kiQ+oagUtUea4RDgmCfmSSjOXlC6c5qAuPcnEmAPDvW3ET7/7zZnl4 G4vQ== X-Gm-Message-State: ACgBeo1uNvXrUN6KlF+R6B6eJg8SZQzlhMCHDBvHa5GvzDK1onupSa/+ TMC/0meDS70NjcPoDLLkGe7/Fw== X-Google-Smtp-Source: AA6agR557a68A28uaXoSIeKdmvNzbTM0Ny3U/oteTSHz5ZHwIapC+B9nEc6H0RjuhnZ2aK0AhXbE5g== X-Received: by 2002:a1c:2783:0:b0:3a2:fd82:bf46 with SMTP id n125-20020a1c2783000000b003a2fd82bf46mr382235wmn.29.1659463174307; Tue, 02 Aug 2022 10:59:34 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:59:33 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 11/11] spi: dw: initialize dwc-ssi-1.03a controller Date: Tue, 2 Aug 2022 18:57:55 +0100 Message-Id: <20220802175755.6530-12-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define the initialization of dwc-ssi-1.03a controller and mark it with the capability of enhanced SPI supporting dual/quad/octal modes of transfer. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-mmio.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..db80e0645172 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -237,6 +237,15 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static int dw_spi_hssi_ext_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + dwsmmio->dws.ip = DW_HSSI_ID; + dwsmmio->dws.caps = DW_SPI_CAP_EXT_SPI; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +361,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "snps,dwc-ssi-1.03a", dw_spi_hssi_ext_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);