From patchwork Tue Aug 2 17:34:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauri Sandberg X-Patchwork-Id: 594971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1FA3C00140 for ; Tue, 2 Aug 2022 17:36:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231506AbiHBRgo (ORCPT ); Tue, 2 Aug 2022 13:36:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229530AbiHBRgm (ORCPT ); Tue, 2 Aug 2022 13:36:42 -0400 Received: from mailserv1.kapsi.fi (mailserv1.kapsi.fi [IPv6:2001:67c:1be8::25:1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCE5F33E06; Tue, 2 Aug 2022 10:36:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ext.kapsi.fi; s=20161220; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=fvM/g7yEmol5LB1hRTfh0dP3z5l+1DidjnEGxSNhVDA=; b=Udv7QKnmiAS3H9k5XfcUw89ka8 6GvIX2sUR1RGU8wqdC+UaMMxTLcVcVkQtBso1YnE9zAOYcuDQmHRcNsp9yehY11VzgvT6Hjvmvpg8 yHDSlM/g45n3GcV2Q31cv78fiILx2Dgv5itMZOZVDF1U32SgIXxpbfJ1ozxsjoqSbvhLPUrIZVYN5 vXxEK1WM6YKHACA5j+jzkVU5dZ8I4nmTsNGGvz0bAHI0IEXP+ky7XoLa8iM2wNuwUDNyaZGTGnyAa hIlTLeIsQY/ILk7VtXPoTKeymCavyeckp9Oawa4E+4+8Xqg+biopdLXeOlkSYxT4TQ7m0CxEwL25o KYpc7mkQ==; Received: from a82-197-11-249.mpynet.fi ([82.197.11.249]:55983 helo=localhost) by mailserv1.kapsi.fi with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oIvop-008Ymy-4O; Tue, 02 Aug 2022 20:36:36 +0300 Received: by localhost (sSMTP sendmail emulation); Tue, 02 Aug 2022 20:36:33 +0300 From: Mauri Sandberg To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, andrew@lunn.ch, sebastian.hesselbarth@gmail.com, gregory.clement@bootlin.com, linux@armlinux.org.uk, lpieralisi@kernel.org, kw@linux.com, thomas.petazzoni@bootlin.com, pali@kernel.org, Mauri Sandberg , Rob Herring Date: Tue, 2 Aug 2022 20:34:22 +0300 Message-Id: <20220802173423.47230-2-maukka@ext.kapsi.fi> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220802173423.47230-1-maukka@ext.kapsi.fi> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220802173423.47230-1-maukka@ext.kapsi.fi> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 82.197.11.249 X-SA-Exim-Mail-From: maukka@ext.kapsi.fi Subject: [PATCH v2 1/2] dt-bindings: PCI: mvebu: Add orion5x compatible X-SA-Exim-Version: 4.2.1 (built Sat, 13 Feb 2021 17:57:42 +0000) X-SA-Exim-Scanned: Yes (on mailserv1.kapsi.fi) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a compatible string to bindings to indicate that orion5x PCIe is supported too. Signed-off-by: Mauri Sandberg Acked-by: Rob Herring --- v1->v2: - added ack by Rob --- Documentation/devicetree/bindings/pci/mvebu-pci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index 6d022a9d36ee..ced5d030fe55 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -7,6 +7,7 @@ Mandatory properties: marvell,armada-xp-pcie marvell,dove-pcie marvell,kirkwood-pcie + marvell,orion5x-pcie - #address-cells, set to <3> - #size-cells, set to <2> - #interrupt-cells, set to <1> From patchwork Tue Aug 2 17:34:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mauri Sandberg X-Patchwork-Id: 594970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0C23C19F28 for ; Tue, 2 Aug 2022 17:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231807AbiHBRgp (ORCPT ); Tue, 2 Aug 2022 13:36:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229545AbiHBRgm (ORCPT ); Tue, 2 Aug 2022 13:36:42 -0400 Received: from mailserv1.kapsi.fi (mailserv1.kapsi.fi [IPv6:2001:67c:1be8::25:1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCD5833A29; Tue, 2 Aug 2022 10:36:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ext.kapsi.fi; s=20161220; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Cc:To:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=slMr5916vD+9RDJ4lDNYA3WKLFVZwkO7Qq68zICCIVM=; b=WAAGaGbYPF6jnS+A7gzqHjklbX dzU/fyImxQ/jMVbZYew3zkHPYV2g4FjMvtOJnDaipVaDkNdhhBh6FeKvfzuHJHH3XeH20AMd3e0gM RyZAXB+BKl8y1dxYQcitgewZzyU/2D4VFaPhh4V2vNCJildJW5U7TYajyt8reOrtEtBb2shrHaW1r kUYsrXcJVJEaddkc1Qco1fNWsoQrvXcb15RP0pCXjslRutTp0EsWS1Gc6PxOIOb+sN1cMNwMM/I+h rpPF8X8jnSFMeArMMW150Xk1uCvzYRjw2ZsF+jDsftcuPBR2qFksd8ATqLnGU8amji/s60/5flBM7 BwYZQDrw==; Received: from a82-197-11-249.mpynet.fi ([82.197.11.249]:55984 helo=localhost) by mailserv1.kapsi.fi with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oIvoq-008Yn2-WB; Tue, 02 Aug 2022 20:36:38 +0300 Received: by localhost (sSMTP sendmail emulation); Tue, 02 Aug 2022 20:36:35 +0300 From: Mauri Sandberg To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, andrew@lunn.ch, sebastian.hesselbarth@gmail.com, gregory.clement@bootlin.com, linux@armlinux.org.uk, lpieralisi@kernel.org, kw@linux.com, thomas.petazzoni@bootlin.com, pali@kernel.org, Mauri Sandberg Date: Tue, 2 Aug 2022 20:34:23 +0300 Message-Id: <20220802173423.47230-3-maukka@ext.kapsi.fi> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220802173423.47230-1-maukka@ext.kapsi.fi> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220802173423.47230-1-maukka@ext.kapsi.fi> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 82.197.11.249 X-SA-Exim-Mail-From: maukka@ext.kapsi.fi Subject: [PATCH v2 2/2] PCI: mvebu: add support for orion5x X-SA-Exim-Version: 4.2.1 (built Sat, 13 Feb 2021 17:57:42 +0000) X-SA-Exim-Scanned: Yes (on mailserv1.kapsi.fi) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for orion5x PCIe controller. There is Orion-specific errata that config space via CF8/CFC registers is broken. Workaround documented in errata documented (linked from above documentation) does not work when DMA is used and instead other undocumented workaround is needed which maps config space to memory (and therefore avoids usage of broken CF8/CFC memory mapped registers). Signed-off-by: Mauri Sandberg Cc: Pali Rohár --- v1 -> v2: - do pcie related mvebu windows and remaps in pcie_setup() --- arch/arm/mach-orion5x/common.c | 13 ------- arch/arm/mach-orion5x/pci.c | 14 +++++++ drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pci-mvebu.c | 59 ++++++++++++++++++++++++++++++ 4 files changed, 74 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 7bcb41137bbf..9d8be5ce1266 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -231,19 +231,6 @@ void __init orion5x_init_early(void) void orion5x_setup_wins(void) { - /* - * The PCIe windows will no longer be statically allocated - * here once Orion5x is migrated to the pci-mvebu driver. - */ - mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, - ORION_MBUS_PCIE_IO_ATTR, - ORION5X_PCIE_IO_PHYS_BASE, - ORION5X_PCIE_IO_SIZE, - ORION5X_PCIE_IO_BUS_BASE); - mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, - ORION_MBUS_PCIE_MEM_ATTR, - ORION5X_PCIE_MEM_PHYS_BASE, - ORION5X_PCIE_MEM_SIZE); mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, ORION_MBUS_PCI_IO_ATTR, ORION5X_PCI_IO_PHYS_BASE, diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 9574c73f3c03..7c4e2f355cc7 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -150,6 +150,20 @@ static int __init pcie_setup(struct pci_sys_data *sys) */ orion_pcie_setup(PCIE_BASE); + /* + * The PCIe windows will no longer be statically allocated + * here once Orion5x is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, + ORION_MBUS_PCIE_IO_ATTR, + ORION5X_PCIE_IO_PHYS_BASE, + ORION5X_PCIE_IO_SIZE, + ORION5X_PCIE_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, + ORION_MBUS_PCIE_MEM_ATTR, + ORION5X_PCIE_MEM_PHYS_BASE, + ORION5X_PCIE_MEM_SIZE); + /* * Check whether to apply Orion-1/Orion-NAS PCIe config * read transaction workaround. diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index b8d96d38064d..a249375837f0 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -5,7 +5,7 @@ menu "PCI controller drivers" config PCI_MVEBU tristate "Marvell EBU PCIe controller" - depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST + depends on ARCH_MVEBU || ARCH_DOVE || ARCH_ORION5X || COMPILE_TEST depends on MVEBU_MBUS depends on ARM depends on OF diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index c1ffdb06c971..1d3052aa7e49 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -1487,6 +1487,54 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie) return 0; } +static int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where))); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +/* Relevant only for Orion-1/Orion-NAS */ +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) +#define ORION5X_PCIE_WA_SIZE SZ_16M +#define ORION_MBUS_PCIE_WA_TARGET 0x04 +#define ORION_MBUS_PCIE_WA_ATTR 0x79 + +static int mvebu_pcie_child_rd_conf_wa(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) +{ + struct mvebu_pcie *pcie = bus->sysdata; + struct mvebu_pcie_port *port; + + port = mvebu_pcie_find_port(pcie, bus, devfn); + if (!port) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (!mvebu_pcie_link_up(port)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* + * We only support access to the non-extended configuration + * space when using the WA access method (or we would have to + * sacrifice 256M of CPU virtual address space.) + */ + if (where >= 0x100) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val); +} + static int mvebu_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1663,6 +1711,16 @@ static int mvebu_pcie_probe(struct platform_device *pdev) bridge->align_resource = mvebu_pcie_align_resource; bridge->map_irq = mvebu_pcie_map_irq; + if (of_machine_is_compatible("marvell,orion5x-88f5181")) { + dev_info(dev, "Applying Orion-1/Orion-NAS PCIe config read transaction workaround\n"); + + mvebu_pcie_child_ops.read = mvebu_pcie_child_rd_conf_wa; + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET, + ORION_MBUS_PCIE_WA_ATTR, + ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); + } + return pci_host_probe(bridge); } @@ -1733,6 +1791,7 @@ static const struct of_device_id mvebu_pcie_of_match_table[] = { { .compatible = "marvell,armada-370-pcie", }, { .compatible = "marvell,dove-pcie", }, { .compatible = "marvell,kirkwood-pcie", }, + { .compatible = "marvell,orion5x-pcie", }, {}, }; From patchwork Mon Sep 5 19:23:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 602808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA5FAECAAD3 for ; Mon, 5 Sep 2022 19:25:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231940AbiIETZi (ORCPT ); Mon, 5 Sep 2022 15:25:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231929AbiIETZe (ORCPT ); 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Mon, 5 Sep 2022 21:25:17 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , Mauri Sandberg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 7/7] ARM: dts: orion5x: Add PCIe node Date: Mon, 5 Sep 2022 21:23:10 +0200 Message-Id: <20220905192310.22786-8-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905192310.22786-1-pali@kernel.org> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220905192310.22786-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define PCIe aperture for top level soc node handled by mbus driver and define PCIe controller node with one PCIe Root Port. Old Orion arch code maps first 16 MB of PCIe config space to physical address 0xf0000000. But for full PCIe support it is needed to map whole 256 MB long PCIe config space. There are probably no Orion boards with more than 2 GB of RAM, so 256 MB of free physical address space must exist. Tests on Orion board proved that there is free space in physical address range 0xd0000000-0xdfffffff. So use this physical space for mapping whole 256 MB long PCIe config space. In case there would be some issue with this range, particular Orion device tree board file can change it to 16 MB size or move it to old location. By default orion5x.dtsi include file would contains whole PCIe config space for full PCIe support. By default is PCIe node disabled, so this change in orion5x.dtsi has no effect for any board until board dts file explicitly enable it. Each board has to migrate its PCIe code from old arch specific to device tree based. Signed-off-by: Pali Rohár --- Changes in v3: * New patch --- arch/arm/boot/dts/orion5x.dtsi | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 2d41f5c166ee..41954d96ebbf 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -18,6 +18,9 @@ #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; + pcie-cfg-aperture = <0xd0000000 0x10000000>; /* 256 MiB config space */ + pcie-mem-aperture = <0xe0000000 0x08000000>; /* 128 MiB memory space */ + pcie-io-aperture = <0xf2000000 0x00100000>; /* 1 MiB I/O space */ devbus_bootcs: devbus-bootcs { compatible = "marvell,orion-devbus"; @@ -226,6 +229,54 @@ }; }; + pciec: pcie { + compatible = "marvell,orion5x-pcie"; + status = "disabled"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&intc>; + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0x0 0x2000>, /* Port 0.0 Internal registers */ + <0x82000000 0x0 0xf0000000 MBUS_ID(0x04, 0x79) 0x0 0x0 0x10000000>, /* Port 0.0 Config space registers */ + <0x82000000 0x1 0x00000000 MBUS_ID(0x04, 0x59) 0x0 0x1 0x00000000>, /* Port 0.0 Mem */ + <0x81000000 0x1 0x00000000 MBUS_ID(0x04, 0x51) 0x0 0x1 0x00000000>; /* Port 0.0 I/O */ + + pcie0: pcie@1,0 { + status = "disabled"; + reg = <0x0800 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + assigned-addresses = <0x82000800 0x0 0x40000 0x0 0x2000>, /* Port 0.0 Internal registers */ + <0x82000800 0x0 0xf0000000 0x0 0x10000000>; /* Port 0.0 Config space registers */ + ranges = <0x82000000 0x0 0x0 0x82000000 0x1 0x00000000 0x1 0x00000000>, /* Port 0.0 Mem */ + <0x81000000 0x0 0x0 0x81000000 0x1 0x00000000 0x1 0x00000000>; /* Port 0.0 I/O */ + bus-range = <0x00 0xff>; + + clocks = <&core_clk 0>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + + #interrupt-cells = <1>; + interrupt-names = "intx", "error"; + interrupts = <11>, <10>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + crypto_sram: sa-sram { compatible = "mmio-sram"; reg = ;