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Wed, 25 Jan 2017 11:52:14 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH 1/2] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks Date: Wed, 25 Jan 2017 12:51:57 +0100 Message-id: <1485345118-3082-2-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485345118-3082-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGIsWRmVeSWpSXmKPExsWy7djPc7pFEzsiDOYeY7LYOGM9q8X1L89Z Lc6f38BuMeP8PiaLtUfuslscftPO6sDmsWlVJ5tH35ZVjB6fN8kFMEdx2aSk5mSWpRbp2yVw ZVxYyVNwhr/i9ub7LA2M+3i7GDk5JARMJObf/sQIYYtJXLi3nq2LkYtDSGAZo8TLhTvYQBJC Ap8ZJW7N8YJpaNj+kQmuaN7JHhYIp4FJYvLHy+wgVWwChhJdb7vAukUEVCU+ty1gByliFnjK KHFvcQsTSEJYIEziyPYDrF2MHBwsQEXX54aDmLwC7hILZptALJOTOHlsMiuIzSngIfH2Vycr yBgJgetsEm8+d4C1SgjISmw6wAxhukicXW4G0Sos8er4FnYIW0ais+MgE4TdzyjR1KoNYc9g lDj3FhoQ1hKHj18EW8UswCcxadt0qJG8Eh1tQhAlHhIzb02FGuMocfrlf3aIz2czShz/toB5 AqPMAkaGVYwiqaXFuempxYZ6xYm5xaV56XrJ+bmbGIGxefrf8fc7GJ82hxxiFOBgVOLhfZHS HiHEmlhWXJl7iFGCg1lJhNehpSNCiDclsbIqtSg/vqg0J7X4EKM0B4uSOO/eBVfChQTSE0tS s1NTC1KLYLJMHJxSDYzSl9XEpUSFT0j7r7ZcxrV63WLhtgmfBVTnSP4UXMasIh4Zxr9S99tk 2ysLy33usPyLl3eWlTWZ5uhyu5FN1zqUu/L1v2tTquT+6YpWLthjHXGcyTZoeuH0Dd+bPk9r O/+tYINm8xHP9hyFmKUy8kIh96Q7vs5ebnNlX1Nszd5H37JlzrVVH1ViKc5INNRiLipOBADq 4/iyyQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsVy+t/xy7prJ3ZEGDT0mltsnLGe1eL6l+es FufPb2C3mHF+H5PF2iN32S0Ov2lndWDz2LSqk82jb8sqRo/Pm+QCmKPcbDJSE1NSixRS85Lz UzLz0m2VQkPcdC2UFPISc1NtlSJ0fUOClBTKEnNKgTwjAzTg4BzgHqykb5fglnFhJU/BGf6K 25vvszQw7uPtYuTkkBAwkWjY/pEJwhaTuHBvPRuILSSwhFFi7YaELkYuILuJSeLkrY0sIAk2 AUOJrrddYEUiAqoSn9sWsIMUMQs8Z5R4v7sfqIiDQ1ggTOJ0uzeIyQJUc31uOIjJK+AusWC2 CcQqOYmTxyazgticAh4Sb391skKsdZeYu/gJ0wRG3gWMDKsYRVJLi3PTc4sN9YoTc4tL89L1 kvNzNzECw3TbsZ+bdzBe2hh8iFGAg1GJh3dCUnuEEGtiWXFl7iFGCQ5mJRFeh5aOCCHelMTK qtSi/Pii0pzU4kOMpkAnTWSWEk3OB8ZQXkm8oYmhuaWhkbGFhbmRkZI4b8mHK+FCAumJJanZ qakFqUUwfUwcnFINjPP3FCyLqXdY/DpFT41b+mP1xbadHavvZqRkPMtR/7b7t3Kffl6T/fF5 BW0iU5p+TUpy2c3UrFCwfUnzr1u3bwh2VFjppfbm9a1Z+fClYYzVhfmcxpmiLU/csx9o/nj2 Jfzgtr6VM7XF6mdN2M4S2MC6q+B+rELKRSFb5lt6Dr6Lp29ZvM43X4mlOCPRUIu5qDgRAOAh 1YppAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170125115214eucas1p1517ce7ca8fe88e4742a1306630b91d09 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170125115214eucas1p1517ce7ca8fe88e4742a1306630b91d09 X-RootMTR: 20170125115214eucas1p1517ce7ca8fe88e4742a1306630b91d09 References: <1485345118-3082-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- include/dt-bindings/clock/exynos5433.h | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 0db5204c307c..1ab4fca255e1 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -2559,8 +2559,10 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np) FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), /* PHY clocks from MIPI_DPHY0 */ - FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), - FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", + NULL, 0, 188000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", + NULL, 0, 100000000), /* PHY clocks from HDMI_PHY */ FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", NULL, 0, 300000000), diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 4fa6bb2136e3..be39d23e6a32 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -771,7 +771,10 @@ #define CLK_PCLK_DECON 113 -#define DISP_NR_CLK 114 +#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 +#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 + +#define DISP_NR_CLK 116 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 From patchwork Wed Jan 25 11:51:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 92437 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp2170668qgi; Wed, 25 Jan 2017 03:52:46 -0800 (PST) X-Received: by 10.98.8.11 with SMTP id c11mr46132446pfd.135.1485345166770; Wed, 25 Jan 2017 03:52:46 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 25 Jan 2017 11:52:14 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH 2/2] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e Date: Wed, 25 Jan 2017 12:51:58 +0100 Message-id: <1485345118-3082-3-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485345118-3082-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsWy7djP87r5EzsiDC7P0bfYOGM9q8X1L89Z Lc6f38BuMeP8PiaLtUfuslscftPO6sDmsWlVJ5tH35ZVjB6fN8kFMEdx2aSk5mSWpRbp2yVw ZUz79oK54K5QxaUFh5gbGJ/wdzFyckgImEh8/LuFHcIWk7hwbz1bFyMXh5DAUkaJL5t+s0A4 nxklHmzazwbTsX9NN1TVMkaJiT1rmSCcBiaJyR8vg81iEzCU6HrbBdYhIqAq8bltATtIEbPA U0aJe4tbmEASwgKJEs3/poMVsQAVnVwylRXE5hVwl3jwZSszxDo5iZPHJoPFOQU8JN7+6mQF GSQhcJtNYvmNRqBBHECOrMSmA8wQpovE3HN1EK3CEq+Ow/wmI3F5cjcLhN3PKNHUqg1hz2CU OPeWF8K2ljh8/CLYKmYBPolJ26ZDjeSV6GgTgijxkLj2dRbUZY4Sv+b8gvp9NqPEgkUbGScw yixgZFjFKJJaWpybnlpsrFecmFtcmpeul5yfu4kRGKOn/x3/tIPx6wmrQ4wCHIxKPLwvUtoj hFgTy4orcw8xSnAwK4nwOrR0RAjxpiRWVqUW5ccXleakFh9ilOZgURLn3bPgSriQQHpiSWp2 ampBahFMlomDU6qBca78l2AX14QTjVd+lShdqZQ99HnfmYePV+nWvljFNal4jvzBW1NnhU7t MDg225AvX+f80ntLHpnNvPT69AmNt6d4PebzPj0ZH3HLp+q1X9XBZBG9O/4nHLcVupzc8TBI 2ythssL89Y6dZ6+1iLZrXm/V/nmi5Ox1cf4960Ofy5Qxb3143PZPrr0SS3FGoqEWc1FxIgCq 5dA+zQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrFLMWRmVeSWpSXmKPExsVy+t/xy7o5EzsiDG5cEbDYOGM9q8X1L89Z Lc6f38BuMeP8PiaLtUfuslscftPO6sDmsWlVJ5tH35ZVjB6fN8kFMEe52WSkJqakFimk5iXn p2TmpdsqhYa46VooKeQl5qbaKkXo+oYEKSmUJeaUAnlGBmjAwTnAPVhJ3y7BLWPatxfMBXeF Ki4tOMTcwPiEv4uRk0NCwERi/5puNghbTOLCvfVgtpDAEkaJ4w1WXYxcQHYTk8TJWxtZQBJs AoYSXW+7wIpEBFQlPrctYAcpYhZ4zijxfnc/WJGwQKJE87/pYEUsQEUnl0xlBbF5BdwlHnzZ ygyxTU7i5LHJYHFOAQ+Jt786WSE2u0vMXfyEaQIj7wJGhlWMIqmlxbnpucVGesWJucWleel6 yfm5mxiB4brt2M8tOxi73gUfYhTgYFTi4Z2Q1B4hxJpYVlyZe4hRgoNZSYTXoaUjQog3JbGy KrUoP76oNCe1+BCjKdBRE5mlRJPzgbGUVxJvaGJobmloZGxhYW5kpCTOO/XDlXAhgfTEktTs 1NSC1CKYPiYOTqkGxvz5RkdK7iz+KDBPVE5EiknkiItUSlNa+tO0hifnnycKtz9Wv7a2pchT 0eyXl/nTNo9n7tc3z+BTmfOg9U6rHs8te/UCHefsZdc+OLUuWhq5++KluXO8lTWWLaneI5w1 df0Fpqayec9V2zT//1o9/0x7+sHbk08E7Z7Qv1/t0aFdvIxzngRvT1BiKc5INNRiLipOBACr 1R3vbQIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170125115215eucas1p239b83cbdfead5b59e3cbbc6e3d3a4b22 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170125115215eucas1p239b83cbdfead5b59e3cbbc6e3d3a4b22 X-RootMTR: 20170125115215eucas1p239b83cbdfead5b59e3cbbc6e3d3a4b22 References: <1485345118-3082-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add initial clock configuration for display subsystem for Exynos5433 based TM2/TM2e boards in device tree in order to avoid dependency on the configuration left by the bootloader. This initial configuration is also needed to ensure that display subsystem is operational if display power domain gets turned off before clock controller is probed and the inital clock configuration left by the bootloader saved. Signed-off-by: Marek Szyprowski --- .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 25 ++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Chanwoo Choi diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 13a0950b57e2..1b9a8a92a40c 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -218,15 +218,32 @@ }; &cmu_disp { - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <0>, + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; - assigned-clock-rates = <0>, <400000000>; + assigned-clock-rates = <266000000>, <400000000>; }; &cmu_fsys {