From patchwork Thu Aug 4 10:49:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 595929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C81BBC19F2B for ; Thu, 4 Aug 2022 10:49:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238438AbiHDKta (ORCPT ); Thu, 4 Aug 2022 06:49:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231555AbiHDKt3 (ORCPT ); Thu, 4 Aug 2022 06:49:29 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BEAD5018F for ; Thu, 4 Aug 2022 03:49:28 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E373AB82449 for ; Thu, 4 Aug 2022 10:49:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B8BDC433D7; Thu, 4 Aug 2022 10:49:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659610165; bh=QqMenMtuuDz9IMUdXlJREV9LB27AexWX4PM5ieA0+6o=; h=From:To:Cc:Subject:Date:From; b=sxrsGHv0sLsAxMeOSmYMw08id1xgS0ORUIQDMJpROZ+s+/IUaHixolxrK/1BNhe36 owcjCDRI7TUGtXMqrxHmTg/990f1tDkX6rJcjED0w0gZkdcLcQdmDU4+TGkG64/n9J p2rZv2ye3RwasWLYUDQijci0LRng+0ymSPvfh1bAQ8NcqDZRuzktOnNzAuwv9bic5d rJtdGy10rZz3rusWLbhWyKlzsN10+enQTeJ1kfD2ldNyKXQ0l2jGEGkoPdPt6oMJJ1 7ocorlKEbmAgyAcIyv1j5y8irKKAfWdwtRWHuY0kOlHx24KWRcf9P4L8jl360eBeTN qiwcW4bJ1Y4rg== Received: by pali.im (Postfix) id 4077380A; Thu, 4 Aug 2022 12:49:22 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Linus Walleij Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH 1/4] pinctrl: armada-37xx: Add missing GPIO-only pins Date: Thu, 4 Aug 2022 12:49:12 +0200 Message-Id: <20220804104915.23719-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org gpio1_5 and gpio2_2 are GPIO-only pins. Add them into MPP groups table so they are properly exported as valid pin numbers. Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Pali Rohár --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index a140b6bfbfaa..2b44c634ccb5 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -122,6 +122,16 @@ struct armada_37xx_pinctrl { .funcs = {_func1, _func2} \ } +#define PIN_GRP_GPIO_0(_name, _start, _nr) \ + { \ + .name = _name, \ + .start_pin = _start, \ + .npins = _nr, \ + .reg_mask = 0, \ + .val = {0}, \ + .funcs = {"gpio"} \ + } + #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ { \ .name = _name, \ @@ -179,6 +189,7 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { "pwm", "led"), PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), + PIN_GRP_GPIO_0("gpio1_5", 5, 1), PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), @@ -195,6 +206,7 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), + PIN_GRP_GPIO_0("gpio2_2", 2, 1), PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), From patchwork Thu Aug 4 10:49:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 595416 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E311C19F2D for ; Thu, 4 Aug 2022 10:49:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231555AbiHDKtb (ORCPT ); Thu, 4 Aug 2022 06:49:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229575AbiHDKt3 (ORCPT ); Thu, 4 Aug 2022 06:49:29 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58A723DF39 for ; Thu, 4 Aug 2022 03:49:28 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 12EC5B8119C for ; Thu, 4 Aug 2022 10:49:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB944C433D6; Thu, 4 Aug 2022 10:49:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659610165; bh=b9e6f7QyGeXEQipqkQe1Q41JGjIlUd+dl7sHDQm0Ydk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ehtn3dbiSEZXepJZAn3FacrPg3pc9uU+6q6kjcm/raUKTMxl3PoxhiY9EXpdQ1grx itl5BakRyuDs0t0bcSxYyoEKOWhHJAPByPjfSOT1M7XUdhExr/DKFyP45D2d774wyD ohWnrMSml9OWf8lxH327osU/Uxenulu9YI0UoW9/Z7jO/wEQlhBc4h9Sf2WN++sMuZ /V7EOL41yneTHrsH1Y0RluZ3c11cCTNbkoCDjUH5mtkNcPG9HjJEraVChr6oGUKlUt X4ilM3APNdpQBlm/hj4tUr1wZ2kOMU0UGI9son5UDfGb3QiDHx2A4qb6XSuqMZcumN Xy32oPprQ43qQ== Received: by pali.im (Postfix) id 2748AAC9; Thu, 4 Aug 2022 12:49:23 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Linus Walleij Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH 2/4] pinctrl: armada-37xx: Fix definitions for MPP pins 20-22 Date: Thu, 4 Aug 2022 12:49:13 +0200 Message-Id: <20220804104915.23719-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220804104915.23719-1-pali@kernel.org> References: <20220804104915.23719-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org All 3 MPP pins (20, 21 and 22) can be configured individually and also can be configured to GPIO functions. Fix definitions for these MPP pins in existing pin groups. After this change GPIO function can be enabled just for one of these 3 pins. Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Pali Rohár --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 2b44c634ccb5..e5e5f0ea0e77 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -213,9 +213,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), + "ptp", "mii"), + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), + "ptp", "mii"), PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), "mii", "mii_err"), }; From patchwork Thu Aug 4 10:49:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 595928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF9C9C3F6B0 for ; Thu, 4 Aug 2022 10:49:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229575AbiHDKtd (ORCPT ); Thu, 4 Aug 2022 06:49:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238145AbiHDKta (ORCPT ); Thu, 4 Aug 2022 06:49:30 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5309E5019F for ; Thu, 4 Aug 2022 03:49:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 01150B824E4 for ; Thu, 4 Aug 2022 10:49:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F576C43470; Thu, 4 Aug 2022 10:49:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659610166; bh=NRYgkbOBZl35JeLYiTrlSXLZ0yPBiRFJgFdAcvvkHxU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g2ik1eaEM/rZo+hFWBRmv3Rk+FDT+ZJALZe7ymjJyFELnmquWZgpeqcp991scGS8l 5o1Tw95zcFU2HSUVE+5coEt2Cw/+tqdI281hr5yBGGN9A1azI7n33or5w7DSnU0dLf FamgLbC9AnUfZwDPndvH31IKMBrug8ZWJktIA0vovLV5pMb/y8tA8Szmh903v2v5ZJ VLND6qC1KDVC4gHhCjM7mO6Vf0oayXaYXYWZynBi5OXffA78vBbE8lD92KdKYviqwv Kyj84Y5MHLAzF5SPdCUP9yQRypFl61tC2HSZsudY2+zVJy3DeEnx2TOa+maRzxG6nt aUQqnLrkpzpUA== Received: by pali.im (Postfix) id 0FF91B01; Thu, 4 Aug 2022 12:49:24 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Linus Walleij Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH 3/4] pinctrl: armada-37xx: Checks for errors in gpio_request_enable callback Date: Thu, 4 Aug 2022 12:49:14 +0200 Message-Id: <20220804104915.23719-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220804104915.23719-1-pali@kernel.org> References: <20220804104915.23719-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Now when all MPP pins are properly defined and every MPP pin has GPIO function, always checks for errors in armada_37xx_gpio_request_enable() function when calling armada_37xx_pmx_set_by_name(). Function armada_37xx_pmx_set_by_name() should not return "not supported" error anymore for any GPIO pin when requesting GPIO mode. Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Pali Rohár --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index e5e5f0ea0e77..8978e6c15905 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -503,8 +503,11 @@ static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev, dev_dbg(info->dev, "requesting gpio %d\n", offset); - while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) - armada_37xx_pmx_set_by_name(pctldev, "gpio", group); + while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) { + ret = armada_37xx_pmx_set_by_name(pctldev, "gpio", group); + if (ret) + return ret; + } return 0; } From patchwork Thu Aug 4 10:49:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 595415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ADFCC19F2B for ; Thu, 4 Aug 2022 10:49:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231946AbiHDKte (ORCPT ); Thu, 4 Aug 2022 06:49:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238427AbiHDKta (ORCPT ); Thu, 4 Aug 2022 06:49:30 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFFCA3DF39 for ; Thu, 4 Aug 2022 03:49:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 75C0DB82510 for ; Thu, 4 Aug 2022 10:49:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11E3AC43141; Thu, 4 Aug 2022 10:49:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659610167; bh=1rb6O8LRdwEcTR40sjSsN+WfgRWcVvhq+f42Fyg1OW8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vBTzW6oI6uguIyuzonnR/66G5d4XkxfKmdqY+HsKz0HP3J3iDgWTH1gwIwSozqSD4 W0olwUkNn2wXPdJHXXcBb2jw2YC5mDnnKiIUrqveYnTnwYQkIXOWDxsHsucGhc4/qG SGaGDk2JoReERhEetWk3wa2llIAzdAKv+Kc7mPamUJovmtWRij4UyLNnrF+hxoFKZN pUP07ZZfD7BusD9NJQ7RxSfF+FqiOtv/IHaKsws2h5wyQvL6Pc832Lc8yCuanFkWwB He4scGy1E+cQJS134EVg9rpJVROaNvjx1SgLvE5ueJRcr9aYiAtzBcPOnPL4viFEgO N1FIvFqdhOH1g== Received: by pali.im (Postfix) id B7FFAB0F; Thu, 4 Aug 2022 12:49:24 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Linus Walleij Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH 4/4] pinctrl: armada-37xx: Remove unused macro PIN_GRP() Date: Thu, 4 Aug 2022 12:49:15 +0200 Message-Id: <20220804104915.23719-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220804104915.23719-1-pali@kernel.org> References: <20220804104915.23719-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Macro PIN_GRP() is not used, remove it. Signed-off-by: Pali Rohár --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 8978e6c15905..1b48c4db2f28 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -112,16 +112,6 @@ struct armada_37xx_pinctrl { struct armada_37xx_pm_state pm; }; -#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ - { \ - .name = _name, \ - .start_pin = _start, \ - .npins = _nr, \ - .reg_mask = _mask, \ - .val = {0, _mask}, \ - .funcs = {_func1, _func2} \ - } - #define PIN_GRP_GPIO_0(_name, _start, _nr) \ { \ .name = _name, \