From patchwork Wed Aug 10 08:59:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 596632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC715C00140 for ; Wed, 10 Aug 2022 09:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231750AbiHJJAX (ORCPT ); Wed, 10 Aug 2022 05:00:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231893AbiHJJAU (ORCPT ); Wed, 10 Aug 2022 05:00:20 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EF061AF06; Wed, 10 Aug 2022 02:00:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660122019; x=1691658019; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=c2PE8iAmkH1Oin6CAU5HGkAjPeE646cGNzdZY+RUVJE=; b=Fvs1ad2/F30RaGRq+xTBsaILfwopkHMilluA7w/4fav6NBXoVer+ry9G RPx5AsXT/sLkJpd4p02VUJyKF7aVT1oZHXk1AXfm1jLeuu0bFHB6N0WMj RjI2t8NRNnGvf4JF1Oyksp23xCpKUPR4bMEglCaWMuisW846kWfPOhlyX SsXm8CjSFzKZ7V2uyf0y+S8NdFVGAbptQxdTBwc5kaB0G6FpWNis0dAKW 66OB1jul6hIbeNF/W3KN1CBKLXzARmh1YKPtMUcaDSboZ23JdBdT0KAYL ZGV2k1ZkgS3R1siSZFOXcPBWA4NkbrUAqF0b4vNusJXMpsF4esRCgCKhQ A==; X-IronPort-AV: E=Sophos;i="5.93,226,1654585200"; d="scan'208";a="108383200" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Aug 2022 02:00:18 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 10 Aug 2022 02:00:13 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Wed, 10 Aug 2022 02:00:11 -0700 From: Conor Dooley To: Conor Dooley , Daire McNamara CC: , , , , , , , , Subject: [PATCH] riscv: dts: microchip: add qspi compatible fallback Date: Wed, 10 Aug 2022 09:59:15 +0100 Message-ID: <20220810085914.801170-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The "hard" QSPI peripheral on PolarFire SoC is derived from version 2 of the FPGA IP core. The original binding had no fallback etc, so this device tree is valid as is. There was also no functional driver for the QSPI IP, so no device with a devicetree from a previous mainline release will regress. Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/ Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- See the link for binding discussion. I'll apply this at some point once the driver makes it upstream. CC: nagasuresh.relli@microchip.com CC: valentina.fernandezalanis@microchip.com CC: broonie@kernel.org CC: devicetree@vger.kernel.org CC: krzysztof.kozlowski+dt@linaro.org CC: robh+dt@kernel.org CC: linux-kernel@vger.kernel.org CC: linux-spi@vger.kernel.org CC: linux-riscv@lists.infradead.org --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 499c2e63ad35..45e3cc659882 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -330,7 +330,7 @@ spi1: spi@20109000 { }; qspi: spi@21000000 { - compatible = "microchip,mpfs-qspi"; + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21000000 0x0 0x1000>;