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Thu, 11 Aug 2022 12:42:51 +0000 From: Shenwei Wang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linus.walleij@linaro.org, brgl@bgdev.pl, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Shenwei Wang Subject: [PATCH v4 1/3] dt-bindings: gpio: Add imx scu gpio driver bindings Date: Thu, 11 Aug 2022 07:41:33 -0500 Message-Id: <20220811124135.95299-2-shenwei.wang@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220811124135.95299-1-shenwei.wang@nxp.com> References: <20220811124135.95299-1-shenwei.wang@nxp.com> X-ClientProxiedBy: SJ0PR13CA0064.namprd13.prod.outlook.com (2603:10b6:a03:2c4::9) To AM9PR04MB8274.eurprd04.prod.outlook.com (2603:10a6:20b:3e8::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8fd9f30e-1300-488b-8833-08da7b970127 X-MS-TrafficTypeDiagnostic: VI1PR0402MB2832:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Shenwei Wang --- .../bindings/gpio/fsl,imx-sc-gpio.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/fsl,imx-sc-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/fsl,imx-sc-gpio.yaml b/Documentation/devicetree/bindings/gpio/fsl,imx-sc-gpio.yaml new file mode 100644 index 000000000000..a1b024cddc97 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/fsl,imx-sc-gpio.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/fsl,imx-sc-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO driver over IMX SCU firmware API + +maintainers: + - Shenwei Wang + +description: | + This module provides the standard interface to control the + resource pins in SCU domain on i.MX8 platforms. + +properties: + compatible: + enum: + - fsl,imx8qxp-sc-gpio + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +examples: + - | + gpio0: gpio { + compatible = "fsl,imx8qxp-sc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; From patchwork Thu Aug 11 12:41:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 597126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1785C19F2A for ; Thu, 11 Aug 2022 12:43:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235345AbiHKMnY (ORCPT ); Thu, 11 Aug 2022 08:43:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235338AbiHKMnX (ORCPT ); Thu, 11 Aug 2022 08:43:23 -0400 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80057.outbound.protection.outlook.com [40.107.8.57]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 926C189827; 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Thu, 11 Aug 2022 12:43:19 +0000 From: Shenwei Wang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linus.walleij@linaro.org, brgl@bgdev.pl, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Shenwei Wang , Krzysztof Kozlowski Subject: [PATCH v4 2/3] dt-bindings: firmware: imx: Add imx-scu gpio node Date: Thu, 11 Aug 2022 07:41:34 -0500 Message-Id: <20220811124135.95299-3-shenwei.wang@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220811124135.95299-1-shenwei.wang@nxp.com> References: <20220811124135.95299-1-shenwei.wang@nxp.com> X-ClientProxiedBy: SJ0PR05CA0042.namprd05.prod.outlook.com (2603:10b6:a03:33f::17) To AM9PR04MB8274.eurprd04.prod.outlook.com (2603:10a6:20b:3e8::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c2cacd12-eae8-44b7-3490-08da7b9711de X-MS-TrafficTypeDiagnostic: VI1PR0402MB2832:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Shenwei Wang Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/firmware/fsl,scu.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml index b40b0ef56978..1fe61c2599e4 100644 --- a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml @@ -30,6 +30,11 @@ properties: Clock controller node that provides the clocks controlled by the SCU $ref: /schemas/clock/fsl,scu-clk.yaml + gpio: + description: + Control the GPIO PINs on SCU domain over the firmware APIs + $ref: /schemas/gpio/fsl,imx-sc-gpio.yaml + ocotp: description: OCOTP controller node provided by the SCU From patchwork Thu Aug 11 12:41:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 596749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE031C19F2D for ; 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This patch implements the standard GPIO driver interface to access those PINs on the SCU domain over the SCU APIs. Signed-off-by: Shenwei Wang --- drivers/gpio/Kconfig | 4 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-imx-scu.c | 139 ++++++++++++++++++++++++++++++++++++ 3 files changed, 144 insertions(+) create mode 100644 drivers/gpio/gpio-imx-scu.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0499c2facbb0..b01310f6ebcc 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -341,6 +341,10 @@ config GPIO_ICH If unsure, say N. +config GPIO_IMX_SCU + def_bool y + depends on IMX_SCU + config GPIO_IOP tristate "Intel IOP GPIO" depends on ARCH_IOP32X || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 3fa4f3f93d85..b39ab87793ec 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o obj-$(CONFIG_GPIO_I8255) += gpio-i8255.o obj-$(CONFIG_GPIO_ICH) += gpio-ich.o obj-$(CONFIG_GPIO_IDT3243X) += gpio-idt3243x.o +obj-$(CONFIG_GPIO_IMX_SCU) += gpio-imx-scu.o obj-$(CONFIG_GPIO_IOP) += gpio-iop.o obj-$(CONFIG_GPIO_IT87) += gpio-it87.o obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4xx.o diff --git a/drivers/gpio/gpio-imx-scu.c b/drivers/gpio/gpio-imx-scu.c new file mode 100644 index 000000000000..17be21b8f3b7 --- /dev/null +++ b/drivers/gpio/gpio-imx-scu.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2021~2022 NXP + * + * The driver exports a standard gpiochip interface + * to control the PIN resources on SCU domain. + */ + +#include +#include +#include +#include +#include + +struct scu_gpio_priv { + struct gpio_chip chip; + struct mutex lock; + struct device *dev; + struct imx_sc_ipc *handle; +}; + +static unsigned int scu_rsrc_arr[] = { + IMX_SC_R_BOARD_R0, + IMX_SC_R_BOARD_R1, + IMX_SC_R_BOARD_R2, + IMX_SC_R_BOARD_R3, + IMX_SC_R_BOARD_R4, + IMX_SC_R_BOARD_R5, + IMX_SC_R_BOARD_R6, + IMX_SC_R_BOARD_R7, +}; + +static int imx_scu_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct scu_gpio_priv *priv = gpiochip_get_data(chip); + int level; + int err; + + if (offset >= chip->ngpio) + return -EINVAL; + + mutex_lock(&priv->lock); + + /* to read PIN state via scu api */ + err = imx_sc_misc_get_control(priv->handle, + scu_rsrc_arr[offset], 0, &level); + mutex_unlock(&priv->lock); + + if (err) { + dev_err(priv->dev, "SCU get failed: %d\n", err); + return err; + } + + return level; +} + +static void imx_scu_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct scu_gpio_priv *priv = gpiochip_get_data(chip); + int err; + + if (offset >= chip->ngpio) + return; + + mutex_lock(&priv->lock); + + /* to set PIN output level via scu api */ + err = imx_sc_misc_set_control(priv->handle, + scu_rsrc_arr[offset], 0, value); + mutex_unlock(&priv->lock); + + if (err) + dev_err(priv->dev, "SCU set (%d) failed: %d\n", + scu_rsrc_arr[offset], err); +} + +static int imx_scu_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + if (offset >= chip->ngpio) + return -EINVAL; + + return GPIO_LINE_DIRECTION_OUT; +} + +static int imx_scu_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct scu_gpio_priv *priv; + struct gpio_chip *gc; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ret = imx_scu_get_handle(&priv->handle); + if (ret) + return ret; + + priv->dev = dev; + mutex_init(&priv->lock); + + gc = &priv->chip; + gc->base = -1; + gc->parent = dev; + gc->ngpio = sizeof(scu_rsrc_arr)/sizeof(unsigned int); + gc->label = dev_name(dev); + gc->get = imx_scu_gpio_get; + gc->set = imx_scu_gpio_set; + gc->get_direction = imx_scu_gpio_get_direction; + + platform_set_drvdata(pdev, priv); + + return devm_gpiochip_add_data(dev, gc, priv); +} + +static const struct of_device_id imx_scu_gpio_dt_ids[] = { + { .compatible = "fsl,imx8qxp-sc-gpio" }, + { /* sentinel */ } +}; + +static struct platform_driver imx_scu_gpio_driver = { + .driver = { + .name = "gpio-imx-scu", + .of_match_table = imx_scu_gpio_dt_ids, + }, + .probe = imx_scu_gpio_probe, +}; + +static int __init _imx_scu_gpio_init(void) +{ + return platform_driver_register(&imx_scu_gpio_driver); +} + +subsys_initcall_sync(_imx_scu_gpio_init); + +MODULE_AUTHOR("Shenwei Wang "); +MODULE_DESCRIPTION("NXP GPIO over IMX SCU API"); +MODULE_LICENSE("GPL");