From patchwork Wed Aug 17 20:05:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 597966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C7B7C25B08 for ; Wed, 17 Aug 2022 20:06:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241714AbiHQUF6 (ORCPT ); Wed, 17 Aug 2022 16:05:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230051AbiHQUF4 (ORCPT ); Wed, 17 Aug 2022 16:05:56 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40ED45D0C0 for ; Wed, 17 Aug 2022 13:05:54 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id n7so6200713wrv.4 for ; Wed, 17 Aug 2022 13:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vuO3cD7vHfOoM26qaFlIa3/qXvWH4JaTB3axSBEJPBw=; b=aLff/SU5U5NCprD2QuW81ZfqWPcaSFXlXSbnm3nBxoThVUuC+erRdVodWmcN79GWR3 x6K8q62Y/aYgL/FZR7jCoVAQly7asoaWMM3eg4Sn7jt91w07TL5ryQcaxYoFF6mtw7x7 WyCWzHVrw1kx1hzhuGNSQ8Z1QZLPIxrOSVAv5jzhEYz5lNvczMpa1TQU+b0Tf7qi+ALt tyUURhWEo6A/4e0QPQ+c9f7f1yX97VvMESe+aAoTJFbFqSFzjrwU8WvqNZnisdvUVt5J zfYmHcItVD5nQhI8sOUgr2pTtd/SmXdJo6yVsTj0KdxUltsCv4tc4rsYkjw0cepkFKbm LQTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vuO3cD7vHfOoM26qaFlIa3/qXvWH4JaTB3axSBEJPBw=; b=VJyPVGIplLILZgoCAbOD04mchU8aQP+jpv9fbouDGCJG7/9X11WiiDwXf5r8MV+JW+ UwiDqmI77owFxWoKhRqQmFbjJkdrRm7yh+JvFK5uTpfA2Uvh88O77ADT7LhT25HBf7G0 fDKWbYNWaGpOuMMkrEzQ+BDIJ3ioAfoGQdycQj8EP7XajcxpRV/JrQtDEN/QCz4h54Pm fGeofFaOWzHFa7AtvjyD/nrQYrEcfpsP2C+GaOv7uqUFJQP11U0XIFLPAFJAkEZi5Y7w uiknuzgzvsfSZbeyYsIDUtuW6ivQ7quR5k9xEp1GsMVabtcCCf7RcVH27gN2R4yxQnbU OI/w== X-Gm-Message-State: ACgBeo0aYEaZZuxeqMCssUfPj/DI/Yi/xzNlfBxqxOB5ECzIOF/VYgYT xsxv5IU78pwuUFkijbtmoCia0A== X-Google-Smtp-Source: AA6agR6xInXHiAM2BCLKV9u+fYev1yEmFG0NjjMiZhNBeLkYTbhJq4za1Z3qh97Ys5ZCdjUKqm17DQ== X-Received: by 2002:a05:6000:1b92:b0:220:7d86:2e30 with SMTP id r18-20020a0560001b9200b002207d862e30mr15678682wru.530.1660766752738; Wed, 17 Aug 2022 13:05:52 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i133-20020a1c3b8b000000b003a531c7aa66sm3400883wma.1.2022.08.17.13.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 13:05:51 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible Date: Wed, 17 Aug 2022 21:05:21 +0100 Message-Id: <20220817200531.988850-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817200531.988850-1-mail@conchuod.ie> References: <20220817200531.988850-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley While "real" hardware might not use the compatible string "riscv,plic0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic'] 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] 'sifive,plic-1.0.0' was expected 'thead,c900-plic' was expected riscv-virt.dtb: plic@c000000: '#address-cells' is a required property Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Signed-off-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 92e0f8c3eff2..99e01f4d0a69 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -66,6 +66,11 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - items: + - const: sifive,plic-1.0.0 + - const: riscv,plic0 + deprecated: true + description: For the QEMU virt machine only reg: maxItems: 1 From patchwork Wed Aug 17 20:05:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 597965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A6EEC25B08 for ; Wed, 17 Aug 2022 20:06:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238642AbiHQUGF (ORCPT ); Wed, 17 Aug 2022 16:06:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241719AbiHQUF7 (ORCPT ); Wed, 17 Aug 2022 16:05:59 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16B6A83BE3 for ; Wed, 17 Aug 2022 13:05:58 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id s23so7146754wmj.4 for ; Wed, 17 Aug 2022 13:05:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=MSYB9FwL7p/iJdXtPMVngWpHWItwLj/alFVUIh6RUfI=; b=aalXbJEtEyz0fdYAOCKPabkxfm+u5zzEGFKYYYxBeomEWGFk/ytTvkEEfWKdBZ9qam wwPT8nrUrsYfzpKtV1r1kCaWqWs7YknEFQ+aMuxIJu94oyoYyqccYk++TUEtq7RdJvKO MzSWpQ8GV7vEXfBNVWpGsamiURxgJnsbxc7XXf53ogih2Ou90s3e7mUu35VW3GIQCSSw JPvYuuH7VSB7jfYTR68yLcDpE1FtIEkttItkbc9J1nSS2wMYrQSwMbS4hn8f9anRfmWP 24Hrem9kUuAlsAO5ml5foFmLYM1OVh5ICRpf43152oMEX3Pn0AUq0pEnXNS1n6QB9vsm c8qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=MSYB9FwL7p/iJdXtPMVngWpHWItwLj/alFVUIh6RUfI=; b=w24eWS2AK+Hk0rYPo5Gf3gtBePZcCzmKIWLsFsi40NKLJ/u7RV5a1P7o4A/UHgkOYG LU+Crf8B/iWhFF6codEE8aTj9t2SUt8WBCQ9wtN8Us4a6SujTF07X+XkNKsgKCJxg4G5 wbtCkQJT8FUMFXnZsCH7DX+vlENWAGp0ZnILA64MrgGUrSC408g8tvASq/wCMflfWKh9 TPOnFKQkwnCdgutc6UmnTY10WMwWSAzvjCgSqED1LAFmTdVZLx9rVwCIpiaWoRfud3wq t6pB9Ul/dRdLllJCcnKiCcOtW1iyNmhFajOgpJvvOBTOBEdf07+YgrNN0kYTlCOh45+y XaoQ== X-Gm-Message-State: ACgBeo20EKwE8EvHC9wogNsXaqPxEKKPC0C2ojYQEH5ygsDZJyQwAw2Q cRo9nX47MCjx+duqz99TIkS2Jdm9/9kBjCcJ X-Google-Smtp-Source: AA6agR5DU5oL31YGMFMqSJ9QosyAIgz1wKmRamOx/HzSICAxr/vstQ62IK8je47MYg2BbSWSiqFh2A== X-Received: by 2002:a7b:cb88:0:b0:3a5:ea1c:c541 with SMTP id m8-20020a7bcb88000000b003a5ea1cc541mr3165264wmi.114.1660766756496; Wed, 17 Aug 2022 13:05:56 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i133-20020a1c3b8b000000b003a531c7aa66sm3400883wma.1.2022.08.17.13.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 13:05:55 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org Subject: [NOT-A-PATCH 4/4] dt-bindings: riscv: isa string bonus content Date: Wed, 17 Aug 2022 21:05:23 +0100 Message-Id: <20220817200531.988850-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817200531.988850-1-mail@conchuod.ie> References: <20220817200531.988850-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley **NOT FOR CONSIDERATION** I figured, sure why not add the strings for version number validation, just in case we need them in the future. The commented out string is considered by dt-schema to be "not a regex", but regex101 thinks it is... Maybe dt-schema does not support named match groups, but they are the only way that I could trivially find to make this somewhat manageable. Either way, it is permissive so it allows combinations of "M", "MpM" & no number. Not-signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c0e0bc5dce04..38a824453012 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,11 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+)*$ + oneOf: + - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+)*$ + - pattern: ^rv(?:64|32)(?:i\d+)(?:m\d+)(?:a\d+)(?:f\d+)?(?:d\d+)?(?:q\d+)?(?:c\d+)?(?:b\d+)?(?:v\d+)?(?:k\d+)?(?:h\d+)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+\d+)*$ + - pattern: ^rv(?:64|32)(?:i\d+p\d+)(?:m\d+p\d+)(?:a\d+p\d+)(?:f\d+p\d+)?(?:d\d+p\d+)?(?:q\d+p\d+)?(?:c\d+p\d+)?(?:b\d+p\d+)?(?:v\d+p\d+)?(?:k\d+p\d+)?(?:h\d+p\d+)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+(?:\d+p\d+))*$ +# - pattern: ^rv(?:64|32)(?:i(?(?:\d+|\d+p\d+)?)?)(?:m(?:\k)?)(?:a(?:\k)?)(?:f(?:\k)?)?(?:d(?:\k)?)?(?:q(?:\k)?)?(?:c(?:\k)?)?(?:b(?:\k)?)?(?:v(?:\k)?)?(?:k(?:\k)?)?(?:h(?:\k)?)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])*(?:\d+|\d+p\d+)?)+$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false