From patchwork Thu Feb 7 11:09:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157709 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp531273jaa; Thu, 7 Feb 2019 03:33:09 -0800 (PST) X-Google-Smtp-Source: AHgI3IY2OsMpItuvgBTQ10pJyYZNXz3FrFEtpr2Wpw6q/Ew8a+pWiykV1kSJV7lTf93a/Jr4uOWf X-Received: by 2002:a17:902:346:: with SMTP id 64mr16291148pld.337.1549539189370; Thu, 07 Feb 2019 03:33:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549539189; cv=none; d=google.com; s=arc-20160816; b=jwGDrJoLMA6cUYgRv0/FJvxdzad7VEyPtDP/HU7wkqhYCuEl+FI4e8pQsP+YsRVm6C 6iU0dAA83AwBmRaJyl88lw6gYHS6seGqPa8/8Fn+t1eVqPZMxEUc5+I/1eL6FoVINoZg TSRA+WoidwWtz6wp9JrTtMOXG+ZrZ5ajAxvr0urnJoBSxORWyGlAuIP/j66AZaBCp8Bx 5lb3dAQzjyfzmYFbxGaCbUrBIr53FmFYKQvwVpG2I7omjZ9usgbx+wZWE+J/rwH42D2x w+7Zn/NWaK4tORhgSlKN0wWrK6rw4TcZrvWEykS0iG6pltbk4QMtqrmK04ZWhfdObQz7 0f9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=GmaChAagvvR3BKGTtUPZxsSHjPP8U/j4RxXcXLkz7sg=; b=DWDCutk56WCLocUhQWG4BnrMrDcvW17qouRTaXVocANvA0aw7UUgN/mSGy+olez8Ud cFjz6LddTaNpQcYqBJId0LggbQweqeyTU9MrMumF2AVO8smmuVdvH7/k4gbhWftIPyfs BkBeQM1YbxC5yaZXZ2uJ5xsW77A5KzYz/cw6RLVqp3tNHfoYJRmwRakInvBOcFA+vl+P YY1zWuKPemQzc9BPmv6SflNzmOjpXZNZ2LQUrSxVCO9mGbTj1JzZmWUcx5Uoml+PV6bT 2WbreHutlLdFQp2umyzv3fRFhHQSKcT047nSUm5f8sJD6ApSXbWozdTuJBY0Ezz/S/y7 +JOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hqc7pMwJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 62si8928955plc.87.2019.02.07.03.33.09; Thu, 07 Feb 2019 03:33:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hqc7pMwJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727061AbfBGLcV (ORCPT + 31 others); Thu, 7 Feb 2019 06:32:21 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59692 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726561AbfBGLcU (ORCPT ); Thu, 7 Feb 2019 06:32:20 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x17BW6c8103799; Thu, 7 Feb 2019 05:32:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549539126; bh=GmaChAagvvR3BKGTtUPZxsSHjPP8U/j4RxXcXLkz7sg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hqc7pMwJ4b6XG+qT73G5qm+xHApuPwCL+g5nay9WReFMPyxY64Q5IOdLOu3d+vx75 bpvDhpSF2Rq2qf0V+w7Gxtq9fMnSxNgKYEg9xQXwvmAmW1aT5QaI+DS+Jtn8DHO4et O78Tu9UNM8fJ7+f7s0L6uQs48HhV8vWv516BosJU= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x17BW6Rl072695 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Feb 2019 05:32:06 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 7 Feb 2019 05:32:06 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 7 Feb 2019 05:32:06 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x17BVxal026282; Thu, 7 Feb 2019 05:32:03 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v2 1/9] PCI: keystone: Cleanup interrupt related macros Date: Thu, 7 Feb 2019 16:39:16 +0530 Message-ID: <20190207110924.30716-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190207110924.30716-1-kishon@ti.com> References: <20190207110924.30716-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Change both MSI interrupt and legacy interrupt related macros to take an additional argument in order to return the correct register offset. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 26 +++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 14f2b0b4ed5e..5286a480f76b 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -52,17 +52,17 @@ /* IRQ register defines */ #define IRQ_EOI 0x050 -#define IRQ_STATUS 0x184 -#define IRQ_ENABLE_SET 0x188 -#define IRQ_ENABLE_CLR 0x18c #define MSI_IRQ 0x054 -#define MSI0_IRQ_STATUS 0x104 -#define MSI0_IRQ_ENABLE_SET 0x108 -#define MSI0_IRQ_ENABLE_CLR 0x10c -#define IRQ_STATUS 0x184 +#define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) +#define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) +#define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) #define MSI_IRQ_OFFSET 4 +#define IRQ_STATUS(n) (0x184 + ((n) << 4)) +#define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) +#define INTx_EN BIT(0) + #define ERR_IRQ_STATUS 0x1c4 #define ERR_IRQ_ENABLE_SET 0x1c8 #define ERR_AER BIT(5) /* ECRC error */ @@ -142,7 +142,7 @@ static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) u32 pending, vector; int src, virq; - pending = ks_pcie_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4)); + pending = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); /* * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit @@ -169,7 +169,7 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_pcie_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), BIT(bit_pos)); ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); } @@ -181,7 +181,7 @@ static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), BIT(bit_pos)); } @@ -192,7 +192,7 @@ static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), BIT(bit_pos)); } @@ -206,7 +206,7 @@ static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) int i; for (i = 0; i < PCI_NUM_INTX; i++) - ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1); + ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), 0x1); } static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, @@ -217,7 +217,7 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, u32 pending; int virq; - pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS + (offset << 4)); + pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); if (BIT(0) & pending) { virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); From patchwork Thu Feb 7 11:09:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157701 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp530557jaa; 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[209.132.180.67]) by mx.google.com with ESMTP id n32si8337430pgm.439.2019.02.07.03.32.27; Thu, 07 Feb 2019 03:32:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=zIPBan9W; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727144AbfBGLcZ (ORCPT + 31 others); Thu, 7 Feb 2019 06:32:25 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59702 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727089AbfBGLcX (ORCPT ); Thu, 7 Feb 2019 06:32:23 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x17BW9eU103813; Thu, 7 Feb 2019 05:32:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549539129; bh=yikLZbiZ7XlBtVkInDXU3WW2M/89dsx2CmievSEZFwA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zIPBan9WFnKykaNJ3mYeGdeO1cDHMLfCuaMKjkgc/+L/VfzFiLAWvrzfk6QEMf3u5 MU4yK3MBZ/gia0Jqan7zsVq2P0cc0u0zxJkDYZE/HJoQIrXoSk6r1KrOYGTlQM3z1K YblD7eFbLUOpWv/hTclyY+2lBtWUOBx4OQ74KfTw= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x17BW9iB021366 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Feb 2019 05:32:09 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 7 Feb 2019 05:32:09 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 7 Feb 2019 05:32:09 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x17BVxam026282; Thu, 7 Feb 2019 05:32:06 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v2 2/9] PCI: keystone: Modify legacy_irq_handler to check the IRQ_STATUS of INTA/B/C/D Date: Thu, 7 Feb 2019 16:39:17 +0530 Message-ID: <20190207110924.30716-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190207110924.30716-1-kishon@ti.com> References: <20190207110924.30716-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The legacy interrupt handler directly checks the IRQ_STATUS register corresponding to a interrupt line inorder to invoke generic_handle_irq. While this is okay for K2G platform which has separate interrupt line for each of the 4 legacy interrupts, AM654 which uses the same PCIe wrapper has a single interrupt line for all the legacy interrupts. So for AM654 the interrupt handler won't be able to directly check the IRQ_STATUS register corresponding to the interrupt line. Also the legacy interrupt handler uses 'virq' obtained from irq_of_parse_and_map to find the correct interrupt line which raised the interrupt. There is no guarantee that virq assigned for contiguous hardware irq will be contiguous and the interrupt handler might end up checking the wrong IRQ_STATUS register. In order to overcome the above issues, read the IRQ_STATUS register of all the 4 legacy interrupts to determine which interrupt was raised. Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d838c@arm.com Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 5286a480f76b..4cf9849d5a1d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -214,16 +214,11 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, { struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; - u32 pending; int virq; - pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); - - if (BIT(0) & pending) { - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); - dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); - generic_handle_irq(virq); - } + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); + dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); + generic_handle_irq(virq); /* EOI the INTx interrupt */ ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); @@ -607,8 +602,9 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; - u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int irq_no; + u32 reg; dev_dbg(dev, ": Handling legacy irq %d\n", irq); @@ -618,7 +614,13 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) * ack operation. */ chained_irq_enter(chip, desc); - ks_pcie_handle_legacy_irq(ks_pcie, irq_offset); + for (irq_no = 0; irq_no < PCI_NUM_INTX; irq_no++) { + reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(irq_no)); + if (!(reg & INTx_EN)) + continue; + ks_pcie_handle_legacy_irq(ks_pcie, irq_no); + } + chained_irq_exit(chip, desc); } From patchwork Thu Feb 7 11:09:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157702 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp530623jaa; Thu, 7 Feb 2019 03:32:31 -0800 (PST) X-Google-Smtp-Source: AHgI3IYBGTJZE6NAIVNKg5XVY7tA3eWEQkqI/quIbdTACrl65g7sKxn6tjrDJ/QfEN2KYwEaz3WI X-Received: by 2002:a62:9f92:: with SMTP id v18mr15731807pfk.154.1549539151497; Thu, 07 Feb 2019 03:32:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549539151; cv=none; d=google.com; s=arc-20160816; b=asy7ouUAGZViHBPubK++/xQZCvOdi8jAkgY5Ke6QC3yzGZ85L1XTFQHQsy+JzbqU2B M3FUyvvH8r+SBV1HWrwNu3R6/OSRRxhQKNWA0Ewz/LDTRY0qUp3Y8GxkbwcHqlhesoON 1eYaxT66rdu6y8i68upta8Rlrn7gg3cxpWy4QX8Ydr7AGELYpXXI5hd+Ns/jdk7OQePm 1dPNjtIMFahvAZryD5ezqUvuiUpTvgYpe9rszT2ivC5cCLn9pkZeY42D2gP4QS3V7Qwo LdKPCvlWqNoMvSICq+9UqxlCMCSA9o5y9+EvZUG9GbKTJU6ygxPoY2qdD/fNkHTD0XZ7 zepg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=EfD/YeSTu2V724ezrxLjWYqdmMyAEeURDfY8l96QaaY=; b=uXx3mQVNgtNbMXdSWSnfGF2EotN+O1DhIHFqfFxr4naF0BhVFyXRZFwVozTKwZ6zph A6WXRMVX8d9j3i1suuNyDUjG4Tsngyj1JKRZ+3zPZeRjUVtD2NYN5/ilC7icDJzOYe7K FVW/tMKzvHYjnZGkY8e7u5NP1HLjIWTppetY0PzP/Ce//kd1OxN+aIAHC7TH7dYYUaI0 you09OcJdJlXS2pkH61RvCiaNo3/jPDBrRsszOsOOg5dzO9nTLj6xvGVuU55woVTDXRV hIwvoTgqiRT5wBYIFdVlXaknrhlVo3+rY81Q0J5eVQgAJMPaQKl58BxzkT7DtxnNna4f KmUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=f3oRCNyl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g31si9049795pld.358.2019.02.07.03.32.31; Thu, 07 Feb 2019 03:32:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=f3oRCNyl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727184AbfBGLc3 (ORCPT + 31 others); Thu, 7 Feb 2019 06:32:29 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54038 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727091AbfBGLcX (ORCPT ); Thu, 7 Feb 2019 06:32:23 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x17BWCQ0085491; Thu, 7 Feb 2019 05:32:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549539132; bh=EfD/YeSTu2V724ezrxLjWYqdmMyAEeURDfY8l96QaaY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f3oRCNylVOuFaEFS4RDevoKwGV30QZkPX9bODfZYyzxRYRvbxbQJYk6lLJh6jjoli 0N5XK5yQrVN9gVCJVMBde7lyfQ071RHIbF+sLG+3+Lx3xq2IhUG1J2FW7gYLjrHRYD J67aZef1MyWtQY2YfbJlWGnoCm2F/gVl8LOgISwE= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x17BWCeQ067521 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Feb 2019 05:32:12 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 7 Feb 2019 05:32:12 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 7 Feb 2019 05:32:12 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x17BVxan026282; Thu, 7 Feb 2019 05:32:09 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v2 3/9] PCI: keystone: Add separate functions for configuring MSI and legacy interrupt Date: Thu, 7 Feb 2019 16:39:18 +0530 Message-ID: <20190207110924.30716-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190207110924.30716-1-kishon@ti.com> References: <20190207110924.30716-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ks_pcie_get_irq_controller_info() was used to configure both MSI and legacy interrupt. This will prevent MSI or legacy interrupt specific intializations. Add separate functions to configure MSI and legacy interrupts. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 188 +++++++++++----------- 1 file changed, 96 insertions(+), 92 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 4cf9849d5a1d..b1d01751c1af 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -87,11 +87,8 @@ struct keystone_pcie { struct dw_pcie *pci; /* PCI Device ID */ u32 device_id; - int num_legacy_host_irqs; - int legacy_host_irqs[PCI_NUM_INTX]; struct device_node *legacy_intc_np; - int num_msi_host_irqs; int msi_host_irqs[MAX_MSI_HOST_IRQS]; int num_lanes; u32 num_viewport; @@ -201,14 +198,6 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp) return dw_pcie_allocate_domains(pp); } -static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) -{ - int i; - - for (i = 0; i < PCI_NUM_INTX; i++) - ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), 0x1); -} - static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset) { @@ -490,17 +479,6 @@ static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie) ks_pcie->app = *res; - /* Create legacy IRQ domain */ - ks_pcie->legacy_irq_domain = - irq_domain_add_linear(ks_pcie->legacy_intc_np, - PCI_NUM_INTX, - &ks_pcie_legacy_irq_domain_ops, - NULL); - if (!ks_pcie->legacy_irq_domain) { - dev_err(dev, "Failed to add irq domain for legacy irqs\n"); - return -EINVAL; - } - return dw_pcie_host_init(pp); } @@ -624,85 +602,117 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie, - char *controller, int *num_irqs) +static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) { - int temp, max_host_irqs, legacy = 1, *host_irqs; struct device *dev = ks_pcie->pci->dev; - struct device_node *np_pcie = dev->of_node, **np_temp; - - if (!strcmp(controller, "msi-interrupt-controller")) - legacy = 0; - - if (legacy) { - np_temp = &ks_pcie->legacy_intc_np; - max_host_irqs = PCI_NUM_INTX; - host_irqs = &ks_pcie->legacy_host_irqs[0]; - } else { - np_temp = &ks_pcie->msi_intc_np; - max_host_irqs = MAX_MSI_HOST_IRQS; - host_irqs = &ks_pcie->msi_host_irqs[0]; - } + struct device_node *np = ks_pcie->np; + struct device_node *intc_np; + int irq_count; + int irq; + int ret; + int i; - /* interrupt controller is in a child node */ - *np_temp = of_get_child_by_name(np_pcie, controller); - if (!(*np_temp)) { - dev_err(dev, "Node for %s is absent\n", controller); - return -EINVAL; - } + if (!IS_ENABLED(CONFIG_PCI_MSI)) + return 0; - temp = of_irq_count(*np_temp); - if (!temp) { - dev_err(dev, "No IRQ entries in %s\n", controller); - of_node_put(*np_temp); + intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); + if (!intc_np) { + dev_WARN(dev, "msi-interrupt-controller node is absent\n"); return -EINVAL; } - if (temp > max_host_irqs) - dev_warn(dev, "Too many %s interrupts defined %u\n", - (legacy ? "legacy" : "MSI"), temp); + irq_count = of_irq_count(intc_np); + if (!irq_count) { + dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); + ret = -EINVAL; + goto err; + } - /* - * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to - * 7 (MSI) - */ - for (temp = 0; temp < max_host_irqs; temp++) { - host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp); - if (!host_irqs[temp]) - break; + if (irq_count > MAX_MSI_HOST_IRQS) { + dev_warn(dev, "Too many MSI interrupt lines defined %u\n", + irq_count); + irq_count = MAX_MSI_HOST_IRQS; } - of_node_put(*np_temp); + for (i = 0; i < irq_count; i++) { + irq = irq_of_parse_and_map(intc_np, i); + if (!irq) { + ret = -EINVAL; + goto err; + } + ks_pcie->msi_host_irqs[i] = irq; - if (temp) { - *num_irqs = temp; - return 0; + irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, + ks_pcie); } - return -EINVAL; + of_node_put(intc_np); + return 0; + +err: + of_node_put(intc_np); + return ret; } -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) +static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) { + struct device *dev = ks_pcie->pci->dev; + struct irq_domain *legacy_irq_domain; + struct device_node *np = ks_pcie->np; + struct device_node *intc_np; + int irq_count; + int irq; + int ret; int i; - /* Legacy IRQ */ - for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) { - irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i], + intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); + if (!intc_np) { + dev_WARN(dev, "legacy-interrupt-controller node is absent\n"); + return -EINVAL; + } + + irq_count = of_irq_count(intc_np); + if (!irq_count) { + dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); + ret = -EINVAL; + goto err; + } + + for (i = 0; i < irq_count; i++) { + irq = irq_of_parse_and_map(intc_np, i); + if (!irq) { + ret = -EINVAL; + goto err; + } + irq_set_chained_handler_and_data(irq, ks_pcie_legacy_irq_handler, ks_pcie); } - ks_pcie_enable_legacy_irqs(ks_pcie); - - /* MSI IRQ */ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) { - irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i], - ks_pcie_msi_irq_handler, - ks_pcie); - } + + legacy_irq_domain = + irq_domain_add_linear(intc_np, PCI_NUM_INTX, + &ks_pcie_legacy_irq_domain_ops, NULL); + if (!legacy_irq_domain) { + dev_err(dev, "Failed to add irq domain for legacy irqs\n"); + ret = -EINVAL; + goto err; } + ks_pcie->legacy_irq_domain = legacy_irq_domain; + + for (i = 0; i < PCI_NUM_INTX; i++) + ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); + + of_node_put(intc_np); + + return 0; + +err: + of_node_put(intc_np); + return ret; +} +static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) +{ if (ks_pcie->error_irq > 0) ks_pcie_enable_error_irq(ks_pcie); } @@ -756,6 +766,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); int ret; + ret = ks_pcie_config_legacy_irq(ks_pcie); + if (ret) + return ret; + + ret = ks_pcie_config_msi_irq(ks_pcie); + if (ret) + return ret; + dw_pcie_setup_rc(pp); ks_pcie_establish_link(ks_pcie); @@ -805,20 +823,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct device *dev = &pdev->dev; int ret; - ret = ks_pcie_get_irq_controller_info(ks_pcie, - "legacy-interrupt-controller", - &ks_pcie->num_legacy_host_irqs); - if (ret) - return ret; - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - ret = ks_pcie_get_irq_controller_info(ks_pcie, - "msi-interrupt-controller", - &ks_pcie->num_msi_host_irqs); - if (ret) - return ret; - } - /* * Index 0 is the platform interrupt for error interrupt * from RC. This is optional. From patchwork Thu Feb 7 11:09:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157704 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp530807jaa; Thu, 7 Feb 2019 03:32:42 -0800 (PST) X-Google-Smtp-Source: AHgI3IaizCGx2FeeenrgCsyWPsIVdmMGsfNsHVfHc6XmJ3AwZKINAcrvySLM00W+/xia3xtjxBiB X-Received: by 2002:a62:32c4:: with SMTP id y187mr16144667pfy.195.1549539162021; Thu, 07 Feb 2019 03:32:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549539162; cv=none; d=google.com; s=arc-20160816; b=y3m1qqiFTcZSZpvXJLFrYTPY0dk5eFWFN2AvmjhAFMrTJ9Ate58WDzbBJr6rqhEEQj maAmXaolCGW/eC0S6IWmnyRoCCoUNHGIxbIOHLu3T7pc8Bx5LAwTa1UIlEsshqQUZsta ijHWvkNXpSjJ0NasWvmlJ78pPy4CxOxcNq7E3Cazy61j9UFK0ILaOU1HCWn1/m24gsz7 kPmAY+bT9icsfzCmLYuQ72TNNeks20IkksLqcrslc/j3aSrif1CsbwFnki+ncNEgD7OM hAc5a8MQ0RwaqYuVas9wC95365/lTDiHoLvL57/ZbMfHFKV4wv+dcngQcXfIrmj3qyCi ITiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=hDnQR6WIzJqxZvFm5EvH1nkw9aQ+DyUIIB3b8SxGyWA=; b=fq4XChDjFlaZwYDHoCHmZZc8P6qB8ycX/8pGK/7sXdmUcrFwnc6421V/OLinBvzIS4 W0NMwTAL7+9H9NQkW+ZDda7VcMPX3z3SvUGkig2N8/sX1oqBjxfbgHCaHw+Kb3PtkikB u1LjnL0RPuTOD8cjIepOmI2iAl2RB+U7jZ2GAfxMX7GTtQBS2/uPReh5w6QyYGM6UWAl Gpw6qU5cTaclia0KwhQlD94Ssrv/7DAk9g4kc2gyAapFzvNPqTfe/2SGOfe4bx2HWXni ciQR2o0uIsn7uZuhTy9vQKeC9L7D+of+styQOo9Rft/2RrVRIi+iErxMVA7+QmOGQy5V P3iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Fx7uHaxw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 12si8944624pfx.102.2019.02.07.03.32.41; Thu, 07 Feb 2019 03:32:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Fx7uHaxw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727188AbfBGLcf (ORCPT + 31 others); Thu, 7 Feb 2019 06:32:35 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:46048 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726579AbfBGLc2 (ORCPT ); Thu, 7 Feb 2019 06:32:28 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x17BWFwV030934; Thu, 7 Feb 2019 05:32:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549539135; bh=hDnQR6WIzJqxZvFm5EvH1nkw9aQ+DyUIIB3b8SxGyWA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Fx7uHaxwY8cTuhb0luiuIft+GR057u2kiD9kJurFsoD+dvnAhuF20392/asVBsQHQ G7oOu3CRqfWfkLWtuen7zDMtDmVzT7ZgAyzPiXjRvfwdZoq9fZcKSxcck9QHKinzAZ +wMJO9JgQ7X0vny9UhsU3y5wrVMSB+pDlp49yv2k= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x17BWFB2017077 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Feb 2019 05:32:15 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 7 Feb 2019 05:32:15 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 7 Feb 2019 05:32:15 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x17BVxao026282; Thu, 7 Feb 2019 05:32:12 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v2 4/9] PCI: keystone: Use hwirq to get the IRQ number offset Date: Thu, 7 Feb 2019 16:39:19 +0530 Message-ID: <20190207110924.30716-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190207110924.30716-1-kishon@ti.com> References: <20190207110924.30716-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ks_pcie_msi_irq_handler() uses 'virq' to get the IRQ number offset. This offset is used to get the correct MSI_IRQ_STATUS register corresponding to the IRQ line that raised the interrupt. There is no guarantee that 'virq' assigned for consecutive hardware IRQ will be contiguous. And this might get us an incorrect IRQ number offset. Fix it here by using 'hwirq' to get the IRQ number offset. Since we don't store the 'virq' numbers of all the IRQ numbers, stop checking if irq count is greater than MAX_MSI_HOST_IRQS and remove MAX_MSI_HOST_IRQS. Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d838c@arm.com Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 24 ++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b1d01751c1af..a404fad12bdf 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -74,7 +74,6 @@ #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ ERR_NONFATAL | ERR_FATAL | ERR_SYS) -#define MAX_MSI_HOST_IRQS 8 /* PCIE controller device IDs */ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 @@ -89,7 +88,7 @@ struct keystone_pcie { u32 device_id; struct device_node *legacy_intc_np; - int msi_host_irqs[MAX_MSI_HOST_IRQS]; + int msi_host_irq; int num_lanes; u32 num_viewport; struct phy **phy; @@ -547,9 +546,9 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); + unsigned int irq = desc->irq_data.hwirq; struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); - u32 offset = irq - ks_pcie->msi_host_irqs[0]; + u32 offset = irq - ks_pcie->msi_host_irq; struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -607,6 +606,7 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) struct device *dev = ks_pcie->pci->dev; struct device_node *np = ks_pcie->np; struct device_node *intc_np; + struct irq_data *irq_data; int irq_count; int irq; int ret; @@ -628,19 +628,21 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) goto err; } - if (irq_count > MAX_MSI_HOST_IRQS) { - dev_warn(dev, "Too many MSI interrupt lines defined %u\n", - irq_count); - irq_count = MAX_MSI_HOST_IRQS; - } - for (i = 0; i < irq_count; i++) { irq = irq_of_parse_and_map(intc_np, i); if (!irq) { ret = -EINVAL; goto err; } - ks_pcie->msi_host_irqs[i] = irq; + + if (!ks_pcie->msi_host_irq) { + irq_data = irq_get_irq_data(irq); + if (!irq_data) { + ret = -EINVAL; + goto err; + } + ks_pcie->msi_host_irq = irq_data->hwirq; + } irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, ks_pcie); From patchwork Thu Feb 7 11:09:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157705 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp530866jaa; Thu, 7 Feb 2019 03:32:44 -0800 (PST) X-Google-Smtp-Source: AHgI3IYNLyQ3I6Urny28Vy9ZJaS6P5AGPSktjPum2RT9o5yuk+Ll2MoIkuXjfBMoujRLGBRQNKbP X-Received: by 2002:a17:902:2be8:: with SMTP id l95mr12691993plb.270.1549539164830; Thu, 07 Feb 2019 03:32:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549539164; cv=none; d=google.com; s=arc-20160816; b=BAv8KuSItHN2iDQMl3fNxPgaq8Whu554ZLpVyXeiA8ZN5SVy/1W/FZPDSq2zDHUQ/6 ek3UY3jq8IDxpfDgJiuilYcwJ0J1pj7fu4KOp7QBgK1QwPR9RtEQLQud/G0GUN4rFpAy h+lM11nQ/YKMM3xn/R5PFxlVFmnQa36MBQYyk4tQF/Jj8SrGe2RH9nt2JXwzwO1oWKfx e0/HFAx9eXEhUDX7CUrqnIHayaDCtEKDfrfmW1mvVfQ1G0NxLsqFl7CZwWHdLuMb/Nbe l/XppZtDb8LIC0MwjuDaSqhJpOzEpEykNT5dN8aSib+/S0rkRQ32m+BfS2PW2X9yJIGt PXmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+DNFTCN6kLzsyD8ckIZzKnVQOfpVAB28NIL/3tTQaWQ=; b=JPtZETdXLOEoo2Y0jx/rnXLcKb8CH5yi3242m2lqv+vb8cGuzQNZIkR1uDqYb9PsSc m52FQQkFDG84X/0y8LcYGyRr5AW9kLa3Yzq+DJHAIQISZ+Ad/8x8yHqQQ3+TKYc1KU2g ducGOsDAcjMq1muHtk9gFiSOWVGz3IqfvjPmxG2Q3zLvy7I360VWhefwBMF6iQ9JZfW0 q/IGzWjIyGJWyjWimR7YHcsjm4lxgbGsgdocpw5F0RrFAxQiLkQqtVurk/gnmvSEiRTN 2RbE8QVDd1W6FMJiCAGfFEk2KoSjoxJ/vTbEmAG+Ne7UDBS12WvRzuXOp0QQUbhBgBJg tfiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mKZTPV7K; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Having two functions for handling the interrupt was used when keystone PCIe driver was implemented using two files. But with commit b492aca35c982011500377797d2 ("PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c"), which merged the keystone PCIe driver to use a single file, two functions for handling the interrupt handler is not required. Handle both MSI interrupt and legacy interrupt in a single interrupt handler here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 92 ++++++++++------------- 1 file changed, 39 insertions(+), 53 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index a404fad12bdf..3d1abc99fd08 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -104,13 +104,6 @@ struct keystone_pcie { struct resource app; }; -static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, - u32 *bit_pos) -{ - *reg_offset = offset % 8; - *bit_pos = offset >> 3; -} - static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -130,31 +123,6 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, writel(val, ks_pcie->va_app_base + offset); } -static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - u32 pending, vector; - int src, virq; - - pending = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); - - /* - * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit - * shows 1, 9, 17, 25 and so forth - */ - for (src = 0; src < 4; src++) { - if (BIT(src) & pending) { - vector = offset + (src << 3); - virq = irq_linear_revmap(pp->irq_domain, vector); - dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", - src, vector, virq); - generic_handle_irq(virq); - } - } -} - static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) { u32 reg_offset, bit_pos; @@ -163,7 +131,9 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) pci = to_dw_pcie_from_pp(pp); ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + + reg_offset = irq % 8; + bit_pos = irq >> 3; ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), BIT(bit_pos)); @@ -176,7 +146,9 @@ static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + reg_offset = irq % 8; + bit_pos = irq >> 3; + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), BIT(bit_pos)); } @@ -187,7 +159,9 @@ static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + reg_offset = irq % 8; + bit_pos = irq >> 3; + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), BIT(bit_pos)); } @@ -197,21 +171,6 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp) return dw_pcie_allocate_domains(pp); } -static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, - int offset) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - int virq; - - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); - dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); - generic_handle_irq(virq); - - /* EOI the INTx interrupt */ - ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); -} - static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); @@ -550,8 +509,13 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc) struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); u32 offset = irq - ks_pcie->msi_host_irq; struct dw_pcie *pci = ks_pcie->pci; + struct pcie_port *pp = &pci->pp; struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); + u32 vector; + u32 virq; + u32 reg; + u32 pos; dev_dbg(dev, "%s, irq %d\n", __func__, irq); @@ -561,7 +525,23 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc) * ack operation. */ chained_irq_enter(chip, desc); - ks_pcie_handle_msi_irq(ks_pcie, offset); + + reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); + /* + * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit + * shows 1, 9, 17, 25 and so forth + */ + for (pos = 0; pos < 4; pos++) { + if (!(reg & BIT(pos))) + continue; + + vector = offset + (pos << 3); + virq = irq_linear_revmap(pp->irq_domain, vector); + dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", pos, vector, + virq); + generic_handle_irq(virq); + } + chained_irq_exit(chip, desc); } @@ -581,6 +561,7 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int irq_no; + u32 virq; u32 reg; dev_dbg(dev, ": Handling legacy irq %d\n", irq); @@ -595,9 +576,14 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(irq_no)); if (!(reg & INTx_EN)) continue; - ks_pcie_handle_legacy_irq(ks_pcie, irq_no); - } + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, irq_no); + dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", irq_no, virq); + generic_handle_irq(virq); + + /* EOI the INTx interrupt */ + ks_pcie_app_writel(ks_pcie, IRQ_EOI, irq_no); + } chained_irq_exit(chip, desc); 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[209.132.180.67]) by mx.google.com with ESMTP id e68si8870878pfb.101.2019.02.07.03.32.38; Thu, 07 Feb 2019 03:32:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=t+H4kagr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727210AbfBGLch (ORCPT + 31 others); Thu, 7 Feb 2019 06:32:37 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:46074 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726782AbfBGLce (ORCPT ); Thu, 7 Feb 2019 06:32:34 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x17BWLiQ030967; Thu, 7 Feb 2019 05:32:21 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549539141; bh=bMG5G9sG7SbqYDiuJSnVlAPFQXEkItTlVqc0PM19k0g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=t+H4kagrAHeDiKrBGCxIPLHvvDv2dELqTQ4pDdGTXTyyhswtDHh5ZogaZIjdalhLe 7kc18K7JYVvxagHNUQ7RF7eVwENMDCJPaPTRtJgXLb8ojqHxAHtWlLFWMqDgg5OXrq /EqA6XXlwW6l+Di97L+rs5++KLWWcfdFPkT4Kw8A= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x17BWLOV017119 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Feb 2019 05:32:21 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 7 Feb 2019 05:32:21 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 7 Feb 2019 05:32:21 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x17BVxaq026282; Thu, 7 Feb 2019 05:32:18 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v2 6/9] PCI: dwc: Add support to use non default msi_irq_chip Date: Thu, 7 Feb 2019 16:39:21 +0530 Message-ID: <20190207110924.30716-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190207110924.30716-1-kishon@ti.com> References: <20190207110924.30716-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms using Designware IP uses dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the Designware IP. However certain platforms like Keystone (K2G) which uses Desingware IP has it's own MSI controller logic. For handling such platforms, the irqchip ops uses msi_irq_ack, msi_set_irq, msi_clear_irq callback functions. Add support to use different msi_irq_chip with default as dw_pci_msi_bottom_irq_chip. This is in preparation to get rid off msi_irq_ack, msi_set_irq, msi_clear_irq and other Keystone specific dw_pcie_host_ops. This will also help to get rid of get_msi_addr and get_msi_data ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 721d60a5d9e4..042de09b0451 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -245,7 +245,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, bit + i, - &dw_pci_msi_bottom_irq_chip, + pp->msi_irq_chip, pp, handle_edge_irq, NULL, NULL); @@ -277,6 +277,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + if (!pp->msi_irq_chip) + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 1f56e6ae34ff..95e0c3c93f48 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -176,6 +176,7 @@ struct pcie_port { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; + struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_status[MAX_MSI_CTRLS]; raw_spinlock_t lock; From patchwork Thu Feb 7 11:09:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157707 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp531006jaa; Thu, 7 Feb 2019 03:32:53 -0800 (PST) X-Google-Smtp-Source: AHgI3IZ2K4eifb4qVm9puzhM4hUqbDSUt0RNBrPOVUulWASp4sYUPOYZbtYA7EpkdNd8/+/65Vv4 X-Received: by 2002:a63:d005:: with SMTP id z5mr14346089pgf.64.1549539173907; Thu, 07 Feb 2019 03:32:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549539173; cv=none; d=google.com; s=arc-20160816; b=c+wW1BIst2pPnN+G2GGeh0pEHuV0fPzmmliVwlHw/PXdArEuQyHcnx66ROrERMShck IDEFWhncgrYD03UbbKUsUOh/QJ4+Fq+E36tNEyX6rZNCFkGtIVE4mJjyaYZAFZuPL+Fb fBZb7xMWu55JttPSOE6fJYlhZgV6FMNaJVLSN6PDdKugR7olo5ju/CUtS8+liEfqlfTZ 8E60kKbm9kBC8k5mOOMpMSQzu8KA4k27yMj+sbS/X00RZ+XAqzKRXs60nREBjCvq9tPi QQegQS6jNkzDt57M0YHWi9Mynz93EZFup5t4srvSE14eikVH6MIBMHu0/szKU2mIrqY5 YCQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=mvQ4LuillFqXvxg71gFR7S4jEmgc2bXgTs+yh2AUVNc=; b=bZKTlTyhb3fH7SWo804ppWBi5V78FQhpbUhJjtqYdZYpUE5fI03Fap5Z5oEBVmvXLy I9wg/smeqTvxzaODPkZfX0/OLnixS+SKhJj6UIETivJT6A4YCJHXMK7JFnieaJgJ7OgV QExyl8fv6c7coRZSAgprzpVhl6M/4GLWe8vstNGNtBHxkK19vbV3VdyiIdf1mGHQZxiY KpIWbvCOSmGcjaKrfrACoyx8nhMCgAAj/lgFxgu1R570Rmoq2krTo4qR4RPTOBaNFv2p 9j6SUjzgOt7PvJbGCdxtG4epeZLJJEL83CKIbwzjOuw086QZ2pSzdmN4GqOYpTDlB7gl aa+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FK8eW5io; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m198si9015065pga.98.2019.02.07.03.32.53; Thu, 07 Feb 2019 03:32:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FK8eW5io; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727234AbfBGLcr (ORCPT + 31 others); Thu, 7 Feb 2019 06:32:47 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54102 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726750AbfBGLcp (ORCPT ); Thu, 7 Feb 2019 06:32:45 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x17BWOMF085641; Thu, 7 Feb 2019 05:32:24 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549539144; bh=mvQ4LuillFqXvxg71gFR7S4jEmgc2bXgTs+yh2AUVNc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FK8eW5ioutqHnKVUDUWHBJR5F7uiWnXdT5wT1K9mgHShJ167tG9WW2jMNqhO3ET5F SvxoEewl1RUsUXrheMrSJRsXsEUSHNbr0rulS9IXeJmT0twQnoaUbDrv+BdRC/6/37 BKqHvwpyDUWot7aqsZdGFIcKhMfwd8gS8V+D3D7A= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x17BWOk9017167 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Feb 2019 05:32:24 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 7 Feb 2019 05:32:24 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 7 Feb 2019 05:32:24 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x17BVxar026282; Thu, 7 Feb 2019 05:32:21 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v2 7/9] PCI: keystone: Use Keystone specific msi_irq_chip Date: Thu, 7 Feb 2019 16:39:22 +0530 Message-ID: <20190207110924.30716-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190207110924.30716-1-kishon@ti.com> References: <20190207110924.30716-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use Keystone specific msi_irq_chip to configure the MSI controller logic in the PCIe keystone wrapper instead of using the default Designware msi_irq chip (dw_pci_msi_bottom_irq_chip) with callback functions for configuring the Keystone MSI controller. This will help to remove Keystone specific callback functions added in dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 96 +++++++++++++++++------ 1 file changed, 72 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 3d1abc99fd08..94eb5830967e 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -104,14 +104,6 @@ struct keystone_pcie { struct resource app; }; -static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - - return ks_pcie->app.start + MSI_IRQ; -} - static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) { return readl(ks_pcie->va_app_base + offset); @@ -123,11 +115,14 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, writel(val, ks_pcie->va_app_base + offset); } -static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) +static void ks_pcie_msi_irq_ack(struct irq_data *data) { - u32 reg_offset, bit_pos; + struct pcie_port *pp = irq_data_get_irq_chip_data(data); struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; struct dw_pcie *pci; + u32 reg_offset; + u32 bit_pos; pci = to_dw_pcie_from_pp(pp); ks_pcie = to_keystone_pcie(pci); @@ -140,34 +135,91 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); } -static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) +static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - u32 reg_offset, bit_pos; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + struct dw_pcie *pci; + u64 msi_target; + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); + + msi_target = ks_pcie->app.start + MSI_IRQ; + msg->address_lo = lower_32_bits(msi_target); + msg->address_hi = upper_32_bits(msi_target); + msg->data = data->hwirq; + + dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", + (int)data->hwirq, msg->address_hi, msg->address_lo); +} + +static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static void ks_pcie_msi_mask(struct irq_data *data) +{ + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; + struct dw_pcie *pci; + unsigned long flags; + u32 reg_offset; + u32 bit_pos; + + raw_spin_lock_irqsave(&pp->lock, flags); + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); reg_offset = irq % 8; bit_pos = irq >> 3; - ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), BIT(bit_pos)); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } -static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) +static void ks_pcie_msi_unmask(struct irq_data *data) { - u32 reg_offset, bit_pos; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; + struct dw_pcie *pci; + unsigned long flags; + u32 reg_offset; + u32 bit_pos; + + raw_spin_lock_irqsave(&pp->lock, flags); + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); reg_offset = irq % 8; bit_pos = irq >> 3; - ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), BIT(bit_pos)); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } +static struct irq_chip ks_pcie_msi_irq_chip = { + .name = "KEYSTONE-PCI-MSI", + .irq_ack = ks_pcie_msi_irq_ack, + .irq_compose_msi_msg = ks_pcie_compose_msi_msg, + .irq_set_affinity = ks_pcie_msi_set_affinity, + .irq_mask = ks_pcie_msi_mask, + .irq_unmask = ks_pcie_msi_unmask, +}; + static int ks_pcie_msi_host_init(struct pcie_port *pp) { + pp->msi_irq_chip = &ks_pcie_msi_irq_chip; return dw_pcie_allocate_domains(pp); } @@ -788,11 +840,7 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { .rd_other_conf = ks_pcie_rd_other_conf, .wr_other_conf = ks_pcie_wr_other_conf, .host_init = ks_pcie_host_init, - .msi_set_irq = ks_pcie_msi_set_irq, - .msi_clear_irq = ks_pcie_msi_clear_irq, - .get_msi_addr = ks_pcie_get_msi_addr, .msi_host_init = ks_pcie_msi_host_init, - .msi_irq_ack = ks_pcie_msi_irq_ack, .scan_bus = ks_pcie_v3_65_scan_bus, }; From patchwork Thu Feb 7 11:09:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157706 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp530958jaa; Thu, 7 Feb 2019 03:32:50 -0800 (PST) X-Google-Smtp-Source: AHgI3IbmjfEoCKgwtE8U6brQOAWBAcDr8fqn/fCAdGrBPNmr/J7sKNibykQujqa+choyAVL7+2j3 X-Received: by 2002:a65:47ca:: with SMTP id f10mr14686163pgs.166.1549539170594; Thu, 07 Feb 2019 03:32:50 -0800 (PST) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id m198si9015065pga.98.2019.02.07.03.32.50; Thu, 07 Feb 2019 03:32:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="tLpIty/t"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727253AbfBGLct (ORCPT + 31 others); Thu, 7 Feb 2019 06:32:49 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59780 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726901AbfBGLcp (ORCPT ); Thu, 7 Feb 2019 06:32:45 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x17BWRmB103886; Thu, 7 Feb 2019 05:32:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549539147; bh=Wg8eVVcGkCEzwPn38RuwoHwNSdtUXqnC8EdiJtBZloY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tLpIty/t5r+KKx0kDyOy+7/J5r4HfJqhRu8ssl9lI0ymMf7zzfsBkpxghenvO5tgv lcIHIJdCTnRPf4SoOr3m3k+Vlj9K0H05rKidDoaBVjMfHriXAa8r27kSLPlGG4isR3 v1+Ae7uvSD3oQHJYz3FjYt4GBMeic4NMC7+L2bdc= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x17BWRUF017205 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Feb 2019 05:32:27 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 7 Feb 2019 05:32:27 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 7 Feb 2019 05:32:27 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x17BVxas026282; Thu, 7 Feb 2019 05:32:24 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v2 8/9] PCI: dwc: Remove Keystone specific dw_pcie_host_ops Date: Thu, 7 Feb 2019 16:39:23 +0530 Message-ID: <20190207110924.30716-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190207110924.30716-1-kishon@ti.com> References: <20190207110924.30716-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that Keystone started using it's own msi_irq_chip, remove Keystone specific callback function defined in dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I Acked-by: Gustavo Pimentel --- .../pci/controller/dwc/pcie-designware-host.c | 45 ++++++------------- drivers/pci/controller/dwc/pcie-designware.h | 5 --- 2 files changed, 14 insertions(+), 36 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 042de09b0451..9492b05e8ff0 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -126,18 +126,12 @@ static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); u64 msi_target; - if (pp->ops->get_msi_addr) - msi_target = pp->ops->get_msi_addr(pp); - else - msi_target = (u64)pp->msi_data; + msi_target = (u64)pp->msi_data; msg->address_lo = lower_32_bits(msi_target); msg->address_hi = upper_32_bits(msi_target); - if (pp->ops->get_msi_data) - msg->data = pp->ops->get_msi_data(pp, data->hwirq); - else - msg->data = data->hwirq; + msg->data = data->hwirq; dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", (int)data->hwirq, msg->address_hi, msg->address_lo); @@ -157,17 +151,13 @@ static void dw_pci_bottom_mask(struct irq_data *data) raw_spin_lock_irqsave(&pp->lock, flags); - if (pp->ops->msi_clear_irq) { - pp->ops->msi_clear_irq(pp, data->hwirq); - } else { - ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; + ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; - pp->irq_status[ctrl] &= ~(1 << bit); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, - ~pp->irq_status[ctrl]); - } + pp->irq_status[ctrl] &= ~(1 << bit); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, + ~pp->irq_status[ctrl]); raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -180,17 +170,13 @@ static void dw_pci_bottom_unmask(struct irq_data *data) raw_spin_lock_irqsave(&pp->lock, flags); - if (pp->ops->msi_set_irq) { - pp->ops->msi_set_irq(pp, data->hwirq); - } else { - ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; + ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; - pp->irq_status[ctrl] |= 1 << bit; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, - ~pp->irq_status[ctrl]); - } + pp->irq_status[ctrl] |= 1 << bit; + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, + ~pp->irq_status[ctrl]); raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -209,9 +195,6 @@ static void dw_pci_bottom_ack(struct irq_data *d) dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit); - if (pp->ops->msi_irq_ack) - pp->ops->msi_irq_ack(d->hwirq, pp); - raw_spin_unlock_irqrestore(&pp->lock, flags); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 95e0c3c93f48..ea4b215b605d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -142,14 +142,9 @@ struct dw_pcie_host_ops { int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); int (*host_init)(struct pcie_port *pp); - void (*msi_set_irq)(struct pcie_port *pp, int irq); - void (*msi_clear_irq)(struct pcie_port *pp, int irq); - phys_addr_t (*get_msi_addr)(struct pcie_port *pp); - u32 (*get_msi_data)(struct pcie_port *pp, int pos); void (*scan_bus)(struct pcie_port *pp); void (*set_num_vectors)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); - void (*msi_irq_ack)(int irq, struct pcie_port *pp); }; struct pcie_port { From patchwork Thu Feb 7 11:09:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157708 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp531101jaa; Thu, 7 Feb 2019 03:32:58 -0800 (PST) X-Google-Smtp-Source: AHgI3IaHWji/M07GGEk3N6I3K7PJaYOqyTbYhmGKHLq6nOZTxqP6B0/kzqRQ3zSMlRo3ymEkyG1t X-Received: by 2002:aa7:808f:: with SMTP id v15mr7871851pff.30.1549539178010; Thu, 07 Feb 2019 03:32:58 -0800 (PST) ARC-Seal: i=1; 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Writing to MSI control registers on platforms which doesn't use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses it's own MSI controller logic instead of Designware's MSI controller logic. Signed-off-by: Kishon Vijay Abraham I Acked-by: Gustavo Pimentel --- .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9492b05e8ff0..d7184e1a7d92 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -647,17 +647,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - pp->irq_status[ctrl] = 0; + if (!pp->ops->msi_host_init) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + pp->irq_status[ctrl] = 0; + } } /* Setup RC BARs */