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(89-27-92-210.bb.dnainternet.fi. [89.27.92.210]) by smtp.gmail.com with ESMTPSA id u19-20020a05651220d300b0048a7ef09b22sm2361230lfr.274.2022.08.23.00.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Aug 2022 00:30:10 -0700 (PDT) From: Krzysztof Kozlowski To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sam Protsenko , Krzysztof Kozlowski Subject: [PATCH] arm64: dts: exynos: Add SysMMU nodes for Exynos850 Date: Tue, 23 Aug 2022 10:30:06 +0300 Message-Id: <20220823073006.358764-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Sam Protsenko Add all SysMMU nodes to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220809113323.29965-10-semen.protsenko@linaro.org --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 45 +++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 8e78b50416d8..c61441f3a89a 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -503,6 +503,51 @@ i2c_6: i2c@13890000 { status = "disabled"; }; + sysmmu_mfcmscl: sysmmu@12c50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12c50000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_dpu: sysmmu@130c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x130c0000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_is0: sysmmu@14550000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14550000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_is1: sysmmu@14570000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14570000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_aud: sysmmu@14850000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14850000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; + #iommu-cells = <0>; + }; + sysreg_peri: syscon@10020000 { compatible = "samsung,exynos850-sysreg", "syscon"; reg = <0x10020000 0x10000>;